CN117394861B - TDC unit compatible with spread spectrum and construction method - Google Patents
TDC unit compatible with spread spectrum and construction method Download PDFInfo
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- CN117394861B CN117394861B CN202311697606.0A CN202311697606A CN117394861B CN 117394861 B CN117394861 B CN 117394861B CN 202311697606 A CN202311697606 A CN 202311697606A CN 117394861 B CN117394861 B CN 117394861B
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- 238000001228 spectrum Methods 0.000 title claims abstract description 35
- 238000010276 construction Methods 0.000 title claims abstract description 9
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 4
- 230000001934 delay Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000013139 quantization Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/60—Analogue/digital converters with intermediate conversion to frequency of pulses
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
Abstract
The invention discloses a TDC unit compatible with spread spectrum and a construction method thereof, which are used for a phase-locked loop circuit system, wherein the TDC unit comprises a first delay unit and a second delay unit; the first delay unit is connected in series with the second delay unit, and the two ends of the first delay unit are connected in series with the second delay unit; the first delay unit is composed of a plurality of standard delay circuits; the second delay unit is composed of a plurality of times of difference delay circuits, and the times of difference delay circuits are distributed on two sides of the first delay unit. The first delay unit is used for determining a locked TDC working interval according to the spread spectrum band signal, the loop bandwidth and the loop parameters of the system phase-locked loop. The invention realizes the support of spread spectrum by using a shorter TDC, reduces the number of units and saves the power consumption and the area under the condition of ensuring the required delay value.
Description
Technical Field
The invention relates to the technical field of TDC circuits, in particular to a TDC unit compatible with spread spectrum and a construction method.
Background
In an all-digital phase-locked loop, time-to-digital converter (TDC) is used to convert the phase difference of the input into a digital code value and output. For the existing TDC circuit structure, after the phase-locked loop is locked, the phase change is stable, and the input phase difference of the TDC is small; in a high-performance digital phase locked loop, although there is also an interference source such as noise, the fluctuation of the TDC input phase difference after locking is relatively small.
After general locking, the maximum fluctuation range of the phase-locked loop under the interference of noise and the like under the non-spread spectrum condition does not exceed 4 standard delays. For the purposes of saving area and reducing power consumption, if spreading is not supported, the phase discrimination range supported by the TDC is usually narrower, and only the length of the TDC working in the locking stage is required to be ensured, so that the requirement on the length of the TDC is shorter.
Under the application scene supporting spread spectrum, jitter caused by interference sources such as open noise is removed, and the spread spectrum can cause a fixed relatively large deviation of the TDC input range. Therefore, in the application supporting spread spectrum, after the phase-locked loop is locked under the interference of noise and the like, the actual working interval of the TDC is two sections of working areas relative to the non-spread spectrum condition; the two sections of working areas can cross a section which is hardly used, and the length of the TDC can be obviously increased by the section, so that the phase discrimination range required to be supported by the TDC is larger, and the area and the power consumption of the TDC can be relatively increased.
Disclosure of Invention
In order to solve the problems, the invention provides a spread spectrum compatible TDC unit and a construction method thereof, which combine the phase input characteristics of the spread spectrum TDC with the time difference delay mode, realize the support of the spread spectrum by using a shorter TDC, reduce the power consumption and reduce the area.
The invention provides a TDC unit compatible with spread spectrum, which is used for a phase-locked loop circuit system, and the specific technical scheme is as follows:
the TDC unit comprises a first delay unit and a second delay unit;
the first delay unit and the second delay unit are connected in series, and the second delay unit is connected in series to both ends of the first delay unit;
the first delay unit is composed of a plurality of standard delay circuits;
the second delay unit is composed of a plurality of times of difference delay circuits, and the times of difference delay circuits are distributed on two sides of the first delay unit.
Further, the number of the standard delay circuits forming the first delay unit is not smaller than the number of the standard delay circuits in the maximum fluctuation range of the phase-locked loop under the interference of noise and the like under the non-spread spectrum condition after the phase-locked loop of the system is locked.
Further, the delay difference of the standard delay circuit is 1.
Further, the delay difference of the multiple difference delay circuit is an integer multiple of the delay difference of the standard delay circuit.
Further, the multiple difference delay circuits are distributed on two sides of the first delay unit in a mode of increasing by a multiple of 2.
Further, the delay difference between the head end and the tail end of the TDC unit is the same.
Further, based on the intermediate delay circuits, each delay circuit is distributed in a centrally symmetric architecture according to the delay difference.
The invention also discloses a construction method of the TDC unit compatible with spread spectrum, which comprises the following steps:
s1: acquiring a possible phase jitter range according to the input and output frequency information, the frequency multiplication type, and the loop bandwidth and loop parameters of a system phase-locked loop;
the frequency multiplication type is used for judging whether the input and output frequency information is integral frequency multiplication or decimal frequency multiplication;
s2, determining a working interval of the linear TDC unit after locking according to the phase jitter information and the fluctuation value before locking, and marking the working interval as a first working interval;
s3: constructing a working interval part into a delay unit formed by a plurality of standard delay circuits based on the position of the locked working interval;
s4: and forming a delay unit by a plurality of times of delay circuits taking the delay difference of the standard delay circuit as a reference according to the designed times of delay relation at two ends of the working interval.
Further, the delay difference at both ends of the first working interval is the same.
Further, the linear TDC unit is a TDC unit architecture formed by connecting a plurality of identical standard delay circuits in series.
The beneficial effects of the invention are as follows:
the invention sets the standard delay circuit aiming at the locked working area, sets the multiple difference delay circuit based on the multiple difference of the standard delay circuit at two ends of the working area, reduces the number of units under the condition of ensuring the required delay value, realizes the shorter TDC supporting spread spectrum, reduces the power consumption and simultaneously reduces the area of the device.
Drawings
Fig. 1 is a functional architecture diagram of a TDC unit.
FIG. 2 is a schematic flow chart of the construction method of the present invention.
Fig. 3 is a schematic diagram illustrating the existence of a fixed delay between the output and input under triangular spreading.
Fig. 4 is a schematic diagram illustrating the working section after locking.
Fig. 5 is a schematic diagram illustrating the TDC function.
Fig. 6 is a schematic diagram illustrating the phase discrimination range of the TDC.
Detailed Description
In the following description, the technical solutions of the embodiments of the present invention are clearly and completely described, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In the description of the embodiments of the present invention, it should be noted that, the indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship conventionally put in use of the product of the present invention as understood by those skilled in the art, merely for convenience of describing the present invention and simplifying the description, and is not indicative or implying that the apparatus or element to be referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first," "second," and the like, are used merely for distinguishing between descriptions and not for understanding as indicating or implying a relative importance.
In the description of the embodiments of the present invention, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; may be directly connected or indirectly connected through an intermediate medium. The specific meaning of the above terms in the present invention will be understood in specific cases by those of ordinary skill in the art.
The function of the TDC is described herein as follows;
referring to fig. 5, the TDC is configured to receive two voltage signals V 1 And V 2 The output delay difference Td of (a) is converted into a corresponding digital code value Dout; suppose V 1 And V 2 Input phase difference T D When the conversion parameter delta=5ps of the TDC is=50ps, the digital code value dout=10 of the TDC conversion output can be obtained, and the phase difference of the two voltage signals is known to be 50ps based on the digital code value output by the TDC unit.
As shown in FIG. 6, since the length of the TDC circuit is limited, if the input phase difference is smaller than 0 or larger than T FS The digital code value Dout outputs all 0 s and all 1 s, respectively.
Example 1
The embodiment 1 of the invention discloses a TDC unit compatible with spread spectrum, which is used for a phase-locked loop circuit system, as shown in fig. 1, and the specific technical scheme is as follows:
the TDC unit comprises a first delay unit and a second delay unit;
the first delay unit is connected with the second delay unit in series, and the second delay unit is connected with both ends of the first delay unit in series;
the first delay unit is composed of a plurality of standard delay circuits;
the second delay unit is composed of a plurality of times of difference delay circuits, and the times of difference delay circuits are distributed on two sides of the first delay unit.
The delay difference of the standard delay circuit is 1, wherein the delay difference of 1 represents one unit delay; the standard circuit may employ a set of RC circuits as a delay element. For RC circuits, the delays of the cells are different for different capacitance values. The numbers in fig. 1 represent delay differences, and each block represents a delay circuit corresponding to the delay differences.
In this embodiment, the number of the standard delay circuits forming the first delay unit is not smaller than the number of standard delay circuits in a maximum fluctuation range of the phase-locked loop under noise and other interference under a non-spread spectrum condition after the phase-locked loop of the system is locked.
In particular, inside a high performance phase locked loop, T-based FS Linear TDC unit with delta of 40, delta representing delay difference, T FS Representing the phase discrimination range of the TDC unit, wherein the maximum fluctuation range of the phase-locked loop under the interference of noise and the like is not more than 4 standard delays under the non-spread spectrum condition after locking;
in the present embodiment, the first delay unit is described by a standard delay circuit having 4 delay differences of 1;
the first delay unit is a working interval of the TDC unit, which is input with the phase difference of the TDC under the spread spectrum condition in the phase-locked loop circuit of the current system, and the number of the first delay units is two;
the section spanned between the two working sections and the delay circuit parts at the two ends of the TDC unit are the second delay unit.
In this embodiment, the delay difference between the head end and the tail end of the TDC unit is the same;
the TDC unit is based on intermediate delay circuits, and the delay circuits are distributed in a central symmetrical structure according to the delay difference.
In this embodiment, the delay difference of the multiple difference delay circuit is an integer multiple of the delay difference of the standard delay circuit, and the multiple difference delay circuits are distributed in a manner of increasing by a multiple of 2 on both sides of the first delay unit.
Specifically, as shown in fig. 1, delay circuits with a delay difference of 2 and a delay difference of 4 are respectively disposed outwards at two sides of the first delay unit.
In this embodiment, a delay circuit with a delay difference of 8 is further provided between the two first delay units.
Example 2
The embodiment 2 of the invention also discloses a construction method of the TDC unit compatible with spread spectrum, as shown in fig. 2, and the specific process is as follows:
s1: acquiring a possible phase jitter range according to the input and output frequency information, the frequency multiplication type, and the loop bandwidth and loop parameters of a system phase-locked loop;
the frequency multiplication type is used for judging whether the input and output frequency information is integral frequency multiplication or decimal frequency multiplication;
in this embodiment, triangular spread spectrum is taken as an example for explanation:
as shown in fig. 3, due to different designs of loop bandwidths and loop parameters of different phase-locked loop circuits, the actual response will be slightly different for the input triangular wave signal, but there will be a relatively fixed delay between the output and input control of the design oscillator, and this delay will make the input end of the TDC see a relatively fixed phase difference in two directions;
for a relatively fixed phase difference in these two directions, it is known at which delay circuit the incoming phase difference allows the TDC signal to respond in the spread spectrum case.
S2, determining a working interval of the linear TDC unit after locking according to the phase jitter information and the fluctuation value before locking, and recording the working interval as a first working interval.
The linear TDC unit is a TDC unit framework formed by connecting a plurality of identical standard delay circuits in series;
as shown in fig. 4, in the current spread spectrum, the actual operation region after locking spans a region which is hardly used.
S3: based on the position of the locked working interval, the working interval part is constructed as a delay unit composed of a plurality of standard delay circuits.
S4: and forming delay units by using a plurality of times of delay circuits with delay differences of the standard delay circuits as reference according to the designed times of delay relation distribution at two ends of the first working interval.
The delay difference at the two ends of the first working interval is the same, and the deterioration of quantization error is not caused.
The multiple difference relation of the delay differences between the multiple difference delay circuits is designed according to the position of the locked first interval, so that the delay differences at two ends of the first working interval are identical, the multiple difference relation distribution of the multiple difference delay circuits of the continuous section is identical, the specific multiple differences of the delay differences between the multiple difference delay circuits are designed according to actual conditions, and the method is not particularly limited.
Specifically, as shown in fig. 1, in the present embodiment, four standard delay circuits with a delay difference of 1 are provided in the first operation section, and delay circuits with a delay difference of 2 and a delay difference of 4 are provided at both ends of the first operation section.
In this embodiment, step S5 further includes determining whether a delay difference between the two working intervals is greater than a delay difference delay circuit between two ends of the first working interval according to a span between the two first working intervals and a delay difference between the delay circuits between two ends of the first working intervals, and if so, setting the delay difference delay circuit between the two working intervals based on the designed TDC unit.
Specifically, in this embodiment, a delay circuit with a delay difference of 8 is provided in the middle portion of the two operation sections.
Based on the constructed TDC unit, under the spread spectrum condition, the first working interval is a spread spectrum working interval, and the delay unit with double difference is utilized in the middle of two sections of spread spectrum working intervals, so that the required delay value is realized while the number of units is reduced.
The invention is not limited to the specific embodiments described above. The invention extends to any novel one, or any novel combination, of the features disclosed in this specification, as well as to any novel one, or any novel combination, of the steps of the method or process disclosed.
Claims (7)
1. A spread-spectrum compatible TDC unit for phase-locked loop circuitry, the TDC unit comprising a first delay unit and a second delay unit;
the first delay units are connected in series with the second delay units, and the first delay units are arranged between the second delay units;
the first delay unit is composed of a plurality of standard delay circuits;
the second delay unit is composed of a plurality of multiple difference delay circuits, and the multiple difference delay circuits are distributed on two sides of the first delay unit;
the delay difference of the standard delay circuit is 1, the delay difference of the standard delay circuit is 1 to represent one unit delay, the standard delay circuit can adopt a group of RC circuits as one delay unit, and the delay difference of the multiple difference delay circuit is an integral multiple of the delay difference of the standard delay circuit;
the construction of the spread spectrum compatible TDC unit is as follows:
s1: acquiring a phase jitter range according to the input and output frequency information, the frequency multiplication type, and the loop bandwidth and loop parameters of a system phase-locked loop;
s2: determining a working interval after locking of the linear TDC unit according to the phase jitter information and the fluctuation value before locking, and marking the working interval as a first working interval;
s3: constructing a working interval part into a delay unit formed by a plurality of standard delay circuits based on the position of the locked working interval;
s4: and forming a delay unit by a plurality of times of delay circuits taking the delay difference of the standard delay circuit as a reference according to the designed times of delay relation at two ends of the working interval.
2. The spread compatible TDC unit of claim 1, wherein the number of standard delay circuits constituting the first delay unit is not less than the number of standard delay circuits within a maximum fluctuation range of the phase locked loop under noise interference in a non-spread case after the system phase locked loop is locked.
3. The spread-compatible TDC unit of claim 1, wherein the multiple difference delay circuits are distributed in increments of a multiple of 2 on both sides of the first delay unit.
4. A spread spectrum compatible TDC unit according to any one of claims 1-3, characterized in that the delay difference of the head end and the tail end of the TDC unit is the same.
5. The spread spectrum compatible TDC unit of claim 4, wherein each delay circuit is distributed in a centrally symmetric architecture according to a delay difference based on an intermediate delay circuit.
6. The spread spectrum compatible TDC unit of claim 1, wherein the delay difference at both ends of the first operating interval is the same.
7. The spread spectrum compatible TDC unit of claim 1, wherein the linear TDC unit is a TDC unit architecture formed of several identical standard delay circuits connected in series.
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Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1956714A1 (en) * | 2007-02-08 | 2008-08-13 | Stmicroelectronics SA | Method for adding random noise in a time-to-digital converter circuit and circuits for implementing the method |
| CN104237856A (en) * | 2014-09-28 | 2014-12-24 | 贵州航天计量测试技术研究所 | Radar detection signal high-accuracy time-delay generating device and control method |
| EP3035536A1 (en) * | 2014-12-19 | 2016-06-22 | Stichting IMEC Nederland | An ADPLL having a TDC circuit with a dynamically adjustable offset delay |
| KR101765306B1 (en) * | 2016-08-19 | 2017-08-07 | 아주대학교산학협력단 | Fractional frequency multiplying delay locked loop |
| CN107836082A (en) * | 2016-05-17 | 2018-03-23 | 华为技术有限公司 | A kind of time-to-digit converter and digital phase-locked loop |
| CN109302178A (en) * | 2018-08-28 | 2019-02-01 | 上海奥令科电子科技有限公司 | A kind of delay lock loop for frequency multiplier circuit |
| CN111865300A (en) * | 2020-07-08 | 2020-10-30 | 福州大学 | Programmable digital control delay line applied to double-loop delay phase-locked loop |
| CN113196668A (en) * | 2018-12-21 | 2021-07-30 | 英特尔公司 | Adaptive time-to-digital converter and method |
| CN116938251A (en) * | 2023-09-18 | 2023-10-24 | 厦门电科星拓科技有限公司 | Method, circuit and system for improving spread spectrum tracking capability of time-to-digital converter |
| CN117040528A (en) * | 2023-07-25 | 2023-11-10 | 西安电子科技大学芜湖研究院 | Current-type frequency multiplication delay phase-locked loop capable of configuring delay line and configuration method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8344772B2 (en) * | 2009-12-18 | 2013-01-01 | Electronics And Telecommunications Research Institute | Time-to-digital converter and all digital phase-locked loop including the same |
-
2023
- 2023-12-12 CN CN202311697606.0A patent/CN117394861B/en active Active
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1956714A1 (en) * | 2007-02-08 | 2008-08-13 | Stmicroelectronics SA | Method for adding random noise in a time-to-digital converter circuit and circuits for implementing the method |
| CN104237856A (en) * | 2014-09-28 | 2014-12-24 | 贵州航天计量测试技术研究所 | Radar detection signal high-accuracy time-delay generating device and control method |
| EP3035536A1 (en) * | 2014-12-19 | 2016-06-22 | Stichting IMEC Nederland | An ADPLL having a TDC circuit with a dynamically adjustable offset delay |
| CN107836082A (en) * | 2016-05-17 | 2018-03-23 | 华为技术有限公司 | A kind of time-to-digit converter and digital phase-locked loop |
| KR101765306B1 (en) * | 2016-08-19 | 2017-08-07 | 아주대학교산학협력단 | Fractional frequency multiplying delay locked loop |
| CN109302178A (en) * | 2018-08-28 | 2019-02-01 | 上海奥令科电子科技有限公司 | A kind of delay lock loop for frequency multiplier circuit |
| CN113196668A (en) * | 2018-12-21 | 2021-07-30 | 英特尔公司 | Adaptive time-to-digital converter and method |
| CN111865300A (en) * | 2020-07-08 | 2020-10-30 | 福州大学 | Programmable digital control delay line applied to double-loop delay phase-locked loop |
| CN117040528A (en) * | 2023-07-25 | 2023-11-10 | 西安电子科技大学芜湖研究院 | Current-type frequency multiplication delay phase-locked loop capable of configuring delay line and configuration method |
| CN116938251A (en) * | 2023-09-18 | 2023-10-24 | 厦门电科星拓科技有限公司 | Method, circuit and system for improving spread spectrum tracking capability of time-to-digital converter |
Non-Patent Citations (1)
| Title |
|---|
| 非线性优化的时间数字转换器设计;肖远等;微电子学;第53卷(第05期);772-778 * |
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