CN114153136B - Full-period digital-to-time converter based on clock calibration technology - Google Patents
Full-period digital-to-time converter based on clock calibration technology Download PDFInfo
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Abstract
The invention discloses a full-period digital-to-time converter based on a clock calibration technology, which is characterized by comprising a single-slip circuit, a multi-phase clock signal generating unit and a clock signal generating unit, wherein the single-slip circuit is used for converting an input single-ended signal into a differential signal and inputting the differential signal into the multi-phase clock signal generating unit; the multi-phase clock signal generating unit is used for generating multi-phase clock signals according to the input differential signals and inputting the multi-phase clock signals into the adjustable delay module; the adjustable delay module is used for delaying the multiphase clock signal according to the output signal of the digital module and then inputting the multiphase clock signal into the multiplexer; the multi-path selector is used for selecting a group of adjacent two-phase signals to output according to the switch control signal generated by the digital module; the phase interpolator is used for generating a numerical control time signal according to the adjacent two-phase signals; the time-to-digital converter is used for calculating the time difference of the rising edges of the adjacent two-phase signals and inputting the time difference to the digital module; the digital module is used for generating a signal for delay control of the multiphase clock signal and a switch control signal by the adjustable delay module according to the time difference of the rising edges of the adjacent two-phase signals of each group.
Description
Technical Field
The invention belongs to the technical field of radio frequency integrated circuits, relates to a full-period digital-to-time converter, is applied to a polar coordinate or phase difference digital transmitter, clock data recovery, a time domain analog-to-digital converter and the like, and particularly relates to a clock calibration technology for improving the linearity of the full-period digital-to-time converter.
Background
Full-period digital-to-time converters are circuit modules that are commonly used in the field of rf integrated circuit technology. Polar or phase-difference digital transmitters may use a full-period digital-to-time converter as a phase modulator, whose linearity may affect the performance of the transmitter, such as vector magnitude error, adjacent channel ratio, etc. The clock data recovery system may use a full cycle digital-to-time converter as the eye opening detection, the linearity of which may affect the accuracy of the sampling phase and the signal-to-noise ratio of the data signal. The time domain analog-to-digital converter can use a full-period digital-to-time converter as a static calibration, and the linearity of the time domain analog-to-digital converter affects the performance of resolution, signal-to-noise ratio, spurious-free dynamic range and the like. In summary, the linearity of the full-period digital-to-time converter is a very important performance indicator.
As shown in fig. 1, a common implementation of a full-period digital-to-time converter is to first generate a multiphase clock by using a multiphase clock generation circuit, select a two-phase clock by using a multiplexer, and then generate a required phase signal by using a phase interpolator. Chen et al have made an 8-bit Digital-to-time Converter Using a four-divider architecture to generate an eight-Phase clock and a vector-sum type Phase interpolator (m.chen, a.a.afez and c.k.yang, "a 0.1-1.5ghz 8-bit interpolator-Based Digital-to-Phase Converter Using Harmonic reconstruction," in IEEE Journal of Solid-State Circuits, vol.48, no.11, pp.2681-2692, nov.2013.). Sievert et al have made an 11-bit Digital-to-Time Converter, which uses a quad divider and a delay unit to generate a sixteen-phase clock and then uses a charge-charged phase Interpolator (S.Sievert et al, "A2 GHz 244fs-Resolution 1.2ps-Peak-INL Edge Interpolator-Based Digital-to-Time Converter in 28nm CMOS," in IEEE Journal of Solid-State Circuits, vol.51, no.12, pp.2992-3004, dec.2016.). The integral nonlinearity of the existing digital-to-time converter chip has fixed deviation along with a control code due to the error of a multiphase clock, and the integral nonlinearity is reflected in that a large nonlinear error exists at the switching position of the multiphase clock.
In summary, a clock calibration technique is needed to ensure the accuracy of the multi-phase clocks in the digital-to-time converter, so as to improve the overall linearity of the digital-to-time converter.
Disclosure of Invention
In view of the technical problems in the prior art, the present invention provides a full-period digital-to-time converter based on a clock calibration technique.
In order to achieve the purpose, the invention adopts the following technical scheme:
a full-period digital time converter based on a clock calibration technology is characterized by comprising a single slip circuit, a multiphase clock signal generating unit, an adjustable delay module, a digital module, a time-to-digital converter, a multiplexer and a phase interpolator; wherein the content of the first and second substances,
the single-slip circuit is used for converting an input single-ended signal into a differential signal and inputting the differential signal into the multiphase clock signal generating unit;
the multi-phase clock signal generating unit is used for generating multi-phase clock signals according to the input differential signals and inputting the multi-phase clock signals into the adjustable delay module;
the adjustable delay module is used for delaying the multiphase clock signals according to the output signals of the digital module and then inputting the multiphase clock signals into the multiplexer;
the multi-path selector is used for selecting a group of adjacent two-phase signals from the input multiphase clock signals to output according to the switch control signals generated by the digital module;
the phase interpolator is used for generating numerical control time signals according to the adjacent two-phase signals output by the multiplexer;
the time-to-digital converter is used for calculating the time difference of rising edges of adjacent two-phase signals output by the multiplexer and inputting the time difference to the digital module;
and the digital module is used for generating a control signal for delay control of the adjustable delay module on the multiphase clock signal and a switch control signal of the multiplexer according to the time difference of the rising edge of each group of adjacent two-phase signals.
Furthermore, the signal with the leading phase in the two adjacent phase signals is input into the time-to-digital converter after being delayed to enable the rising edge arrival time of the two adjacent phase signals to be similar.
Furthermore, the adjustable delay module includes a plurality of adjustable delay units, an input signal of each adjustable delay unit is connected to an input terminal of a buffer, an output terminal of the buffer is connected to a capacitor of the tunable capacitor array, and the tunable capacitor array is configured to delay the multiphase clock signal according to an output signal of the digital module.
Further, the time-to-digital converter couples the first input signal φ 1 to the first buffer BUF 1 Is connected to the input of a first buffer BUF 1 The output end of the first RC delay array is connected with the input end of the first RC delay array; the time-to-digital converter combines a second input signal phi 2 with a second buffer BUF 2 Is connected to the input of a second buffer BUF 2 The output end of the first RC delay array is connected with the input end of the second RC delay array; first buffer BUF 1 The output signal of (2) is time delayed by a first RC delay array, wherein a resistor R in the first RC delay array n To R 1 Connected in series, a capacitor C n To C 1 The connection is carried out in a parallel mode; capacitor C n To C 1 Are the same, and resistors R are sequentially connected in series from the input end to the output end n To R 1 The values are changed according to R/n, R/(n-1) \ 8230A, R/3, R/2 and R, and are used for generating a series of signals with different rising edge time; second buffer BUF 2 Is connected to a second RC delay array identical to the first RC delay array for sequentially comparing the time edge signals generated by the first RC delay array with the second buffer BUF 2 The output signals are compared with the time edge to obtain a group of output control codes B n To B 0 Representing the time difference between the quantized two-phase signals phi 1 and phi 2.
Further, the phase interpolator is a charge-charging phase interpolator.
The working mode of the full-period digital-to-time converter based on the clock calibration technology is divided into a digital-to-time conversion mode and a clock calibration mode.
In the digital time conversion mode, a single-slip circuit is used for converting an input single-ended signal into a differential signal, a four-frequency divider generates an eight-phase clock signal, a multiplexer selects an adjacent two-phase signal, a digital module generates a switch control signal of the multiplexer, the two-phase signal is connected with a charge-charged phase interpolator, and the digital control time signal is output through an output buffer after being generated. Because the single slip circuit and the quarter-frequency circuit are easily affected by process mismatch and fluctuation, and the precision of the eight-phase clock is limited, the precision of the clock needs to be adjusted through a clock calibration mode.
In the clock calibration mode, the output of the switch-controlled multiplexer is connected to the input of a time-to-digital converter, wherein the leading signal of the two output signals of the multiplexer is subjected to a fixed delay, the fixed delay is a predetermined delay time, and the delay value is required to make the arrival time of the rising edge of the two input signals of the time-to-digital converter as close as possible. The output end of the time-to-digital converter is connected with the input end of the digital module, and the output signals of the digital module after comparison and sequencing operations are used for controlling eight-phase clock delay. The time difference between the eight-phase clocks is reduced and increased through the adjustable delay units of the eight-phase clock signal output buffer stage, the eight-phase clock signals generated by the four frequency dividers are respectively connected with one adjustable delay unit (eight adjustable delay units are needed in total), and the output end of the digital module is respectively connected with each adjustable delay unit and used for controlling the delay of each clock signal. The specific calibration steps are as follows:
(1) The multiplexer selects a first group of adjacent two-phase signals, the time-to-digital converter calculates the time difference of the rising edge between the two signals, and the result is recorded into the register. After completion, the multiplexer selects the next adjacent set of two phase signals.
(2) And (4) repeating the step (1) until the multiplexer traverses eight groups of adjacent two-phase signals, and recording eight groups of time differences.
(3) The eight sets of time differences are compared and if they are all equal, the calibration is complete. Otherwise, sorting the eight groups of time differences in size.
(4) And generating a control signal for controlling the delay of the multiphase clock signal by the adjustable delay unit and a switch control signal of the multiplexer according to the sequencing result, so that the time difference corresponding to the four groups of signals with larger time difference is reduced, and the time difference corresponding to the four groups of signals with smaller time difference is increased.
And then repeating (1) to (4) until the calibration is completed.
The method has low requirement on the linearity of the time-to-digital converter, and only needs to judge the relative size of the time difference, namely only needs to ensure that the relationship between the digital code output after quantization and the input time difference keeps monotone increasing. After the clock precision is ensured, the charge charging type phase interpolator can provide higher linearity, so that the full-period digital-to-time converter based on the clock calibration technology has higher linearity.
Compared with the existing full-cycle digital-to-time converter, the invention has the advantages that the precision of the multiphase clock is obviously improved, and the digital-to-time conversion linearity is better. The invention has the following advantages and positive effects:
1) The linearity is high: the invention can solve the problem of accuracy reduction caused by phase mismatch among multiphase clocks. The phase interpolation is carried out on the premise of ensuring the precision of the multi-phase clock, and the digital time converter with higher linearity can be realized.
2) The scheme is easy to implement: the clock calibration technology of the invention only adds eight units with adjustable delay time and one time-to-digital converter on the basis of the traditional digital time converter, thus having small circuit cost and simple scheme. The method has low requirement on the linearity of the time-to-digital converter, and only needs to ensure that the relationship between the digital code output after quantization and the input time difference keeps monotone increasing; in addition, the time quantization range of the time-to-digital converter only needs to cover the time of multiphase clock mismatch, so the design of the time-to-digital converter is easy to realize.
3) The application range is wide: the full-period digital-to-time converters all need to generate multiphase clock signals, and the clock calibration technology in the invention can be applied to various full-period digital-to-time converters.
Drawings
FIG. 1 is a schematic diagram of a general full-cycle digital-to-time converter;
FIG. 2 is a block diagram of a full-cycle digital-to-time converter based on a clock calibration technique according to an embodiment of the present invention;
FIG. 3 is a circuit diagram of a quad divider and a multiplexer in the clock calibration technique according to an embodiment of the present invention;
FIG. 4 is a circuit diagram of a time-to-digital converter in the clock calibration technique according to an embodiment of the present invention;
fig. 5 is a circuit structure diagram of a charge-charging phase interpolator according to an embodiment of the present invention.
Detailed Description
The present invention will now be described in detail by way of examples with reference to the accompanying figures 2-5.
The embodiment is a 12-bit full-period digital-to-time converter chip based on a clock calibration technology, which is used in a standard CMOS process and has an operating frequency of 1.5 GHz. Fig. 2 shows the overall architecture of the digital-to-time converter, the input signal is a single-ended signal of 6GHz and is connected to the input terminal of the single-slip circuit, the output differential signal is connected to the input terminal of the 4-frequency divider, and the eight-phase clock generated by the 4-frequency divider and passing through the adjustable delay buffer is connected to the input terminal of the 3-bit multiplexer. In normal digital time conversion mode, switch S 1 And S 2 The output of the control multiplexer is connected with the input end of the 9-bit phase interpolator, and 12-bit numerical control time signals are output to control the switching between the normal digital time conversion mode and the clock calibration mode. The output of the multiplexer is connected to the phase interpolator in the normal working mode; in the calibration mode, a calibration feedback loop is accessed. . In clock calibration mode, switch S 1 And S 2 The output of the control multiplexer is connected to the input of the time-to-digital converter, wherein the phase-leading signal is first subjected to a fixed delay. The output end of the time-to-digital converter is connected with the input end of the digital module, and the output signals of the digital module after comparison and sequencing operations are used for controlling eight-phase clock delay. The calibration mode is started only once before the digital time converter chip enters a normal digital time conversion mode, and the control code of the eight-phase clock delay unit is kept unchanged after the digital time converter chip enters the digital time conversion mode.
Fig. 3 is a circuit diagram of a divide-by-four unit, an adjustable delay unit, and a multiplexer according to an embodiment of the present invention. The differential signal of 6GHz is connected with the input end of the four-frequency divider, and the differential signal passes through two D triggers D 1 And D 2 Then 4 frequency division is carried out to generate a signal of 1.5GHz, and a differential signal of 6GHz passes through 8D triggers D 3 To D 10 Resampling the frequency-divided 1.5GHz signal, and generating eight-phase signal phi after resampling the 1.5GHz signal 1 To phi 8 . The eight-phase signal is connected to the multiplexed input through eight adjustable delay units. The input signal of each adjustable delay unit is connected with the input end of a buffer, and the output end of the buffer is connected with the tunable capacitor array. According to the sequencing result in the calibration mode, the control signal of the adjustable delay unit is generated to control the capacitance value of the tunable capacitor array capacitor, increasing the capacitance value can increase the delay time, and decreasing the capacitance value can decrease the delay time. In this way a precise adjustment of the delay time is made. The multiplexing is controlled by 3-bit digital signals, each input signal being controlled by a transmission gate switch.
Fig. 4 is a circuit configuration diagram of the time-to-digital converter in the embodiment of the present invention. Two input signals phi 1 and phi 2 of the time-to-digital converter are respectively coupled to two buffers BUF 1 And BUF 2 And the output end of the buffer is respectively connected with the input ends of the RC delay array 1 and the RC delay array 2. Buffer BUF 1 The output signal of (2) is time-delayed by a series of serially connected resistor-capacitors, resistor R n To R 1 Connected in series by a capacitor C n To C 1 The connection is in parallel. Capacitor C n To C 1 Are of the same magnitude, and the resistance R n To R 1 When the values are changed according to R/n, R/(n-1) \8230andR/3, R/2 and R, the RC delay array generates a series of signals with different rising edge times, and the signals are sequentially delayed by RC time. Buffer BUF 2 Is connected to the same RC delay array 2 as RC delay array 1. The time edge signals generated by the RC delay array 1 are one by one connected with the buffer BUF 2 The output signals are compared with time edges to obtain a group of output control codes B n To B 0 Representing the time difference between the quantized two-phase signals phi 1 and phi 2.
FIG. 5 shows a circuit configuration of a charge-charged phase interpolator according to an embodiment of the present inventionAnd (6) patterning. The resolution of the phase interpolator is 9 bits, two input signals phi of the phase interpolator A And phi B Respectively connected with the output end of the multiplexer, and the phase interpolator comprises 71 phase interpolator units, wherein the charging current of 63 units is eight times of that of the other 8 units. The upper 6 bits and the lower 3 bits are both thermometer code control, and binary code control is between them. The current mirror of the phase interpolator unit is selected to be a common-gate structure, providing a sufficiently large output impedance, whose voltage bias V is X1 ，V X2 And V B Need to be generated by an additional bias circuit. The output ends of the 71 phase interpolator units are connected to the charging capacitor C 1 The output end of the upper polar plate needs a discharge switch S 3 Resetting is performed.
The above-mentioned embodiments are only for illustrating the principles of the technical solutions of the present invention, and should not be used to limit the present invention, and any equivalent changes and modifications made within the spirit and principles of the present invention should fall within the protection scope of the present invention.
Claims (5)
1. A full-period digital time converter based on a clock calibration technology is characterized by comprising a single slip circuit, a multiphase clock signal generating unit, an adjustable delay module, a digital module, a time-to-digital converter, a multiplexer and a phase interpolator; wherein, the first and the second end of the pipe are connected with each other,
the single-slip circuit is used for converting an input single-ended signal into a differential signal and inputting the differential signal into the multiphase clock signal generating unit;
the multiphase clock signal generating unit is used for generating multiphase clock signals according to the input differential signals and inputting the multiphase clock signals to the adjustable delay module;
the adjustable delay module is used for delaying the multiphase clock signals according to the output signals of the digital module and then inputting the multiphase clock signals into the multiplexer;
the multi-path selector is used for selecting a group of adjacent two-phase signals from the input multiphase clock signals to output according to the switch control signals generated by the digital module;
the phase interpolator is used for generating numerical control time signals according to the adjacent two-phase signals output by the multiplexer;
the time-to-digital converter is used for calculating the time difference of the rising edges of the adjacent two-phase signals output by the multiplexer and inputting the time difference to the digital module; the time-to-digital converter combines a first input signal phi 1 with a first buffer BUF 1 Is connected to the input terminal of the first buffer BUF 1 The output end of the first RC delay array is connected with the input end of the first RC delay array; the time-to-digital converter combines the second input signal phi 2 with a second buffer BUF 2 Is connected to the input of a second buffer BUF 2 The output end of the first RC delay array is connected with the input end of the second RC delay array; first buffer BUF 1 The output signal of (a) is subjected to time delay through a first RC delay array; resistor R in first RC delay array n To R 1 Connected in series by a capacitor C n To C 1 The connection is carried out in a parallel connection mode; capacitor C n To C 1 Are the same, and resistors R are sequentially connected in series from the input end to the output end n To R 1 The values are changed according to R/n, R/(n-1) \ 8230A, R/3, R/2 and R, and are used for generating a series of signals with different rising edge time; second buffer BUF 2 Is connected to a second RC delay array identical to the first RC delay array for one-by-one connecting the time edge signals generated by the first RC delay array with the second buffer BUF 2 The output signals are compared with the time edge to obtain a group of output control codes B n To B 0 Representing the time difference between quantized two-phase signals φ 1 and φ 2;
and the digital module is used for generating a control signal for delay control of the adjustable delay module on the multiphase clock signal and a switch control signal of the multiplexer according to the time difference of the rising edges of the adjacent two-phase signals of each group.
2. The full-cycle digitizer as claimed in claim 1, wherein the leading of the two adjacent phase signals is delayed to approximate the arrival time of the rising edge of the two adjacent phase signals before being input into the time-to-digital converter.
3. The full-cycle digital-to-time converter of claim 2, wherein the adjustable delay module comprises a plurality of adjustable delay cells, an input signal of each of the adjustable delay cells being coupled to an input of a buffer, an output of the buffer being coupled to a capacitor of the tunable capacitor array, the tunable capacitor array being configured to delay the multiphase clock signal based on the output signal of the digital module.
4. A full period digital to time converter as claimed in claim 1, 2 or 3 wherein said phase interpolator is a charge-charged phase interpolator.
5. A clock calibration method based on the full-period digital-to-time converter of claim 3, comprising the steps of:
1) The multi-path selector selects a group of adjacent two-phase signals, and the time-to-digital converter calculates the time difference of the rising edges of the currently selected adjacent two-phase signals and records the time difference into the register; then the multi-path selector selects the next group of adjacent two-phase signals;
2) Repeating the step 1) until the multiplexer traverses eight groups of adjacent two-phase signals;
3) The digital module compares the time difference corresponding to each group of adjacent two-phase signals, and if the time differences corresponding to each group of adjacent two-phase signals are equal, the calibration is finished; otherwise, sorting the time difference, and generating a control signal for controlling the delay of the multiphase clock signal by the adjustable delay unit and a switch control signal of the multiplexer according to a sorting result, so that the time difference corresponding to the four groups of signals with larger time difference is reduced, and the time difference corresponding to the four groups of signals with smaller time difference is increased;
4) Repeating the steps 1) to 3) until the calibration is completed.
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| US11619914B2 (en) * | 2021-06-03 | 2023-04-04 | Allegro Microsystems, Llc | Arrayed time to digital converter |
| CN114967411B (en) * | 2022-06-23 | 2024-01-16 | 西北工业大学 | Multi-stage time-to-digital converter with automatic reset mechanism |
| CN116505928B (en) * | 2023-06-28 | 2023-09-22 | 牛芯半导体(深圳)有限公司 | Buffer circuit applied to TX clock |
| CN117555212B (en) * | 2024-01-11 | 2024-04-09 | 深圳市山海半导体科技有限公司 | Time delay module, time-to-digital converter, system and method |
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