CN104467842A - Digital background real-time compensating method for TIADC with reference channel - Google Patents
Digital background real-time compensating method for TIADC with reference channel Download PDFInfo
- Publication number
- CN104467842A CN104467842A CN201410610649.5A CN201410610649A CN104467842A CN 104467842 A CN104467842 A CN 104467842A CN 201410610649 A CN201410610649 A CN 201410610649A CN 104467842 A CN104467842 A CN 104467842A
- Authority
- CN
- China
- Prior art keywords
- adc
- reference channel
- epsiv
- estimated value
- tiadc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
The invention discloses a digital background real-time compensating method for a TIADC with a reference channel. The method is characterized by comprising the following steps that 1, a calibration system of the TIADC with the reference channel is constructed; 2, a clock controller is utilized for sampling external simulation input signals synchronously; 3, a background calibration module carries out error compensation; 4, the reference channel ADC and the TIADC are sampled and converted continuously; 5, the background calibration module carries out difference obtaining calculation; 6, an LMS algorithm is utilized for updating until a stable error estimation value is obtained, and a composite value is output finally. Mismatching errors between TIADC channels can be compensated in real time in a pure digital region, limitation to frequency of input signals is avoided, and the method can be suitable for mismatching error calibration of the TIADC channels with any number of channels.
Description
Technical field
The present invention relates to high speed, high precision analogue switch technology field, specifically a kind of calibration structure to interchannel mismatch error in TIADC and method.
Background technology
Analog to digital converter (Analog-to-Digital Converters, ADC) is in high speed image Video processing, and radio communication, the fields such as digital oscilloscope have a wide range of applications.Along with the operating rate of these equipment is more and more higher, the slew rate requirement for the ADC be applied to wherein is also more and more higher.Now, the single channel ADC of various structure, the performance boundary under existing realization condition is constantly approached in speed and precision two aspect.In order to improve the switching rate of ADC system, a kind of method adopts the time-interleaved mode of multiple ADC to work, and the time-interleaved ADC of the multichannel developed thus (Timing-Interleaved ADC, TIADC) is widely used.But, due to the mismatch of the imbalance mismatch between passage, gain mismatch and sampling instant, seriously limit the dynamic property of TIADC system.
For the mismatch error of TIADC, many schemes are proposed to carry out analysis and the compensation method of various error both at home and abroad, the domestic TIADC time mismatch real-Time Compensation algorithm (Zou Yuexian based on lagrange-interpolation as Zou Yuexian and Zhang Shangliang invention, Zhang Shangliang. a kind of time-interleaved Analog-digital Converter (TIADC) system time mismatch real-Time Compensation algorithm based on lagrange-interpolation. Chinese patent: 200910109487.6, 2009-08-21), Liu Sujuan, a kind of (Liu Sujuan of the method for estimation for TIADC system time error newly of people's inventions such as Wang Junshan, Wang Junshan etc. a kind of method of estimation for TIADC system time error newly. Chinese patent: 201310193800.5, 20132.05.22), the hardware needed for but these algorithms correct and the cost of performance too large, and the limited precision of calibration.The people such as S.Jamal and D.Fu propose to calibrate imbalance mismatch based on random copped wave, based on related operation (correlation-based algorithms), (Jamal Shafiq M is calibrated to gain mismatch and sampling time mismatch, Fu Daihong, Hurst Paul J, Lewis Stephen H.A 10-b 120-Msample/stime-interleaved analog-to-digital converter with digital background calibration [J] .IEEE Journal ofSolid-State Circuits, v 37, n 12, p 1618-1627, December 2002), but this scheme is only applicable to the TIADC of two passages, cannot to more multichannel channel expansion even arbitrarily.The people such as Huawen Jin and Edward Lee propose increase redundant channel to make the randomized method of passage, by spuious for various mismatch error distortion being broken up, improve Spurious Free Dynamic Range (the Huawen Jin of system; Lee, E; Hassoun, M. " Time-interleaved A/D converter with channelrandomization " Proceedings of 1997 IEEE International Symposium on Circuits and Systems (ISCAS) 1997.), but the method can not improve the signal to noise ratio of TIADC system.
Summary of the invention
The weak point that the present invention exists to overcome prior art, the digital backstage real-time compensation method of a kind of TIADC with reference channel is provided, the real-Time Compensation to TIADC interchannel mismatch error can be realized in pure digi-tal territory, frequency input signal is not limited, and the TIADC channel mismatching error calibration of any port number can be applicable to.
The present invention is that technical solution problem adopts following technical scheme:
The feature of the digital backstage real-time compensation method of a kind of TIADC with reference channel of the present invention is carried out as follows:
The calibration system of the TIADC of step 1, structure band reference channel;
The composition of described calibration system comprises: clock controller, the TIADC being with reference channel, background calibration module and data selector unit;
TIADC and the reference channel ADC that the TIADC of described band reference channel is made up of N number of subchannel ADC parallel connection forms;
Background calibration module by mismatch error compensating unit, ask poor unit and the zero type adaptive calibration unit that becomes forms;
Arbitrary subchannel ADC in step 2, described reference channel ADC and TIADC utilizes described clock controller respectively external analog input signal x to be carried out to the sampling of synchronization, and utilizes formula (1) and formula (2) to carry out conversion acquisition reference channel digital signal y respectively
rwith arbitrary subchannel digital signal y
jafter export described background calibration module to;
In formula (1) and formula (2),
with
be respectively the offset error value of described reference channel ADC and the actual offset error value of described arbitrary subchannel ADC; J ∈ [1,2 ... N]; g
rand g
jbe respectively the gain error value of described reference channel ADC and the actual gain error amount of described arbitrary subchannel ADC; Δ t
rwith Δ t
jbe respectively the sampling time error value of described reference channel ADC and the actual samples time error value of described arbitrary subchannel ADC; X' is the first derivative of described external analog input signal x at numeric field;
The mismatch error compensating unit of step 3, described background calibration module receives described reference channel digital signal y
r, arbitrary subchannel digital signal y
j, carry out error compensation, then the output of the output of the reference channel ADC after overcompensation and the described arbitrary subchannel ADC after overcompensation is respectively:
In formula (3),
for the offset error estimated value of reference channel ADC,
for the compensate for poor of reference channel ADC offset error, and have:
the gain error estimated value of reference channel ADC,
for the compensate for poor of the gain error of reference channel ADC, and have:
for the sampling time error estimated value of reference channel ADC, ε
t,rfor the compensate for poor of the sampling time error of reference channel ADC, and have
In formula (4),
for the offset error estimated value of described arbitrary subchannel ADC,
for the compensate for poor of described arbitrary subchannel ADC offset error, and have:
for the gain error estimated value of described arbitrary subchannel ADC, ε
g,jfor the compensate for poor of the gain error of arbitrary subchannel ADC, and have:
for the sampling time error estimated value of described arbitrary subchannel ADC, ε
t,jfor the compensate for poor of the sampling time error of described arbitrary subchannel ADC, and have
Step 4, with the sampling period
for the time interval, described reference channel ADC and described TIADC is carried out continuously
secondary sampling is also changed, and obtains the reference channel digital signal set after compensating respectively
with the TIADC digital signal set obtained after compensation
poor unit is asked described in exporting to; f
sfor the sample frequency of described TIADC, f
reffor the sample frequency of described reference channel ADC; K>=3;
The poor unit of asking of step 5, described background calibration module receives the set of reference channel digital signal
with the set of TIADC digital signal
and utilize formula (5) to carry out asking difference to calculate, obtain difference set
Step 6, by described difference set
matrix equation shown in substitution formula (6):
Δ=C×E (6)
In formula (6),
E=[E
1e
2e
3]
t, and have:
Step 7, utilize described in the become LMS algorithm of zero type adaptive calibration unit described matrix equation is solved, obtain the offset error estimated value of the reference channel ADC upgraded
gain error estimated value
with sampling time error estimated value
meanwhile, the offset error estimated value of the described arbitrary subchannel ADC upgraded is obtained
gain error estimated value
with sample time error estimated value
and pass to described mismatch error compensating unit;
Step 8, repeat step 4 to step 7, until obtain the offset error estimated value of stable reference channel ADC
gain error estimated value
with sampling time error estimated value
meanwhile, the offset error estimated value of stable described arbitrary subchannel ADC is obtained
gain error estimated value
with sample time error estimated value
and pass to described mismatch error compensating unit, then complete the calibration of the offset error of described arbitrary subchannel ADC, gain error and sampling time error;
Step 9, described data selector unit are to the output valve after received calibration
synthesize, obtain the final output valve D of described TIADC
out.
The feature of the digital backstage real-time compensation method of the time interleaving ADC of band reference channel of the present invention is also,
Described step 7 be utilize formula (10), the LMS algorithm shown in formula (11) and formula (12) carries out iterative computation:
In formula (10), formula (11) and formula (12), k is iterations, k ∈ [1,2 ..., ∞]; u
os, u
gand u
tbe respectively iteration step length offset error estimated value, gain error estimated value and sampling time error estimated value being carried out to iterative computation;
with
be respectively offset error estimated value, gain error estimated value and the sampling time error estimated value previous value in iterative process;
with
offset error estimated value, gain error estimated value and sampling time error estimated value after upgrading respectively.
Compared with prior art, Advantageous Effects of the present invention is embodied in:
1, the present invention extracts based on backstage real-time digital error and compensates, do not need the normal conversion interrupting foreground transducer, adaptively passage imbalance mismatch, gain mismatch and sampling time mismatch are calibrated simultaneously by background calibration module, eliminate the restriction of error over time intersection performance of analog-to-digital convertor, calibration accuracy is high, and calibration is carried out at numeric field completely, do not need the realization changing analog circuit;
2, the present invention's zero type adaptive calibration unit that becomes relies on self-adaptation adjust tactics to carry out filtering operation error parameter just can be made progressively to converge to actual value, algorithm is simple, do not need to calculate relevant correlation function, do not need matrix inversion operation, computation complexity is low, be easy to hardware implementing;
3, the present invention utilizes clock controller realization sample to the alignment successively between the subchannel of reference channel ADC and TIADC and change, calibrate for error and do not limit by port number, the structure proposed and collimation technique have the advantages that the Time-Interleaved ADC Systems to any number of channels is expanded.
Accompanying drawing explanation
Fig. 1 is principle of the invention block diagram;
Fig. 2 is the theory diagram that the present invention is applied in TIADC and 1 the reference channel ADC that 4 passages are formed;
Fig. 3 is each sub-ADC channel sample sequential and reference ADC sampling time sequence figure in Fig. 2;
Fig. 4 a be in Fig. 2 offset error offset with LMS iteration convergence design sketch;
Fig. 4 b be in Fig. 2 gain error offset with LMS iteration convergence design sketch;
Fig. 4 c be in Fig. 2 sampling time error offset with LMS iteration convergence design sketch;
Fig. 5 is the frequency spectrum without the TIADC output signal of calibration in Fig. 2;
Fig. 6 is the frequency spectrum of the TIADC output signal in Fig. 2 after calibration.
Embodiment
In the present embodiment, the digital backstage real-time compensation method of a kind of TIADC with reference channel, control to make reference channel ADC sample to same input signal with each subchannel ADC of TIADC successively and change by precision clock, the difference that such reference channel ADC and sub-ADC export is used in digital backstage and becomes in zero type adaptive calibration algorithm to calculate the interchannel mismatch error estimated value of TIADC, realizes causing the calibration of error to lack of proper care mismatch, gain mismatch and sampling instant mismatch of the real-Time Compensation of each Channel Mismatch and each passage; Concrete, be carry out as follows:
The calibration system of the time interleaving ADC of step 1, structure band reference channel;
As shown in Figure 1, the composition of calibration system comprises: clock controller, the TIADC being with reference channel, background calibration module and output data selector unit;
TIADC and the reference channel ADC that TIADC with reference channel is made up of N number of subchannel ADC parallel connection forms;
Background calibration module by mismatch error compensating unit, ask poor unit and the zero type adaptive calibration unit that becomes forms;
The inventive method to be applied in the TIADC of the sampling rate 400MHz that 4 subchannels are formed, calibrating principle figure as shown in Figure 2.
Determine the subchannel ADC number N=4 forming TIADC, the sampling rate of TIADC is that each subchannel ADC sample frequency of fs=400MHz, TIADC is at fs/4=100MHz.Reference channel ADC sample frequency is fr=fs/M=80MHz, M=5.
Four subchannel ADC that clock controller is TIADC provide four road sampling clock CLK1, CLK2, CLK3, CLK4 difference, spaced 45 ° of sampling clock phase; Clock controller provides sampling clock CLKref for reference channel ADC.
Arbitrary subchannel ADC in step 2, described reference channel ADC and TIADC utilizes described clock controller respectively external analog input signal x to be carried out to the sampling of synchronization, and utilizes formula (1) and formula (2) to carry out conversion acquisition reference channel digital signal y respectively
rwith arbitrary subchannel digital signal y
jafter export described background calibration module to;
In formula (1) and formula (2),
with
be respectively the offset error value of described reference channel ADC and the actual offset error value of described arbitrary subchannel ADC; J ∈ [1,2 ... N]; g
rand g
jbe respectively the gain error value of described reference channel ADC and the actual gain error amount of described arbitrary subchannel ADC; Δ t
rwith Δ t
jbe respectively the sampling time error value of described reference channel ADC and the actual samples time error value of described arbitrary subchannel ADC; X' is the first derivative of described external analog input signal x at numeric field;
By clock controller in this example, reference channel ADC aligns with four subchannel ADC of TIADC successively, specifically as shown in Figure 3.
The mismatch error compensating unit of step 3, described background calibration module receives described reference channel digital signal y
r, arbitrary subchannel digital signal y
j, carry out error compensation, then the output of the output of the reference channel ADC after overcompensation and the described arbitrary subchannel ADC after overcompensation is respectively:
In formula (3),
for the offset error estimated value of reference channel ADC,
for the compensate for poor of reference channel ADC offset error, and have:
the gain error estimated value of reference channel ADC,
for the compensate for poor of the gain error of reference channel ADC, and have:
for the sampling time error estimated value of reference channel ADC, ε
t,rfor the compensate for poor of the sampling time error of reference channel ADC, and have
In formula (4),
for the offset error estimated value of described arbitrary subchannel ADC,
for the compensate for poor of described arbitrary subchannel ADC offset error, and have:
for the gain error estimated value of described arbitrary subchannel ADC,
for the compensate for poor of the gain error of arbitrary subchannel ADC, and have:
for the sampling time error estimated value of described arbitrary subchannel ADC, ε
t,jfor the compensate for poor of the sampling time error of described arbitrary subchannel ADC, and have
Step 4, with the sampling period
for the time interval, described reference channel ADC and described TIADC is carried out continuously
secondary sampling is also changed, and obtains the reference channel digital signal set after overcompensation respectively
with the TIADC digital signal set of acquisition after overcompensation
poor unit is asked described in exporting to; f
sfor the sample frequency of described TIADC, f
reffor the sample frequency of described reference channel ADC; K>=3;
In this example, with sampling period Ts=1/fs for interval, the time is needed to be 20Ts when all 4 subchannel ADC of reference channel ADC and TIADC complete once to align, what comprise offset error, gain error and sampling time error in TIADC system adds up to 15, and we are sampled by continuous 100 times and change output 100 number and reportedly pass and ask poor unit.
The poor unit of asking of step 5, described background calibration module receives the set of reference channel digital signal
with the set of TIADC digital signal
and utilize formula (5) to carry out asking difference to calculate, obtain its difference set
Step 6, by difference set
matrix equation shown in substitution formula (6):
Δ=C×E (6)
In formula (6),
E=[E
1e
2e
3]
t, and have
Step 7, utilize the LMS algorithm of zero type adaptive calibration unit to solve matrix equation (6), obtain the offset error estimated value of the reference channel ADC upgraded
gain error estimated value
with sampling time error estimated value
meanwhile, the offset error estimated value of the described arbitrary subchannel ADC upgraded is obtained
gain error estimated value
with sample time error estimated value
and pass to described mismatch error compensating unit; Concrete,
Utilize formula (10), the LMS algorithm shown in formula (11) and formula (12) carry out iterative computation:
In formula (10), formula (11) and formula (12), k is iterations, k ∈ [1,2 ..., ∞]; u
os, u
gand u
tbe respectively iteration step length offset error estimated value, gain error estimated value and sampling time error estimated value being carried out to iterative computation;
with
be respectively offset error estimated value, gain error estimated value and the sampling time error estimated value previous value in iterative process;
with
offset error estimated value, gain error estimated value and sampling time error estimated value after upgrading respectively.In this example, u
os, u
gand u
tvalue is 2
-12.
Step 8, repeat step 4 to step 7, until reference channel ADC obtains stable offset error estimated value
gain error estimated value
with sampling time error estimated value
meanwhile, described arbitrary subchannel ADC obtains stable offset error estimated value
gain error estimated value
with sample time error estimated value
and pass to described mismatch error compensating unit, then complete the calibration of the offset error of described arbitrary subchannel ADC, gain error and sampling time error;
Fig. 4 a is that offset error offset is with LMS iteration convergence design sketch, Fig. 4 b gain error offset is with LMS iteration convergence design sketch, Fig. 4 c sampling time error offset is with LMS iteration convergence design sketch, can find out after 1000 LMS interative computations, three kinds of error compensation value tend towards stability, now, the mismatch error through between each passage Output rusults of error compensation is calibrated.
Step 9, data selector unit receive the output valve after calibration
synthesize, obtain the final output valve D of described TIADC
out.
Fig. 5 is institute's embodiment system without the output spectrum figure after calibration, can find out, the scattering frequency spectrum having gain mismatch, sampling instant mismatch and imbalance mismatch to cause exists.
Fig. 6 is the output spectrum figure of institute's embodiment system after calibration, can find out, the scattering frequency spectrum that gain mismatch, sampling instant mismatch and imbalance mismatch cause is eliminated.
Claims (2)
1. a digital backstage real-time compensation method of the TIADC with reference channel, is characterized in that carrying out as follows:
The calibration system of the TIADC of step 1, structure band reference channel;
The composition of described calibration system comprises: clock controller, the TIADC being with reference channel, background calibration module and data selector unit;
TIADC and the reference channel ADC that the TIADC of described band reference channel is made up of N number of subchannel ADC parallel connection forms;
Background calibration module by mismatch error compensating unit, ask poor unit and the zero type adaptive calibration unit that becomes forms;
Arbitrary subchannel ADC in step 2, described reference channel ADC and TIADC utilizes described clock controller respectively external analog input signal x to be carried out to the sampling of synchronization, and utilizes formula (1) and formula (2) to carry out conversion acquisition reference channel digital signal y respectively
rwith arbitrary subchannel digital signal y
jafter export described background calibration module to;
In formula (1) and formula (2),
with
be respectively the offset error value of described reference channel ADC and the actual offset error value of described arbitrary subchannel ADC; J ∈ [1,2 ... N]; g
rand g
jbe respectively the gain error value of described reference channel ADC and the actual gain error amount of described arbitrary subchannel ADC; Δ t
rwith Δ t
jbe respectively the sampling time error value of described reference channel ADC and the actual samples time error value of described arbitrary subchannel ADC; X' is the first derivative of described external analog input signal x at numeric field;
The mismatch error compensating unit of step 3, described background calibration module receives described reference channel digital signal y
r, arbitrary subchannel digital signal y
j, carry out error compensation, then the output of the output of the reference channel ADC after overcompensation and the described arbitrary subchannel ADC after overcompensation is respectively:
In formula (3),
for the offset error estimated value of reference channel ADC,
for the compensate for poor of reference channel ADC offset error, and have:
the gain error estimated value of reference channel ADC,
for the compensate for poor of the gain error of reference channel ADC, and have:
for the sampling time error estimated value of reference channel ADC, ε
t,rfor the compensate for poor of the sampling time error of reference channel ADC, and have
In formula (4),
for the offset error estimated value of described arbitrary subchannel ADC,
for the compensate for poor of described arbitrary subchannel ADC offset error, and have:
for the gain error estimated value of described arbitrary subchannel ADC, ε
g,jfor the compensate for poor of the gain error of arbitrary subchannel ADC, and have:
for the sampling time error estimated value of described arbitrary subchannel ADC, ε
t,jfor the compensate for poor of the sampling time error of described arbitrary subchannel ADC, and have
Step 4, with the sampling period
for the time interval, described reference channel ADC and described TIADC is carried out continuously
secondary sampling is also changed, and obtains the reference channel digital signal set after compensating respectively
with the TIADC digital signal set obtained after compensation
poor unit is asked described in exporting to; f
sfor the sample frequency of described TIADC, f
reffor the sample frequency of described reference channel ADC; K>=3;
The poor unit of asking of step 5, described background calibration module receives the set of reference channel digital signal
with the set of TIADC digital signal
and utilize formula (5) to carry out asking difference to calculate, obtain difference set
Step 6, by described difference set
matrix equation shown in substitution formula (6):
Δ=C×E(6)
In formula (6), Δ=[Δ y
1, r 1Δ y
2, r 2Δ y
n,r iΔ y
1, r i+1Δ y
n,r jΔ y
n,r m]
1 × M t;
E=[E
1e
2e
3]
t, and have:
Step 7, utilize described in the become LMS algorithm of zero type adaptive calibration unit described matrix equation is solved, obtain the offset error estimated value of the reference channel ADC upgraded
gain error estimated value
with sampling time error estimated value
meanwhile, the offset error estimated value of the described arbitrary subchannel ADC upgraded is obtained
gain error estimated value
with sample time error estimated value
and pass to described mismatch error compensating unit;
Step 8, repeat step 4 to step 7, until obtain the offset error estimated value of stable reference channel ADC
gain error estimated value
with sampling time error estimated value
meanwhile, the offset error estimated value of stable described arbitrary subchannel ADC is obtained
gain error estimated value
with sample time error estimated value
and pass to described mismatch error compensating unit, then complete the calibration of the offset error of described arbitrary subchannel ADC, gain error and sampling time error;
Step 9, described data selector unit are to the output valve after received calibration
synthesize, obtain the final output valve D of described TIADC
out.
2. the digital backstage real-time compensation method of the time interleaving ADC of band reference channel according to claim 1, it is characterized in that, described step 7 be utilize formula (10), the LMS algorithm shown in formula (11) and formula (12) carries out iterative computation:
In formula (10), formula (11) and formula (12), k is iterations, k ∈ [1,2 ..., ∞]; u
os, u
gand u
tbe respectively iteration step length offset error estimated value, gain error estimated value and sampling time error estimated value being carried out to iterative computation;
with
be respectively offset error estimated value, gain error estimated value and the sampling time error estimated value previous value in iterative process;
with
offset error estimated value, gain error estimated value and sampling time error estimated value after upgrading respectively.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410610649.5A CN104467842A (en) | 2014-11-03 | 2014-11-03 | Digital background real-time compensating method for TIADC with reference channel |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410610649.5A CN104467842A (en) | 2014-11-03 | 2014-11-03 | Digital background real-time compensating method for TIADC with reference channel |
Publications (1)
Publication Number | Publication Date |
---|---|
CN104467842A true CN104467842A (en) | 2015-03-25 |
Family
ID=52913310
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410610649.5A Pending CN104467842A (en) | 2014-11-03 | 2014-11-03 | Digital background real-time compensating method for TIADC with reference channel |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN104467842A (en) |
Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104993827A (en) * | 2015-07-08 | 2015-10-21 | 中国电子科技集团公司第二十四研究所 | Device and method for correcting error estimation of analog-digital converter |
CN104993828A (en) * | 2015-08-13 | 2015-10-21 | 无锡比迅科技有限公司 | Time interleaving analog-digital converter sampling time migration calibration method |
CN106209103A (en) * | 2016-07-29 | 2016-12-07 | 电子科技大学 | TIADC gain based on spectrum analysis and the bearing calibration of time error |
CN106230437A (en) * | 2016-07-29 | 2016-12-14 | 电子科技大学 | A kind of TIADC OFFSET ERROR CORRECTION METHODS based on mathematical statistics |
WO2017219463A1 (en) * | 2016-06-20 | 2017-12-28 | Huawei Technologies Co., Ltd. | Skew detection and correction in time-interleaved analog-to-digital converters |
CN107636971A (en) * | 2015-05-29 | 2018-01-26 | 瑞典爱立信有限公司 | AD converter system |
CN108471313A (en) * | 2018-03-12 | 2018-08-31 | 东南大学 | A kind of TIADC system calibration methods based on digital-to-analogue mixed signal |
CN109361389A (en) * | 2018-09-03 | 2019-02-19 | 北京新岸线移动多媒体技术有限公司 | A kind of timesharing interleaved analog-digital converter multichannel mismatch error calibration method and system |
CN109639278A (en) * | 2018-12-19 | 2019-04-16 | 锐捷网络股份有限公司 | The timing compensation method and device of multichannel time-interleaved AD C |
CN110572249A (en) * | 2019-08-29 | 2019-12-13 | 电子科技大学 | Synchronous automatic calibration method for high-speed TIADC |
CN113759784A (en) * | 2021-09-10 | 2021-12-07 | 国网江苏省电力有限公司淮安供电分公司 | Automatic time compensation correction method and synchronous sampling general module |
CN116318603A (en) * | 2023-05-18 | 2023-06-23 | 合肥灿芯科技有限公司 | Mismatch calibration technology based on data edge detection |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7184908B2 (en) * | 2003-11-28 | 2007-02-27 | Agilent Technologies, Inc. | Calibration method of time measurement apparatus |
CN102291141A (en) * | 2011-04-22 | 2011-12-21 | 合肥工业大学 | Time-interleaved split ADC (Analog-to-Digital Converter) calibration structure without redundant channel and adaptive calibration method thereof |
CN103067006A (en) * | 2012-11-22 | 2013-04-24 | 北京工业大学 | Real-time correction method of time error of time-interleaved analog-digital conversion system |
-
2014
- 2014-11-03 CN CN201410610649.5A patent/CN104467842A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7184908B2 (en) * | 2003-11-28 | 2007-02-27 | Agilent Technologies, Inc. | Calibration method of time measurement apparatus |
CN102291141A (en) * | 2011-04-22 | 2011-12-21 | 合肥工业大学 | Time-interleaved split ADC (Analog-to-Digital Converter) calibration structure without redundant channel and adaptive calibration method thereof |
CN103067006A (en) * | 2012-11-22 | 2013-04-24 | 北京工业大学 | Real-time correction method of time error of time-interleaved analog-digital conversion system |
Cited By (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107636971A (en) * | 2015-05-29 | 2018-01-26 | 瑞典爱立信有限公司 | AD converter system |
CN107636971B (en) * | 2015-05-29 | 2022-03-01 | 瑞典爱立信有限公司 | Analog-to-digital converter system |
US10833693B2 (en) | 2015-05-29 | 2020-11-10 | Telefonaktiebolaget Lm Ericsson (Publ) | Time-interleaved analog-to-digital converter system |
CN104993827B (en) * | 2015-07-08 | 2018-03-02 | 中国电子科技集团公司第二十四研究所 | The devices and methods therefor of analog-digital converter estimation error correction |
CN104993827A (en) * | 2015-07-08 | 2015-10-21 | 中国电子科技集团公司第二十四研究所 | Device and method for correcting error estimation of analog-digital converter |
CN104993828A (en) * | 2015-08-13 | 2015-10-21 | 无锡比迅科技有限公司 | Time interleaving analog-digital converter sampling time migration calibration method |
CN104993828B (en) * | 2015-08-13 | 2019-04-09 | 无锡比迅科技有限公司 | Time-interleaved analog-digital converter sample time offsets calibration method |
WO2017219463A1 (en) * | 2016-06-20 | 2017-12-28 | Huawei Technologies Co., Ltd. | Skew detection and correction in time-interleaved analog-to-digital converters |
CN106209103B (en) * | 2016-07-29 | 2019-09-24 | 电子科技大学 | The bearing calibration of TIADC gain and time error based on spectrum analysis |
CN106209103A (en) * | 2016-07-29 | 2016-12-07 | 电子科技大学 | TIADC gain based on spectrum analysis and the bearing calibration of time error |
CN106230437A (en) * | 2016-07-29 | 2016-12-14 | 电子科技大学 | A kind of TIADC OFFSET ERROR CORRECTION METHODS based on mathematical statistics |
CN106230437B (en) * | 2016-07-29 | 2019-09-24 | 电子科技大学 | A kind of TIADC OFFSET ERROR CORRECTION METHODS based on mathematical statistics |
CN108471313B (en) * | 2018-03-12 | 2021-07-02 | 东南大学 | Digital-analog mixed signal-based TIADC system calibration method |
CN108471313A (en) * | 2018-03-12 | 2018-08-31 | 东南大学 | A kind of TIADC system calibration methods based on digital-to-analogue mixed signal |
CN109361389A (en) * | 2018-09-03 | 2019-02-19 | 北京新岸线移动多媒体技术有限公司 | A kind of timesharing interleaved analog-digital converter multichannel mismatch error calibration method and system |
CN109361389B (en) * | 2018-09-03 | 2022-09-16 | 北京新岸线移动多媒体技术有限公司 | Time-division alternative analog-to-digital converter multi-channel mismatch error calibration method and system |
CN109639278A (en) * | 2018-12-19 | 2019-04-16 | 锐捷网络股份有限公司 | The timing compensation method and device of multichannel time-interleaved AD C |
CN110572249A (en) * | 2019-08-29 | 2019-12-13 | 电子科技大学 | Synchronous automatic calibration method for high-speed TIADC |
CN113759784A (en) * | 2021-09-10 | 2021-12-07 | 国网江苏省电力有限公司淮安供电分公司 | Automatic time compensation correction method and synchronous sampling general module |
CN116318603A (en) * | 2023-05-18 | 2023-06-23 | 合肥灿芯科技有限公司 | Mismatch calibration technology based on data edge detection |
CN116318603B (en) * | 2023-05-18 | 2023-08-22 | 合肥灿芯科技有限公司 | Mismatch calibration technology based on data edge detection |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104467842A (en) | Digital background real-time compensating method for TIADC with reference channel | |
CN102291141B (en) | Time-interleaved split ADC (Analog-to-Digital Converter) calibration structure without redundant channel and adaptive calibration method thereof | |
CN108471313B (en) | Digital-analog mixed signal-based TIADC system calibration method | |
US7394415B2 (en) | Time-interleaved analog-to-digital converter and high speed signal processing system using the same | |
CN108631809B (en) | Multichannel digital TR assembly | |
CN103067006B (en) | A kind of real-time correction method for time-interleaved A/D conversion system time error | |
CN109100755B (en) | Method for correcting group delay distortion of radio frequency front end of high-precision GNSS receiver | |
CN105429642A (en) | Method for extending dynamic range of data acquisition system | |
US9685969B1 (en) | Time-interleaved high-speed digital-to-analog converter (DAC) architecture with spur calibration | |
CN109361390B (en) | Inter-channel sampling time error correction module and method for time-interleaved ADC | |
CN108809310B (en) | Passive time-interleaved SAR ADC-based band-pass Delta-Sigma modulator | |
CN114153136B (en) | Full-period digital-to-time converter based on clock calibration technology | |
CN108432140B (en) | Correction device and method | |
CN105141312A (en) | Digital background calibration algorithm for clock skew in N-channel time-interleaved analog-to-digital converter | |
CN111865331B (en) | Phase calibration method for MWC extended system transfer matrix | |
CN104734711A (en) | Calibration module and calibration method used for interchannel gain errors of TIADC | |
CN110927680B (en) | Broadband receiving digital beam forming method based on digital deskew and frequency domain equalization | |
CN115425972A (en) | Error calibration circuit of high-speed cascade analog-to-digital converter circuit | |
CN113783637B (en) | Radio astronomical signal receiving device with separated sidebands | |
CN103684456A (en) | Method for correcting sampling time mismatch | |
CN108696464B (en) | IQ and 4-channel TIADC combined distortion blind estimation and correction method | |
Yin et al. | Optimization of synthesis filters for hybrid filter bank DACs | |
CN104410417B (en) | A kind of double sampled puppet splits separation structure fast digital calibration algorithm | |
CN113346902A (en) | Full-digital calibration structure based on TIADC composite output and calibration method thereof | |
Yang et al. | A fast TIADC calibration method for 5GSPS digital storage oscilloscope |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
RJ01 | Rejection of invention patent application after publication |
Application publication date: 20150325 |
|
RJ01 | Rejection of invention patent application after publication |