CN117394663A

CN117394663A - Inverter control method and inverter control system

Info

Publication number: CN117394663A
Application number: CN202311319821.7A
Authority: CN
Inventors: 姜真军; 何原明; 柳洲; 章成
Original assignee: Hangzhou Silan Microelectronics Co Ltd
Current assignee: Hangzhou Silan Microelectronics Co Ltd
Priority date: 2023-10-11
Filing date: 2023-10-11
Publication date: 2024-01-12

Abstract

Disclosed are an inverter control method and an inverter control system, the control method comprising: generating a multiphase PWM drive signal; setting a minimum sampling time value; shifting the phase of the PWM drive signal based on the minimum sampling time value; and driving the inverter with the phase-shifted PWM driving signal; in the phase shifting process, the pulse width of the multiphase PWM driving signal is unchanged; after the phase shifting, a time interval between rising edges of relatively leading two-phase drive signals in the multiphase PWM drive signals is greater than or equal to a minimum sampling time value, and a time interval between falling edges of relatively lagging two-phase drive signals in the multiphase PWM drive signals is greater than or equal to the minimum sampling time value.

Description

Inverter control method and inverter control system

Technical Field

The present invention relates to the field of semiconductor technologies, and in particular, to an inverter control method and an inverter control system.

Background

With the rapid development of power electronics technology, three-phase inverter systems using an inverter as a main structure are widely used. The three-phase inverter system is a power electronic system for converting direct current into alternating current by control methods such as SPWM (Sinusoidal Pulse Width Modulation ), SVPWM (Space Vector Pulse Width Modulation, space vector pulse width modulation) and the like, and is widely applied to communication, factory and enterprise uninterruptible power supply systems.

The current detection of the inverter is an important feedback link in the control system, and relates to the vector control performance and the current limiting protection capability of the inverter. The three-phase inversion system needs to accurately obtain three-phase current in the full modulation ratio range so as to adjust the optimal control state of the three-phase inverter in real time.

The existing three-phase inverter control method comprises the following steps: the first is to install an isolated current sensor (e.g. hall sensor) on the phase line of the three-phase inverter, and directly sample the current of the phase line, which has the disadvantage that the cost of the sensor is too high to be acceptable for some cost-effective systems. The second is to install sampling resistors on the lower bridge arm of the three-phase inverter to sample the phase current, and the method has the defects of more sampling channels and larger occupied resources. The third is that the three-phase current is reconstructed by sampling peak current in the DC bus series sampling resistor, because the three-phase current can pass through the DC bus finally, the current of the DC bus can accurately reflect the change of the three-phase current, although the three-phase current can be reconstructed by the method, the sampling channel is less, but the sampling reconstruction area of the three-phase current is too narrow in the range of sector boundary and low modulation ratio, especially in the ultra-low modulation ratio, the effective voltage vector is shorter, and the accurate three-phase current can not be obtained at all.

Disclosure of Invention

In view of the foregoing, an objective of the present invention is to provide an inverter control method and an inverter control system, which can meet the sampling requirement by shifting the phase of the PWM driving signal.

According to an aspect of the present invention, there is provided an inverter control method, wherein the control method includes: generating a multiphase PWM drive signal; setting a minimum sampling time value; shifting the phase of the PWM drive signal based on the minimum sampling time value; and driving the inverter with the phase-shifted PWM driving signal; in the phase shifting process, the pulse width of the multiphase PWM driving signal is unchanged; after the phase shifting, a time interval between rising edges of relatively leading two-phase drive signals in the multiphase PWM drive signals is greater than or equal to a minimum sampling time value, and a time interval between falling edges of relatively lagging two-phase drive signals in the multiphase PWM drive signals is greater than or equal to the minimum sampling time value.

Optionally, the PWM driving signal includes a first phase driving signal, a second phase driving signal, and a third phase driving signal, and the phase shifting method includes: fixing either one of a rising edge and a falling edge of the first phase driving signal, and fixing the other edge of the first phase driving signal based on a timing of the fixed edge of the first phase driving signal and a pulse width of the first phase driving signal; and moving the rising and falling edges of the second and third phase drive signals phase by phase based on the fixed edges of the first phase drive signal.

Optionally, a falling edge of the first phase driving signal is fixed, and a rising edge of the first phase driving signal is fixed based on a timing of the falling edge of the first phase driving signal and a pulse width of the first phase driving signal.

Optionally, the phase shifting method of the second phase driving signal includes: setting a falling edge of the second phase drive signal such that a time interval between a falling edge time of the second phase drive signal and a falling edge time of the first phase drive signal is a minimum sampling time value, and the falling edge of the second phase drive signal is advanced relative to the falling edge of the first phase drive signal, and fixing the falling edge of the second phase drive signal; the rising edge of the second phase drive signal is fixed based on the falling edge time of the second phase drive signal and the pulse width of the second phase drive signal.

Optionally, the phase shifting method of the third phase driving signal includes: comparing rising edge moments of the first phase driving signal and the second phase driving signal, and selecting a phase driving signal with a relatively advanced rising edge of the first phase driving signal and the second phase driving signal as a first reference driving signal; setting the rising edge of the third phase driving signal so that the time interval between the rising edge moment of the third phase driving signal and the rising edge moment of the first reference driving signal is a minimum sampling time value, and the rising edge of the third phase driving signal is advanced relative to the rising edge of the first reference driving signal; comparing the falling edge time of the first phase driving signal and the second phase driving signal, and selecting one phase driving signal with relatively advanced falling edge in the first phase driving signal and the second phase driving signal as a second reference driving signal; comparing the falling edge time of the third phase driving signal with the falling edge time of the second reference driving signal, and directly fixing the rising edge and the falling edge of the third phase driving signal when the falling edge of the third phase driving signal is advanced relative to the falling edge of the second reference driving signal; and when the falling edge of the third phase driving signal lags behind the falling edge of the second reference driving signal, shifting the phase of the third phase driving signal again so that the falling edge of the third phase driving signal is flush with the falling edge of the second reference driving signal, and then fixing the rising edge and the falling edge of the third phase driving signal.

Optionally, a rising edge of the first phase drive signal is fixed, and a falling edge of the first phase drive signal is fixed based on a timing of the rising edge of the first phase drive signal and a pulse width of the first phase drive signal.

Optionally, the phase shifting method of the second phase driving signal includes: setting a rising edge of the second phase drive signal such that a time interval between a rising edge time of the second phase drive signal and a rising edge time of the first phase drive signal is a minimum sampling time value, and the rising edge of the second phase drive signal lags with respect to the rising edge of the first phase drive signal, and fixing the rising edge of the second phase drive signal; the falling edge of the second phase driving signal is fixed based on the rising edge time of the second phase driving signal and the pulse width of the second phase driving signal.

Optionally, the phase shifting method of the third phase driving signal includes: comparing the falling edge moments of the first phase driving signal and the second phase driving signal, and selecting a phase PWM driving signal with relatively lagging falling edge moments in the first phase driving signal and the second phase driving signal as a first reference driving signal; setting a falling edge of the third phase drive signal based on the first reference drive signal such that a time interval between a falling edge time of the third phase drive signal and a falling edge time of the first reference drive signal is a minimum sampling time value, and the falling edge of the third phase drive signal lags with respect to the falling edge of the first reference drive signal; comparing rising edge moments of the first phase driving signal and the second phase driving signal, and selecting a phase driving signal with relatively lagging rising edge moments of the first phase driving signal and the second phase driving signal as a second reference driving signal; comparing rising edge moments of the third phase driving signal and the second reference driving signal, and directly fixing rising edges and falling edges of the third phase driving signal when rising edges of the third phase driving signal lag relative to rising edges of the second reference driving signal; and when the rising edge of the third phase driving signal is advanced relative to the rising edge of the second reference driving signal, shifting the phase of the third phase driving signal again so that the rising edge moment of the third phase driving signal is flush with the rising edge of the second reference driving signal, and then fixing the rising edge and the falling edge of the third phase driving signal.

Optionally, the method further comprises sampling and reconstructing direct current bus current of the inverter.

According to another aspect of the present invention, there is provided an inverter control system including: the control module is used for generating a multiphase PWM driving signal, setting a minimum sampling time value, shifting the phase of the PWM driving signal based on the minimum sampling time value, and driving the inverter by the PWM driving signal after the phase shifting; in the phase shifting process of the phase shifting module, the pulse width of the multiphase PWM driving signal is unchanged; after the phase shifting, a time interval between rising edges of relatively leading two-phase drive signals in the multiphase PWM drive signals is greater than or equal to a minimum sampling time value, and a time interval between falling edges of relatively lagging two-phase drive signals in the multiphase PWM drive signals is greater than or equal to the minimum sampling time value.

Optionally, the PWM drive signal includes a first phase drive signal, a second phase drive signal, and a third phase drive signal, and the control module performs the following steps to phase shift the PWM drive signal: fixing either one of a rising edge and a falling edge of the first phase driving signal, and fixing the other edge of the first phase driving signal based on a timing of the fixed edge of the first phase driving signal and a pulse width of the first phase driving signal; and moving the rising and falling edges of the second and third phase drive signals phase by phase based on the fixed edges of the first phase drive signal.

Optionally, the control module performs the following steps to phase shift the second phase drive signal: setting a falling edge of the second phase drive signal such that a time interval between a falling edge time of the second phase drive signal and a falling edge time of the first phase drive signal is a minimum sampling time value, and the falling edge of the second phase drive signal is advanced relative to the falling edge of the first phase drive signal, and fixing the falling edge of the second phase drive signal; the rising edge of the second phase drive signal is fixed based on the falling edge time of the second phase drive signal and the pulse width of the second phase drive signal.

Optionally, the control module performs the following steps to phase shift the third phase drive signal: comparing rising edge moments of the first phase driving signal and the second phase driving signal, and selecting a phase driving signal with a relatively advanced rising edge of the first phase driving signal and the second phase driving signal as a first reference driving signal; setting the rising edge of the third phase driving signal so that the time interval between the rising edge moment of the third phase driving signal and the rising edge moment of the first reference driving signal is a minimum sampling time value, and the rising edge of the third phase driving signal is advanced relative to the rising edge of the first reference driving signal; comparing the falling edge time of the first phase driving signal and the second phase driving signal, and selecting one phase driving signal with relatively advanced falling edge in the first phase driving signal and the second phase driving signal as a second reference driving signal; comparing the falling edge time of the third phase driving signal with the falling edge time of the second reference driving signal, and directly fixing the rising edge and the falling edge of the third phase driving signal when the falling edge of the third phase driving signal is advanced relative to the falling edge of the second reference driving signal; and when the falling edge of the third phase driving signal lags behind the falling edge of the second reference driving signal, shifting the phase of the third phase driving signal again so that the falling edge of the third phase driving signal is flush with the falling edge of the second reference driving signal, and then fixing the rising edge and the falling edge of the third phase driving signal.

Optionally, the control module performs the following steps to phase shift the second phase drive signal: setting a rising edge of the second phase drive signal such that a time interval between a rising edge time of the second phase drive signal and a rising edge time of the first phase drive signal is a minimum sampling time value, and the rising edge of the second phase drive signal lags with respect to the rising edge of the first phase drive signal, and fixing the rising edge of the second phase drive signal; the falling edge of the second phase driving signal is fixed based on the rising edge time of the second phase driving signal and the pulse width of the second phase driving signal.

Optionally, the control module performs the following steps to phase shift the third phase drive signal: comparing the falling edge moments of the first phase driving signal and the second phase driving signal, and selecting a phase PWM driving signal with relatively lagging falling edge moments in the first phase driving signal and the second phase driving signal as a first reference driving signal; setting a falling edge of the third phase drive signal based on the first reference drive signal such that a time interval between a falling edge time of the third phase drive signal and a falling edge time of the first reference drive signal is a minimum sampling time value, and the falling edge of the third phase drive signal lags with respect to the falling edge of the first reference drive signal; comparing rising edge moments of the first phase driving signal and the second phase driving signal, and selecting a phase driving signal with relatively lagging rising edge moments of the first phase driving signal and the second phase driving signal as a second reference driving signal; comparing rising edge moments of the third phase driving signal and the second reference driving signal, and directly fixing rising edges and falling edges of the third phase driving signal when rising edges of the third phase driving signal lag relative to rising edges of the second reference driving signal; and when the rising edge of the third phase driving signal is advanced relative to the rising edge of the second reference driving signal, shifting the phase of the third phase driving signal again so that the rising edge moment of the third phase driving signal is flush with the rising edge of the second reference driving signal, and then fixing the rising edge and the falling edge of the third phase driving signal.

Optionally, the control module further samples and reconstructs a dc bus current of the inverter.

According to the embodiment of the application, any edge of any phase of PWM driving signal is fixed in the phase shifting process, other edges of the three-phase PWM driving signal gradually and slowly move, gradual change of the edges of the three-phase PWM driving signal is guaranteed, and edge jump caused by phase shifting is avoided.

The three-phase PWM driving signal after phase shifting ensures that the action time of two effective vectors is longer than the shortest sampling time in any PWM period of each sector, so that the three-phase PWM driving signal can meet the requirement of ADC conversion precision, and the sampling accuracy is ensured.

Further, two sampling moments of the method are not continuous, one sampling moment is between falling edges of the PWM driving signal, the other sampling moment is between rising edges of the PWM driving signal, and a time interval between the two sampling moments of the method is increased; the sampling method and the sampling device have the advantages that the sampling is respectively carried out on the falling edge and the rising edge, the sampling is discontinuous for two times, and the conversion time of the ADC does not need to be considered, so that the setting of the minimum sampling window Tmin can be smaller, and the phase shifting mode can be suitable for the working condition with higher modulation ratio, and the application range is wider.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the present invention with reference to the accompanying drawings, in which:

fig. 1 shows a schematic diagram of a sampling loop of an inverter of an embodiment;

FIG. 2 is a vector diagram illustrating a spatial vector pulse width modulation algorithm control scheme;

fig. 3a and 3b show the current reconstruction principle of an inverter of an embodiment in sector 1;

fig. 4a and 4b show the space vector pulse width modulated invisible area, wherein fig. 4a shows the invisible area and fig. 4b shows the low modulation ratio invisible area;

fig. 5 shows a block diagram of an inverter control system of an embodiment of the present application;

fig. 6 shows a flowchart of a PWM driving signal phase shifting method according to a first embodiment of the present application;

fig. 7a and 7b show phase shifting processes of PWM driving signals of the sector 1 to the sector 6 in the first embodiment of the present application;

fig. 8 shows different phase shifting patterns of PWM driving signals of the sector 1 according to the first embodiment of the present application;

fig. 9 shows a flowchart of a PWM driving signal phase shifting method according to a second embodiment of the present application;

fig. 10 shows different phase shifting patterns of PWM driving signals of the sector 1 according to the second embodiment of the present application.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements are denoted by like reference numerals throughout the various figures. For clarity, the various features of the drawings are not drawn to scale. Furthermore, some well-known portions may not be shown.

Numerous specific details of the invention, such as construction, materials, dimensions, processing techniques and technologies, may be set forth in the following description in order to provide a thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

It should be understood that in the following description, "circuit" refers to an electrically conductive loop formed by at least one element or sub-circuit through electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or being "connected between" two nodes, it can be directly coupled or connected to the other element or intervening elements may be present, the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled to" or "directly connected to" another element, it means that there are no intervening elements present between the two.

Fig. 1 shows a schematic diagram of a sampling loop of an inverter according to an embodiment. As shown in fig. 1, the inverter 110 is implemented, for example, by a three-phase inverter, and includes a u-phase leg, a v-phase leg, and a w-phase leg connected in parallel between a positive terminal and a negative terminal of a dc power supply, and each leg is composed of two power switching transistors (for example, power switching transistors T1-T6) connected in series, where the power switching transistors T1-T6 are, for example, selected from IGBTs (Insulated GateBipolar Transistor, insulated gate bipolar transistors) or MOSFETs (Metal-Oxide-semiconductor field-Effect Transistor, metal Oxide semiconductor field effect transistors). Inverter 110 is used for supplying dc power V _DC The provided direct current is converted into three-phase alternating current, and the modulating wave is output by controlling the on and off of the power switching tubes T1-T6, so as to achieve the purpose of driving the three-phase load 120.

The inverter 110 controls the on and off of the power switching tubes on the three-phase bridge arm by control methods such as SPWM (Sinusoidal Pulse Width Modulation ), SVPWM (Space Vector Pulse Width Modulation, space vector pulse width modulation), and DPWM (Discontinuous Pulse Width Modulation ) to convert direct current into alternating current.

The power switching tubes T1-T6 in the inverter 110 are conducted in a complementary and symmetrical manner, that is, at the same time, the upper bridge arm and the lower bridge arm of each phase in the inverter 110 are in a conducting state, and only one power switching tube is in a conducting state, so that PWM driving signals provided to the upper bridge arm and the lower bridge arm of the same phase have a complementary relationship. In the control process of the inverter 110, the power switching tube of the upper bridge arm of each phase is turned on, and the state that the power switching tube of the lower bridge arm is turned off is represented by "1"; the power switching tubes of the upper bridge arm of each phase are cut off, and the state that the power switching tubes of the lower bridge arm are conducted is represented by 0. Then there are eight switching states in total in inverter 110, as shown in table 1 below, comprising six basic voltage vectors V1, V2, V3, V4, V5, and V6, and two zero voltage vectors V0 and V7.

Table 1 space vector pulse width modulation algorithm voltage vector table

Fig. 2 shows a vector diagram of a control scheme of a space vector pulse width modulation algorithm, and as shown in fig. 2, starting points of six basic voltage vectors V1 (100), V2 (110), V3 (010), V4 (011), V5 (001), and V6 (101) are put together to form a radial shape. Further, the tail portions of six basic voltage vectors V1 (100), V2 (110), V3 (010), V4 (011), V5 (001) and V6 (101) may be connected together to form a regular hexagon. The six basic voltage vectors divide a regular hexagon into six sectors, each 60 °.

Fig. 3a and 3b show the current reconstruction principle of an inverter in sector 1 according to an embodiment, wherein fig. 3a shows the dc bus current flow under the action of a basic voltage vector V1 (100), and fig. 3b shows the basic voltage vector V1 (100)The direct current bus current flows under the action of the voltage vector V2 (110). As shown in fig. 3a, under the action of a voltage vector V1 (100), the power switch tube of the upper bridge arm of the u-phase bridge arm of the inverter 110 is turned on, the power switch tube of the lower bridge arm is turned off, the power switch tube of the upper bridge arm of the V-phase bridge arm is turned off, and the power switch tube of the lower bridge arm is turned on; the power switch tube of the upper bridge arm of the w-phase bridge arm is disconnected, and the power switch tube of the lower bridge arm is conducted. DC power supply V _DC And a loop is formed by the upper bridge arm of the u-phase bridge arm, the load 120, the lower bridge arm of the v-phase bridge arm and the lower bridge arm of the w-phase bridge arm which are connected in parallel, and the sampling resistor Rs. In the loop, the phase current is controlled by a DC power supply V _DC The positive end flows out, flows into the load 120 through the upper bridge arm of the u-phase bridge arm, and the current flowing out of the load 120 flows back to the direct current power supply V through the lower bridge arm of the V-phase bridge arm and the lower bridge arm of the w-phase bridge arm which are connected in parallel, and the sampling resistor Rs _DC Negative terminal, at this time, the current I collected by the sampling resistor Rs _BUS Equal to the phase current I flowing through the upper leg of the u-phase leg _U I.e. I _BUS ＝I _U Wherein the current flowing into the load 120 is positive.

As shown in fig. 3b, under the action of the voltage vector V2 (110), the power switch tube of the upper arm of the u-phase arm of the inverter 110 is turned on, the power switch tube of the lower arm is turned off, the power switch tube of the upper arm of the V-phase arm is turned on, and the power switch tube of the lower arm is turned off; the power switch tube of the upper bridge arm of the w-phase bridge arm is disconnected, and the power switch tube of the lower bridge arm is conducted. DC power supply V _DC And a loop is formed by an upper bridge arm of the u-phase bridge arm, an upper bridge arm of the second-phase bridge arm v, a load 120, a lower bridge arm of the w-phase bridge arm and a sampling resistor Rs which are connected in parallel. In the loop, the phase current is controlled by a DC power supply V _DC The positive end flows out, flows into the load 120 through the upper bridge arm of the u-phase bridge arm and the upper bridge arm of the second-phase bridge arm V which are connected in parallel, and the current flowing out of the load 120 flows back to the direct current power supply V through the lower bridge arm of the w-phase bridge arm and the sampling resistor Rs _DC Negative terminal, at this time, the current I collected by the sampling resistor Rs _BUS Equal to the phase current I flowing through the lower leg of the w-phase leg _w I.e. I _BUS ＝-I _w Wherein the current flowing out of the load 120 is negative.

Similarly, a current reconstruction table for each sector of the inverter is obtained, as shown in table 2.

Table 2 space vector pulse width modulation algorithm voltage vector table

The above situation is based on an ideal state, and in a practical situation, the inverter 110 needs a minimum sampling time Tmin as a minimum sampling window to obtain an accurate sampling current. In one period of the PWM drive signal, there is a partial region where the two-phase current cannot be sampled, which is called an invisible region. The invisible area includes a low modulation invisible area and a sector transition invisible area. For convenience of processing, the space voltage vector hexagon is specifically divided into an observable area, a low modulation ratio unobservable area and a sector transition unobservable area. Fig. 4a and 4b show the invisible area, wherein fig. 4a shows the sector transition invisible area and the low modulation ratio invisible area, and fig. 4b shows the low modulation ratio invisible area. As shown in fig. 4b, the low modulation invisible area is because the voltage vector applied to the motor winding is small, and the two effective vector magnitudes for synthesizing the voltage vector have short acting time, so that the sampling requirement cannot be met. As shown in fig. 4a, the invisible area of the sector transition is because the voltage vector far from the boundary has short acting time within a certain range near the boundary of the sector, and cannot meet the sampling requirement.

Based on this, an embodiment of the present invention provides an inverter control system, and fig. 5 shows a structural diagram of the inverter control system according to the embodiment of the present application, and as shown in fig. 5, the inverter control system includes an inverter 210, a motor 220, and a control module 230.

Inverter 210 is implemented, for example, by a three-phase inverter, including a u-phase leg, a v-phase leg, and a w-phase leg connected in parallel between the positive and negative terminals of the dc power supply, each of the legs of the phases being composed of two power switching transistors (e.g., power switching transistors T1-T6), the power switching transistors T1-T6 being, for example, selected from IGBTs (Insulated GateBipolar Transistor, insulated gate bipolar transistors) or MOSFETs (Metal-Oxide-semiconductor field-Effect Transistor, metal Oxide semiconductor field effect transistors). The power switching tubes of the upper bridge arm or the lower bridge arm of each phase are turned on and off based on a space vector pulse width modulation algorithm.

The control module 230 generates the multiphase PWM drive signal, sets a minimum sampling time value Tmin, phase shifts the PWM drive signal based on the minimum sampling time value Tmin, and drives the inverter with the phase-shifted PWM drive signal. The control module 230 changes the edge arrangement of the PWM driving signal by shifting the phase, so as to ensure that the effective vector acting time is greater than or equal to the minimum sampling time Tmin, thereby meeting the sampling requirement. The control module 230 samples the voltage signals at two ends of the sampling resistor connected in series with the negative end of the direct current bus to obtain a current sampling signal, and obtains the phase current of the corresponding phase according to the current sampling signal.

In this embodiment, the PWM driving signal includes a first phase driving signal, a second phase driving signal, and a third phase driving signal, where the first phase driving signal, the second phase driving signal, and the third phase driving signal may be any one phase of a u-phase driving signal, a v-phase driving signal, and a w-phase driving signal, respectively.

The control module 230 performs the following steps to complete the phase shifting of the PWM drive signal:

fixing either one of a rising edge and a falling edge of the first phase driving signal, and fixing the other edge of the first phase driving signal based on a timing of the fixed edge of the first phase driving signal and a pulse width of the first phase driving signal; and

based on the fixed edge of the first phase driving signal, the rising edge and the falling edge of the second phase driving signal and the third phase driving signal are moved phase by phase so as to change the edge arrangement of the PWM driving signal and ensure the effective vector acting time; in the phase shifting process, pulse widths of the first phase driving signal, the second phase driving signal and the third phase driving signal are unchanged.

The time interval between rising edges of the two-phase driving signals, which are relatively advanced in rising edge time of the second phase driving signal and the third phase driving signal, after phase shifting, is greater than or equal to a minimum sampling time value, and the time interval between falling edges of the two-phase driving signals, which are relatively retarded in falling edge time of the first phase driving signal and the second phase driving signal, is greater than or equal to a minimum sampling time value.

Fig. 6 shows a flowchart of a PWM driving signal phase shifting method according to a first embodiment of the present application. As shown in fig. 6, the PWM driving signal phase shifting method of the first embodiment of the present application includes the following steps.

Step S11: fixing a falling edge of the first phase driving signal, and fixing a rising edge of the first phase driving signal based on a time of the falling edge of the first phase driving signal and a pulse width of the first phase driving signal;

step S12: setting the falling edge of the second phase driving signal so that the time interval between the falling edge time of the second phase driving signal and the falling edge time of the first phase driving signal is a minimum sampling time value, leading the falling edge of the second phase driving signal relative to the falling edge of the first phase driving signal, and fixing the falling edge of the second phase driving signal;

step S13: fixing a rising edge of the second phase driving signal based on a falling edge time of the second phase driving signal and a pulse width of the second phase driving signal;

step S14: comparing rising edge moments of the first phase driving signal and the second phase driving signal, and selecting a phase driving signal with relatively advanced rising edges of the first phase driving signal and the second phase driving signal as a first reference driving signal;

Step S15: setting the rising edge of the third phase driving signal so that the time interval between the rising edge time of the third phase driving signal and the rising edge time of the first reference driving signal is a minimum sampling time value, and the rising edge of the third phase driving signal is advanced relative to the rising edge of the first reference driving signal;

step S16: comparing the falling edge time of the first phase driving signal and the second phase driving signal, and selecting one phase driving signal with relatively advanced falling edge in the first phase driving signal and the second phase driving signal as a second reference driving signal;

step S17: comparing the falling edge moments of the third phase driving signal and the second reference driving signal; when the falling edge of the third phase driving signal is advanced relative to the falling edge of the second reference driving signal, directly fixing the rising edge and the falling edge of the third phase driving signal; when the falling edge of the third phase driving signal lags behind the falling edge of the second reference driving signal, the third phase driving signal is phase-shifted again, so that the falling edge of the third phase driving signal is flush with the falling edge of the second reference driving signal, and then the rising edge and the falling edge of the third phase driving signal are fixed.

Fig. 7a and 7b show the phase shifting process of the PWM driving signals of the sectors 1 to 6 in the first embodiment of the present application, wherein fig. 7a is a waveform diagram before the phase shifting of the PWM driving signals of the sectors 1 to 6, and fig. 7b is a waveform diagram after the phase shifting of the PWM driving signals of the sectors 1 to 6. In the phase shifting process shown in fig. 7, the first phase driving signal is, for example, a u-phase driving signal, the second phase driving signal is, for example, a v-phase driving signal, and the third phase driving signal is, for example, a w-phase driving signal. In the phase shifting process, pulse widths of the u-phase driving signal, the v-phase driving signal and the w-phase driving signal are unchanged. The phase shifting method according to the first embodiment of the present application will be specifically described with reference to fig. 7a and 7 b.

In step S11, the falling edge of the u-phase driving signal is fixed, and the rising edge of the u-phase driving signal is fixed based on the timing of the falling edge of the u-phase driving signal and the pulse width of the u-phase driving signal.

Specifically, at the falling edge time T1F of the u-phase driving signal, when the pulse width T1DUTY of the u-phase driving signal is unchanged, the rising edge time T1R of the u-phase driving signal is the falling edge time T1F of the u-phase driving signal minus the pulse width T1DUTY of the u-phase driving signal, that is, t1r=t1f-T1 DUTY.

In step S12, the falling edge of the v-phase driving signal is set such that the time interval between the falling edge time of the v-phase driving signal and the falling edge time of the u-phase driving signal is the minimum sampling time value Tmin, and the falling edge of the v-phase driving signal is advanced with respect to the falling edge of the u-phase driving signal, fixing the falling edge of the v-phase driving signal.

Specifically, the falling edge time T2F of the v-phase driving signal is fixed such that the time interval between the falling edge time T1F of the u-phase driving signal and the falling edge time T2F of the v-phase driving signal is the minimum sampling time value Tmin, and the falling edge of the v-phase driving signal is advanced with respect to the falling edge of the u-phase driving signal, that is, t2f=t1f-Tmin.

In step S13, the rising edge of the v-phase drive signal is fixed based on the falling edge timing of the v-phase drive signal and the pulse width of the v-phase drive signal.

Specifically, in the case where the pulse width of the v-phase drive signal is unchanged, the rising edge timing T2R of the v-phase drive signal is the falling edge timing T2F of the v-phase drive signal minus the pulse width T2DUTY of the v-phase drive signal, that is, t2r=t2f—t2duty.

In step S14, the rising edge timings of the u-phase drive signal and the v-phase drive signal are compared, and one phase of drive signals in which the rising edges of the u-phase drive signal and the v-phase drive signal are relatively advanced is selected as the first reference drive signal.

Specifically, when the rising edge time T1R of the u-phase drive signal leads with respect to the rising edge time T2R of the v-phase drive signal, the u-phase drive signal is the first reference drive signal; when the rising edge time T1R of the u-phase driving signal lags behind the rising edge time T2R of the v-phase driving signal, the v-phase driving signal is the first reference driving signal.

Referring to fig. 7a and 7b, in the sectors 1, 5, and 6, the rising edge time T1R of the u-phase drive signal is advanced with respect to the rising edge time T2R of the v-phase drive signal, and the u-phase drive signal is the first reference drive signal. In the sectors 2, 3, and 4, the rising edge time T1R of the u-phase drive signal lags the rising edge time T2R of the v-phase drive signal, which is the first reference drive signal.

In step S15, the rising edge of the w-phase driving signal is set such that the time interval between the rising edge timing of the w-phase driving signal and the rising edge timing of the first reference driving signal is the minimum sampling time value Tmin, and the rising edge of the w-phase driving signal is advanced with respect to the rising edge of the first reference driving signal.

When the v-phase driving signal is the first reference driving signal, the phase of the w-phase driving signal is shifted such that the time interval between the rising edge time T3R of the w-phase driving signal and the rising edge time T2R of the v-phase driving signal is the minimum sampling time value Tmin, and the rising edge time T3R of the w-phase driving signal is advanced with respect to the rising edge time T2R of the v-phase driving signal, i.e., t3r=t2r-Tmin. Such as sector 2, sector 3, and sector 4 in fig. 7a and 7 b.

When the u-phase driving signal is the first reference driving signal, the rising edge time T3R of the w-phase driving signal is fixed, so that the time interval between the rising edge time T3R of the w-phase driving signal and the rising edge time T1R of the u-phase driving signal is the minimum sampling time value Tmin, and the rising edge time T3R of the w-phase driving signal is advanced relative to the rising edge time T1R of the u-phase driving signal, that is, t3r=t1r-Tmin. Such as sector 1, sector 5, and sector 6 in fig. 7a and 7 b.

In step S16, the timings of the falling edges of the u-phase driving signal and the v-phase driving signal are compared, and one of the u-phase driving signal and the v-phase driving signal whose falling edge is relatively advanced is selected as the second reference driving signal.

In this embodiment, in step S12, in the phase shift process of the v-phase driving signal, the falling edge time T1F of the u-phase driving signal is set to be delayed from the falling edge time T2F of the v-phase driving signal, so that the v-phase driving signal is selected as the second reference driving signal.

In step S17, the timings of the falling edges of the w-phase driving signal and the second reference driving signal are compared, when the falling edge of the w-phase driving signal is advanced with respect to the falling edge of the second reference driving signal, the rising edge and the falling edge of the w-phase driving signal are directly fixed, and when the falling edge of the w-phase driving signal is delayed with respect to the falling edge of the second reference driving signal, the w-phase driving signal is phase-shifted again so that the falling edge of the w-phase driving signal is flush with the falling edge of the second reference driving signal, and then the rising edge and the falling edge of the w-phase driving signal are fixed.

Specifically, the pulse width of the w-phase driving signal is kept unchanged, and the falling edge time of the w-phase driving signal is obtained. The rising edge time T3R of the w-phase driving signal plus the pulse width T3DUTY of the w-phase driving signal is the falling edge time T3F of the w-phase driving signal, i.e., t3f=t3r+t3duty.

Comparing the falling edge time of the v-phase driving signal with the falling edge time of the w-phase driving signal, and directly fixing the rising edge time and the falling edge time of the w-phase driving signal when the falling edge time of the v-phase driving signal lags behind the falling edge time of the w-phase driving signal. Such as sector 1, sector 2, sector 3, and sector 6 in fig. 7a and 7 b.

And when the falling edge time of the v-phase driving signal is advanced relative to the falling edge time of the w-phase driving signal, keeping the pulse width of the w-phase driving signal unchanged, and carrying out second phase shifting on the w-phase driving signal. In the second phase shifting process of the w-phase driving signal, the falling edge time of the w-phase driving signal is fixed, the falling edge time T3F of the w-phase driving signal is equal to the falling edge time T2F of the v-phase driving signal, the pulse width of the w-phase driving signal is kept unchanged, the rising edge time T3R of the w-phase driving signal is obtained, and the rising edge time T3R of the w-phase driving signal is fixed. The falling edge time T3F of the w-phase driving signal minus the pulse width T3DUTY of the w-phase driving signal is the rising edge time T3R of the w-phase driving signal, i.e., t3r=t3f-T3 DUTY. At this time, the time interval between the rising edge time T3R of the w-phase driving signal and the rising edge time T2R of the v-phase driving signal is greater than the minimum sampling time value Tmin. Such as sector 4 and sector 5 in fig. 7a and 7 b.

Referring to fig. 7a and 7b, two sampling moments of the PWM drive signal before phase shifting are consecutive, taking the waveform before phase shifting of sector 1 as an example, the sampling moments of the PWM drive signal before phase shifting are (110) and (100) between their falling edges, respectively. The two sampling instants of the PWM drive signal after the phase shift are not consecutive, taking the waveform after the phase shift of sector 1 as an example, one sampling instant of the ADC is between the falling edges of the PWM drive signal, e.g., (100), and the other sampling instant is between the rising edges of the PWM drive signal, e.g., (001). The time interval between two sampling moments of the PWM driving signal after phase shifting is increased, and the conversion time of the ADC does not need to be considered, so that the minimum sampling time value Tmin of the phase shifting method can be set smaller, and the phase shifting method can be suitable for the working condition with higher modulation ratio and has wider application range.

The present application may also be implemented in a variety of other ways, and fig. 8 shows different phase shifting manners of PWM driving signals of the sector 1 according to the first embodiment of the present application. In fig. 8, the S waveform is a waveform diagram of an original PWM driving signal, the A1 waveform is a waveform diagram after phase shifting by the first phase shifting method, the B1 waveform is a waveform diagram after phase shifting by the second phase shifting method, the C1 waveform is a waveform diagram after phase shifting by the third phase shifting method, the D1 waveform is a waveform diagram after phase shifting by the fourth phase shifting method, the E1 waveform is a waveform diagram after phase shifting by the fifth phase shifting method, and the F1 waveform is a waveform diagram after phase shifting by the sixth phase shifting method.

Referring to the S waveform and the A1 waveform in fig. 8, in the first phase shifting method, the first phase driving signal is, for example, a u phase driving signal, the second phase driving signal is, for example, a v phase driving signal, and the third phase driving signal is, for example, a w phase driving signal. The falling edge of the u-phase PWM driving signal is fixed, and the voltage vector interval sampled by the fixed ADC is (100) and (001).

Specifically, the falling edge of the u-phase PWM drive signal is fixed, and the rising edge of the u-phase drive signal is fixed based on the timing of the falling edge of the u-phase drive signal and the pulse width of the u-phase drive signal.

Then, the phase shift of the v-phase drive signal is performed. Specifically, the falling edge of the v-phase drive signal is set such that the time interval between the falling edge time of the v-phase drive signal and the falling edge time of the u-phase drive signal is the minimum sampling time value Tmin, and the falling edge of the v-phase drive signal is advanced with respect to the falling edge of the u-phase drive signal, the falling edge of the v-phase drive signal is fixed, and the rising edge of the v-phase drive signal is fixed based on the falling edge time of the v-phase drive signal and the pulse width of the v-phase drive signal.

Finally, the phase shift of the w-phase driving signal is performed. Specifically, the rising edge timings of the u-phase drive signal and the v-phase drive signal are compared, and one-phase drive signal in which the rising edges of the u-phase drive signal and the v-phase drive signal are relatively advanced is selected as the first reference drive signal. Referring to the waveform A1 in fig. 8, the rising edge timing of the u-phase drive signal is advanced with respect to the rising edge timing of the v-phase drive signal, and the u-phase drive signal is the first reference drive signal.

The rising edge of the w-phase drive signal is set such that the time interval between the rising edge timing of the w-phase drive signal and the rising edge timing of the first reference drive signal is the minimum sampling time value Tmin, and the rising edge of the w-phase drive signal is advanced with respect to the rising edge of the first reference drive signal (u-phase drive signal).

And comparing the falling edge time of the u-phase driving signal and the v-phase driving signal, and selecting one phase of driving signal with the relatively advanced falling edge in the u-phase driving signal and the v-phase driving signal as a second reference driving signal. Referring to the waveform A1 in fig. 8, the falling edge time of the u-phase drive signal is delayed from the falling edge time of the v-phase drive signal, so the v-phase drive signal is selected as the second reference drive signal.

Comparing the falling edge time of the w-phase driving signal and the second reference driving signal (v-phase driving signal), referring to the waveform A1 in fig. 8, the falling edge of the w-phase driving signal leads the falling edge of the second reference driving signal, and the rising edge and the falling edge of the w-phase driving signal are directly fixed.

Referring to the S waveform and the B1 waveform in fig. 8, in the second phase shifting method, the first phase driving signal is, for example, a u-phase driving signal, the second phase driving signal is, for example, a w-phase driving signal, the third phase driving signal is, for example, a v-phase driving signal, the falling edge of the u-phase PWM driving signal is fixed, and the voltage vector intervals sampled by the ADC are fixed to be (100) and (010).

Next, the phase shift of the w-phase drive signal is performed. Specifically, the falling edge time of the w-phase driving signal is fixed such that a time interval between the falling edge time of the u-phase driving signal and the falling edge time of the w-phase driving signal is a minimum sampling time value, and the falling edge time of the u-phase driving signal lags with respect to the falling edge time of the w-phase driving signal, the falling edge of the w-phase driving signal is fixed, and the rising edge of the w-phase driving signal is fixed based on the falling edge time of the w-phase driving signal and the pulse width of the w-phase driving signal.

Finally, the phase shift of the v-phase drive signal is performed.

Specifically, the rising edge time of the u-phase drive signal and the rising edge time of the w-phase drive signal are compared, and a one-phase PWM drive signal, in which the rising edge time of the u-phase drive signal and the rising edge time of the w-phase drive signal are relatively advanced, is selected as the first reference drive signal. Referring to the B1 waveform in fig. 8, the rising edge timing of the u-phase drive signal is advanced with respect to the rising edge timing of the w-phase drive signal, and the u-phase drive signal is the first reference drive signal.

The rising edge time of the v-phase drive signal is fixed such that the time interval between the rising edge time of the v-phase drive signal and the rising edge time of the u-phase drive signal is the minimum sampling time value Tmin, and the rising edge time of the v-phase drive signal is advanced with respect to the rising edge time of the u-phase drive signal.

And comparing the falling edge time of the u-phase driving signal and the w-phase driving signal, and selecting one phase of driving signal with relatively advanced falling edge in the u-phase driving signal and the w-phase driving signal as a second reference driving signal. Referring to the B1 waveform in fig. 8, the falling edge time of the u-phase driving signal lags behind the falling edge time of the w-phase driving signal, so the w-phase driving signal is selected as the second reference driving signal.

Comparing the falling edge time of the v-phase driving signal with the time of the second reference driving signal (the falling edge of the w-phase driving signal), referring to the waveform B1 in fig. 8, the falling edge time of the v-phase driving signal is advanced with respect to the falling edge time of the w-phase driving signal, and the rising edge time and the falling edge time of the v-phase driving signal are directly fixed.

Referring to the S waveform and the C1 waveform in fig. 8, in the third phase shifting method, the first phase driving signal is, for example, a v phase driving signal, the second phase driving signal is, for example, a u phase driving signal, the third phase driving signal is, for example, a w phase driving signal, the falling edge of the v phase PWM driving signal is fixed, and the voltage vector intervals sampled by the ADC are fixed to (010) and (001).

Specifically, the falling edge of the v-phase drive signal is fixed, and the rising edge of the v-phase drive signal is fixed based on the timing of the falling edge of the v-phase drive signal and the pulse width of the v-phase drive signal.

Then, the phase shift of the u-phase drive signal is performed. Specifically, the falling edge of the u-phase drive signal is set such that the time interval between the falling edge time of the u-phase drive signal and the falling edge time of the v-phase drive signal is a minimum sampling time value, and the falling edge of the v-phase drive signal lags behind the falling edge of the u-phase drive signal, the falling edge of the u-phase drive signal is fixed, and the rising edge of the u-phase drive signal is fixed based on the falling edge time of the u-phase drive signal and the pulse width of the u-phase drive signal.

Finally, the phase shift of the w-phase driving signal is performed.

Specifically, the rising edge time of the u-phase drive signal and the rising edge time of the v-phase drive signal are compared, and a one-phase PWM drive signal in which the rising edge time of the u-phase drive signal and the rising edge time of the v-phase drive signal are relatively advanced is selected as the first reference drive signal. Referring to the C1 waveform in fig. 8, the rising edge timing of the u-phase drive signal is advanced with respect to the rising edge timing of the v-phase drive signal, and the u-phase drive signal is the first reference drive signal.

Next, the rising edge of the w-phase drive signal is set such that the time interval between the rising edge timing of the w-phase drive signal and the rising edge timing of the first reference drive signal (u-phase drive signal) is the minimum sampling time value, and the rising edge of the w-phase drive signal is advanced with respect to the rising edge of the first reference drive signal (u-phase drive signal).

Next, the falling edge time of the u-phase driving signal and the w-phase driving signal is compared, and one phase driving signal with the relatively advanced falling edge in the u-phase driving signal and the v-phase driving signal is selected as a second reference driving signal. Referring to the C1 waveform in fig. 8, the falling edge timing of the u-phase drive signal is advanced with respect to the falling edge timing of the v-phase drive signal, so the u-phase drive signal is selected as the second reference drive signal.

Next, the falling edge timings of the w-phase drive signal and the second reference drive signal (u-phase drive signal) are compared, and referring to the waveform C1 in fig. 8, the falling edge of the w-phase drive signal is advanced with respect to the falling edge of the second reference drive signal (u-phase drive signal), and the rising edge and the falling edge of the w-phase drive signal are directly fixed.

Referring to the S waveform and the D1 waveform in fig. 8, in the fourth phase shifting method, the first phase driving signal is, for example, a v phase driving signal, the second phase driving signal is, for example, a w phase driving signal, the third phase driving signal is, for example, a u phase driving signal, the falling edge of the v phase PWM driving signal is fixed, and the voltage vector intervals sampled by the ADC are fixed to (010) and (100).

Next, the phase shift of the w-phase drive signal is performed. Specifically, the falling edge of the w-phase drive signal is set such that the time interval between the falling edge time of the w-phase drive signal and the falling edge time of the w-phase drive signal is a minimum sampling time value, and the falling edge of the v-phase drive signal lags behind the falling edge of the w-phase drive signal, the falling edge of the w-phase drive signal is fixed, and the rising edge of the w-phase drive signal is fixed based on the falling edge time of the w-phase drive signal and the pulse width of the w-phase drive signal.

Finally, the phase shift of the u-phase driving signal is performed.

Specifically, the rising edge timing of the w-phase drive signal and the rising edge timing of the v-phase drive signal are compared, and a one-phase PWM drive signal whose rising edge timings are relatively advanced is selected as the first reference drive signal. Referring to the D1 waveform in fig. 8, the rising edge timing of the w-phase drive signal is advanced with respect to the rising edge timing of the v-phase drive signal, and the w-phase drive signal is the first reference drive signal.

Next, the rising edge of the u-phase drive signal is set such that the time interval between the rising edge timing of the u-phase drive signal and the rising edge timing of the first reference drive signal (w-phase drive signal) is the minimum sampling time value, and the rising edge of the u-phase drive signal is advanced with respect to the rising edge of the first reference drive signal (w-phase drive signal).

Next, the falling edge time of the v-phase driving signal and the falling edge time of the w-phase driving signal are compared, and one phase driving signal with the falling edge relatively advanced in the v-phase driving signal and the w-phase driving signal is selected as a second reference driving signal. Referring to the D1 waveform in fig. 8, the falling edge timing of the w-phase drive signal is advanced with respect to the falling edge timing of the v-phase drive signal, so the w-phase drive signal is selected as the second reference drive signal.

Next, the timings of the falling edges of the u-phase drive signal and the second reference drive signal (w-phase drive signal) are compared, and referring to the waveform D1 in fig. 8, the falling edge of the u-phase drive signal is advanced with respect to the falling edge of the second reference drive signal (w-phase drive signal), and the rising edge and the falling edge of the w-phase drive signal are directly fixed.

Referring to the S waveform and the E1 waveform in fig. 8, in the fifth phase shifting method, the first phase driving signal is, for example, a w phase driving signal, the second phase driving signal is, for example, a u phase driving signal, the third phase driving signal is, for example, a v phase driving signal, the falling edge of the w phase PWM driving signal is fixed, and the voltage vector intervals sampled by the ADC are fixed to be (001) and (010).

Specifically, the falling edge of the w-phase drive signal is fixed, and the rising edge of the w-phase drive signal is fixed based on the timing of the falling edge of the w-phase drive signal and the pulse width of the w-phase drive signal.

Then, the phase shift of the u-phase drive signal is performed. Specifically, the falling edge of the u-phase drive signal is set such that the time interval between the falling edge time of the u-phase drive signal and the falling edge time of the w-phase drive signal is a minimum sampling time value, and the falling edge of the w-phase drive signal lags behind the falling edge of the u-phase drive signal, the falling edge of the u-phase drive signal is fixed, and the rising edge of the u-phase drive signal is fixed based on the falling edge time of the u-phase drive signal and the pulse width of the u-phase drive signal.

Finally, the phase shift of the v-phase drive signal is performed.

Specifically, the rising edge timing of the w-phase drive signal and the rising edge timing of the u-phase drive signal are compared, and one-phase PWM drive signal, in which the rising edge timings of the w-phase drive signal and the u-phase drive signal are relatively advanced, is selected as the first reference drive signal. Referring to the E1 waveform in fig. 8, the rising edge timing of the u-phase drive signal is advanced with respect to the rising edge timing of the w-phase drive signal, and the u-phase drive signal is the first reference drive signal.

Next, the rising edge of the v-phase drive signal is set such that the time interval between the rising edge timing of the v-phase drive signal and the rising edge timing of the first reference drive signal (u-phase drive signal) is the minimum sampling time value, and the rising edge of the v-phase drive signal is advanced with respect to the rising edge of the first reference drive signal (u-phase drive signal).

Next, the falling edge time of the w-phase driving signal and the u-phase driving signal is compared, and one phase driving signal with the relatively advanced falling edge in the w-phase driving signal and the u-phase driving signal is selected as a second reference driving signal. Referring to the E1 waveform in fig. 8, the falling edge timing of the u-phase driving signal is advanced with respect to the falling edge timing of the w-phase driving signal, so the u-phase driving signal is selected as the second reference driving signal.

Next, the falling edge timings of the v-phase drive signal and the second reference drive signal (u-phase drive signal) are compared, and referring to the E1 waveform in fig. 8, the falling edge of the v-phase drive signal is advanced with respect to the falling edge of the second reference drive signal (u-phase drive signal), and the rising edge and the falling edge of the v-phase drive signal are directly fixed.

Referring to the S waveform and the F1 waveform in fig. 8, in the sixth phase shifting method, the first phase driving signal is, for example, a w phase driving signal, the second phase driving signal is, for example, a v phase driving signal, the third phase driving signal is, for example, a u phase driving signal, the falling edge of the w phase PWM driving signal is fixed, and the voltage vector intervals sampled by the ADC are fixed to (001) and (100).

Then, the phase shift of the v-phase drive signal is performed. Specifically, the falling edge of the v-phase drive signal is set such that the time interval between the falling edge time of the v-phase drive signal and the falling edge time of the w-phase drive signal is a minimum sampling time value, and the falling edge of the w-phase drive signal lags behind the falling edge of the v-phase drive signal, the falling edge of the v-phase drive signal is fixed, and the rising edge of the v-phase drive signal is fixed based on the falling edge time of the v-phase drive signal and the pulse width of the v-phase drive signal.

Finally, the phase shift of the u-phase driving signal is performed.

Specifically, the rising edge timing of the w-phase drive signal and the rising edge timing of the v-phase drive signal are compared, and a one-phase PWM drive signal whose rising edge timings are relatively advanced is selected as the first reference drive signal. Referring to the F1 waveform in fig. 8, the rising edge timing of the v-phase drive signal is advanced with respect to the rising edge timing of the w-phase drive signal, and the v-phase drive signal is the first reference drive signal.

Next, the rising edge of the u-phase drive signal is set such that the time interval between the rising edge timing of the u-phase drive signal and the rising edge timing of the first reference drive signal (v-phase drive signal) is the minimum sampling time value, and the rising edge of the u-phase drive signal is advanced with respect to the rising edge of the first reference drive signal (v-phase drive signal).

Next, the falling edge time of the w-phase driving signal and the v-phase driving signal is compared, and one phase driving signal with the relatively advanced falling edge in the w-phase driving signal and the v-phase driving signal is selected as a second reference driving signal. Referring to the F1 waveform in fig. 8, the falling edge timing of the v-phase drive signal is advanced with respect to the falling edge timing of the w-phase drive signal, so the v-phase drive signal is selected as the second reference drive signal.

Next, the falling edge timings of the u-phase drive signal and the second reference drive signal (v-phase drive signal) are compared, and referring to the F1 waveform in fig. 8, the falling edge of the u-phase drive signal is advanced with respect to the falling edge of the second reference drive signal (v-phase drive signal), and the rising edge and the falling edge of the u-phase drive signal are directly fixed.

Fig. 9 shows a flowchart of a PWM driving signal phase shifting method according to a second embodiment of the present application; as shown in fig. 9, the phase shifting method of the PWM driving signal according to the second embodiment of the present application includes the following steps.

Step S21: fixing a rising edge of the first phase driving signal, and fixing a falling edge of the first phase driving signal based on a time of the rising edge of the first phase driving signal and a pulse width of the first phase driving signal;

step S22: setting a rising edge of the second phase drive signal such that a time interval between a rising edge time of the second phase drive signal and a rising edge time of the first phase drive signal is a minimum sampling time value, and the rising edge of the second phase drive signal lags behind the rising edge of the first phase drive signal, and fixing the rising edge of the second phase drive signal;

step S23: fixing a falling edge of the second phase driving signal based on a rising edge time of the second phase driving signal and a pulse width of the second phase driving signal;

step S24: comparing the falling edge time of the first phase driving signal and the falling edge time of the second phase driving signal, and selecting a phase PWM driving signal with relatively lagging falling edge time in the first phase driving signal and the second phase driving signal as a first reference driving signal;

step S25: setting a falling edge of the third phase driving signal based on the first reference driving signal such that a time interval between a falling edge time of the third phase driving signal and a falling edge time of the first reference driving signal is a minimum sampling time value, and the falling edge of the third phase driving signal lags behind the falling edge of the first reference driving signal;

Step S26: comparing rising edge moments of the first phase driving signal and the second phase driving signal, and selecting a phase driving signal with relatively lagging rising edge moments of the first phase driving signal and the second phase driving signal as a second reference driving signal;

step S27: comparing rising edge moments of the third phase driving signal and the second reference driving signal; when the rising edge of the third phase driving signal is lagged relative to the rising edge of the second reference driving signal, directly fixing the rising edge and the falling edge of the third phase driving signal;

when the rising edge of the third phase driving signal is advanced relative to the rising edge of the second reference driving signal, the third phase driving signal is phase-shifted again so that the rising edge time of the third phase driving signal is flush with the rising edge of the second reference driving signal, and then the rising edge and the falling edge of the third phase driving signal are fixed.

Fig. 10 shows different phase shifting patterns of PWM driving signals of the sector 1 according to the second embodiment of the present application. In fig. 10, the S waveform is a waveform diagram of the original PWM driving signal, the A2 waveform is a waveform diagram after phase shifting by the seventh phase shifting method, the B2 waveform is a waveform diagram after phase shifting by the eighth phase shifting method, the C2 waveform is a waveform diagram after phase shifting by the ninth phase shifting method, the D2 waveform is a waveform diagram after phase shifting by the tenth phase shifting method, the E2 waveform is a waveform diagram after phase shifting by the eleventh phase shifting method, and the F2 waveform is a waveform diagram after phase shifting by the twelfth phase shifting method.

Referring to the S waveform and the A2 waveform in fig. 10, in the seventh phase shifting method, the first phase driving signal is, for example, a u-phase driving signal, the second phase driving signal is, for example, a v-phase driving signal, the third phase driving signal is, for example, a w-phase driving signal, the rising edge of the u-phase PWM driving signal is fixed, and the voltage vector sections sampled by the ADC are fixed at (100) and (001).

Specifically, the rising edge of the u-phase drive signal is fixed, and the falling edge of the u-phase drive signal is fixed based on the timing of the rising edge of the u-phase drive signal and the pulse width of the u-phase drive signal.

Then, the phase shift of the v-phase drive signal is performed. Specifically, the rising edge of the v-phase driving signal is set such that the time interval between the rising edge time of the u-phase driving signal and the rising edge time of the v-phase driving signal is a minimum sampling time value, and the rising edge of the u-phase driving signal is advanced relative to the rising edge of the v-phase driving signal, and the rising edge of the v-phase driving signal is fixed; and fixing the falling edge of the v-phase driving signal based on the rising edge time of the v-phase driving signal and the pulse width of the v-phase driving signal.

Finally, the phase shift of the w-phase driving signal is performed.

Specifically, the falling edge time of the u-phase driving signal and the falling edge time of the v-phase driving signal are compared, and one phase of PWM driving signal with relatively lagging falling edge time in the u-phase driving signal and the v-phase driving signal is selected as the first reference driving signal. Referring to the waveform A2 in fig. 10, the falling edge timing of the u-phase drive signal lags behind the falling edge timing of the v-phase drive signal, and the u-phase drive signal is the first reference drive signal.

Next, the falling edge of the w-phase drive signal is set such that the time interval between the falling edge timing of the w-phase drive signal and the falling edge timing of the first reference drive signal (u-phase drive signal) is the minimum sampling time value, and the falling edge of the w-phase drive signal lags behind the falling edge of the first reference drive signal (u-phase drive signal).

Next, rising edge timings of the u-phase driving signal and the v-phase driving signal are compared, and a one-phase PWM driving signal having a delayed rising edge between the u-phase driving signal and the v-phase driving signal is selected as the second reference driving signal. Referring to the waveform A2 in fig. 10, the rising edge timing of the u-phase drive signal is advanced with respect to the rising edge timing of the v-phase drive signal, so the v-phase drive signal is selected as the second reference drive signal.

Next, the rising edge time of the w-phase drive signal and the rising edge time of the second reference drive signal (v-phase drive signal) are compared, and referring to the waveform A2 in fig. 10, the rising edge time of the w-phase drive signal is delayed from the rising edge time of the second reference drive signal (v-phase drive signal), and the rising edge and the falling edge of the w-phase drive signal are directly fixed.

Referring to the S waveform and the B2 waveform in fig. 10, in the eighth phase shift method, the first phase driving signal is, for example, a u-phase driving signal, the second phase driving signal is, for example, a w-phase driving signal, the third phase driving signal is, for example, a v-phase driving signal, the rising edge of the u-phase PWM driving signal is fixed, and the voltage vector sections sampled by the ADC are fixed to (100) and (010).

Next, the phase shift of the w-phase drive signal is performed. Specifically, the rising edge of the w-phase driving signal is set so that the time interval between the rising edge time of the u-phase driving signal and the rising edge time of the w-phase driving signal is the minimum sampling time value, and the rising edge of the u-phase driving signal is advanced relative to the rising edge of the w-phase driving signal, and the rising edge of the w-phase driving signal is fixed; and fixing the falling edge of the w-phase driving signal based on the rising edge time of the w-phase driving signal and the pulse width of the w-phase driving signal.

Finally, the phase shift of the v-phase drive signal is performed.

Specifically, the falling edge time of the u-phase driving signal and the falling edge time of the w-phase driving signal are compared, and one phase PWM driving signal with relatively lagging falling edge time in the u-phase driving signal and the w-phase driving signal is selected as a first reference driving signal. Referring to the B2 waveform in fig. 10, the falling edge timing of the u-phase drive signal lags behind the falling edge timing of the w-phase drive signal, and the u-phase drive signal is the first reference drive signal.

Next, the falling edge of the v-phase drive signal is set such that the time interval between the falling edge timing of the v-phase drive signal and the falling edge timing of the first reference drive signal (u-phase drive signal) is the minimum sampling time value, and the falling edge of the v-phase drive signal lags behind the falling edge of the first reference drive signal (u-phase drive signal).

Next, rising edge timings of the u-phase driving signal and the w-phase driving signal are compared, and a one-phase PWM driving signal having a delayed rising edge between the u-phase driving signal and the w-phase driving signal is selected as the second reference driving signal. Referring to the B2 waveform in fig. 10, the rising edge timing of the u-phase drive signal is advanced with respect to the rising edge timing of the v-phase drive signal, so the w-phase drive signal is selected as the second reference drive signal.

Next, the rising edge time of the v-phase drive signal and the rising edge time of the second reference drive signal (w-phase drive signal) are compared, and referring to the waveform A2 in fig. 10, the rising edge time of the v-phase drive signal is delayed from the rising edge time of the second reference drive signal (w-phase drive signal), and the rising edge and the falling edge of the v-phase drive signal are directly fixed.

Referring to the S waveform and the C2 waveform in fig. 10, in the ninth phase shifting method, the first phase driving signal is, for example, a v phase driving signal, the second phase driving signal is, for example, a u phase driving signal, the third phase driving signal is, for example, a w phase driving signal, the rising edge of the v phase PWM driving signal is fixed, and the voltage vector sections sampled by the ADC are fixed at (010) and (001).

Specifically, the rising edge of the v-phase drive signal is fixed, and the falling edge of the v-phase drive signal is fixed based on the timing of the rising edge of the v-phase drive signal and the pulse width of the v-phase drive signal.

Then, the phase shift of the u-phase drive signal is performed. Specifically, the rising edge of the u-phase driving signal is set such that the time interval between the rising edge time of the v-phase driving signal and the rising edge time of the u-phase driving signal is a minimum sampling time value, and the rising edge of the v-phase driving signal is advanced relative to the rising edge of the u-phase driving signal, and the rising edge of the u-phase driving signal is fixed; and fixing the falling edge of the u-phase driving signal based on the rising edge time of the u-phase driving signal and the pulse width of the u-phase driving signal.

Finally, the phase shift of the w-phase driving signal is performed.

Specifically, the falling edge time of the v-phase driving signal and the falling edge time of the u-phase driving signal are compared, and one phase PWM driving signal with relatively lagging falling edge time in the v-phase driving signal and the u-phase driving signal is selected as a first reference driving signal. Referring to the C2 waveform in fig. 10, the falling edge timing of the u-phase drive signal lags behind the falling edge timing of the v-phase drive signal, and the u-phase drive signal is the first reference drive signal.

Next, the rising edge timings of the v-phase drive signal and the u-phase drive signal are compared, and a one-phase PWM drive signal having a delayed rising edge between the v-phase drive signal and the u-phase drive signal is selected as the second reference drive signal. Referring to the C2 waveform in fig. 10, the rising edge timing of the v-phase drive signal is advanced with respect to the rising edge timing of the u-phase drive signal, so the u-phase drive signal is selected as the second reference drive signal.

Next, the rising edge time of the w-phase drive signal and the rising edge time of the second reference drive signal (u-phase drive signal) are compared, and referring to the waveform C2 in fig. 10, the rising edge time of the w-phase drive signal is delayed from the rising edge time of the second reference drive signal (u-phase drive signal), and the rising edge and the falling edge of the w-phase drive signal are directly fixed.

Referring to the S waveform and the D2 waveform in fig. 10, in the tenth phase shift method, the first phase driving signal is, for example, a v-phase driving signal, the second phase driving signal is, for example, a w-phase driving signal, the third phase driving signal is, for example, a u-phase driving signal, the rising edge of the v-phase PWM driving signal is fixed, and the voltage vector sections sampled by the fixed ADC are (010) and (100).

Next, the phase shift of the w-phase drive signal is performed. Specifically, the rising edge of the w-phase driving signal is set such that the time interval between the rising edge time of the v-phase driving signal and the rising edge time of the w-phase driving signal is a minimum sampling time value, and the rising edge of the v-phase driving signal is advanced relative to the rising edge of the w-phase driving signal, and the rising edge of the w-phase driving signal is fixed; and fixing the falling edge of the w-phase driving signal based on the rising edge time of the w-phase driving signal and the pulse width of the w-phase driving signal.

Finally, the phase shift of the u-phase driving signal is performed.

Specifically, the falling edge time of the v-phase driving signal and the falling edge time of the w-phase driving signal are compared, and one phase of PWM driving signal which is relatively lagging in the falling edge time of the v-phase driving signal and the w-phase driving signal is selected as the first reference driving signal. Referring to the D2 waveform in fig. 10, the falling edge timing of the v-phase drive signal lags behind the falling edge timing of the w-phase drive signal, and the v-phase drive signal is the first reference drive signal.

Next, the falling edge of the u-phase drive signal is set such that the time interval between the falling edge timing of the u-phase drive signal and the falling edge timing of the first reference drive signal (v-phase drive signal) is the minimum sampling time value, and the falling edge of the u-phase drive signal lags behind the falling edge of the first reference drive signal (v-phase drive signal).

Next, the rising edge timings of the v-phase driving signal and the w-phase driving signal are compared, and a one-phase PWM driving signal having a delayed rising edge between the v-phase driving signal and the w-phase driving signal is selected as the second reference driving signal. Referring to the D2 waveform in fig. 10, the rising edge timing of the v-phase drive signal is advanced with respect to the rising edge timing of the u-phase drive signal, so the w-phase drive signal is selected as the second reference drive signal.

Next, the rising edge timings of the u-phase driving signal and the second reference driving signal (w-phase driving signal) are compared, referring to the D2 waveform in fig. 10, the rising edge timings of the u-phase driving signal are advanced with respect to the rising edge timings of the second reference driving signal (w-phase driving signal), the u-phase driving signal is phase-shifted again so that the rising edge timings of the u-phase driving signal are flush with the rising edge of the second reference driving signal, and then the rising edge and the falling edge of the u-phase driving signal are fixed.

Referring to the S waveform and the E2 waveform in fig. 10, in the eleventh phase shifting method, the first phase driving signal is, for example, a w phase driving signal, the second phase driving signal is, for example, a u phase driving signal, the third phase driving signal is, for example, a v phase driving signal, the rising edge of the w phase PWM driving signal is fixed, and the voltage vector sections sampled by the ADC are (001) and (010) fixed.

Specifically, the rising edge of the w-phase drive signal is fixed, and the falling edge of the w-phase drive signal is fixed based on the timing of the rising edge of the w-phase drive signal and the pulse width of the w-phase drive signal.

Then, the phase shift of the u-phase drive signal is performed. Specifically, the rising edge of the u-phase driving signal is set so that the time interval between the rising edge time of the w-phase driving signal and the rising edge time of the u-phase driving signal is the minimum sampling time value, and the rising edge of the w-phase driving signal is advanced relative to the rising edge of the u-phase driving signal, and the rising edge of the u-phase driving signal is fixed; and fixing the falling edge of the u-phase driving signal based on the rising edge time of the u-phase driving signal and the pulse width of the u-phase driving signal.

Finally, the phase shift of the v-phase drive signal is performed.

Specifically, the falling edge time of the w-phase driving signal and the falling edge time of the u-phase driving signal are compared, and one phase PWM driving signal with relatively lagging falling edge time in the w-phase driving signal and the u-phase driving signal is selected as a first reference driving signal. Referring to the E2 waveform in fig. 10, the falling edge timing of the u-phase drive signal lags behind the falling edge timing of the w-phase drive signal, and the u-phase drive signal is the first reference drive signal.

Next, rising edge timings of the w-phase driving signal and the u-phase driving signal are compared, and a phase PWM driving signal having a lag in rising edge of the w-phase driving signal and the u-phase driving signal is selected as the second reference driving signal. Referring to the E2 waveform in fig. 10, the rising edge timing of the w-phase driving signal is advanced with respect to the rising edge timing of the u-phase driving signal, so the u-phase driving signal is selected as the second reference driving signal.

Next, the rising edge time of the v-phase drive signal and the rising edge time of the second reference drive signal (u-phase drive signal) are compared, and referring to the E2 waveform in fig. 10, the rising edge time of the v-phase drive signal is delayed from the rising edge time of the second reference drive signal (u-phase drive signal), and the rising edge and the falling edge of the v-phase drive signal are directly fixed.

Referring to the S waveform and the F2 waveform in fig. 10, in the twelfth phase shift method, the first phase driving signal is, for example, a w phase driving signal, the second phase driving signal is, for example, a v phase driving signal, the third phase driving signal is, for example, a u phase driving signal, the rising edge of the w phase PWM driving signal is fixed, and the voltage vector sections sampled by the ADC are (001) and (100) fixed.

Then, the phase shift of the v-phase drive signal is performed. Specifically, the rising edge of the v-phase driving signal is set such that the time interval between the rising edge time of the w-phase driving signal and the rising edge time of the v-phase driving signal is a minimum sampling time value, and the rising edge of the w-phase driving signal is advanced relative to the rising edge of the v-phase driving signal, and the rising edge of the v-phase driving signal is fixed; and fixing the falling edge of the v-phase driving signal based on the rising edge time of the v-phase driving signal and the pulse width of the v-phase driving signal.

Finally, the phase shift of the u-phase driving signal is performed.

Specifically, the falling edge time of the w-phase driving signal and the falling edge time of the v-phase driving signal are compared, and one phase of PWM driving signal which is relatively lagging in the falling edge time of the w-phase driving signal and the v-phase driving signal is selected as the first reference driving signal. Referring to the F2 waveform in fig. 10, the falling edge timing of the v-phase drive signal lags behind the falling edge timing of the w-phase drive signal, and the v-phase drive signal is the first reference drive signal.

Next, rising edge timings of the w-phase driving signal and the v-phase driving signal are compared, and a one-phase PWM driving signal having a delayed rising edge between the w-phase driving signal and the v-phase driving signal is selected as the second reference driving signal. Referring to the F2 waveform in fig. 10, the rising edge timing of the w-phase drive signal is advanced with respect to the rising edge timing of the v-phase drive signal, so the v-phase drive signal is selected as the second reference drive signal.

Next, the rising edge time of the u-phase drive signal and the rising edge time of the second reference drive signal (v-phase drive signal) are compared, and referring to the F2 waveform in fig. 10, the rising edge time of the u-phase drive signal is delayed from the rising edge time of the second reference drive signal (v-phase drive signal), and the rising edge and the falling edge of the u-phase drive signal are directly fixed.

The PWM driving signals of one period of the sector 1 are phase-shifted based on the above different manners, and the resulting waveforms are also different, but in any manner, the PWM driving signals after phase shifting satisfy that in each period, the time interval between the rising edges of the two-phase driving signals, in which the rising edge timings of the second-phase driving signal and the third-phase driving signal are relatively advanced, is greater than or equal to the minimum sampling time value, and the time interval between the falling edges of the two-phase driving signals, in which the falling edge timings of the first-phase driving signal and the third-phase driving signal are relatively retarded, is greater than or equal to the minimum sampling time value.

Embodiments in accordance with the present invention, as described above, are not intended to be exhaustive or to limit the invention to the precise embodiments disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and the full scope and equivalents thereof.

Claims

1. An inverter control method, wherein the control method comprises:

generating a multiphase PWM drive signal;

setting a minimum sampling time value;

shifting the phase of the PWM drive signal based on the minimum sampling time value; and

driving an inverter with the phase-shifted PWM driving signal;

in the phase shifting process, the pulse width of the multiphase PWM driving signal is unchanged; after the phase shifting, a time interval between rising edges of relatively leading two-phase drive signals in the multiphase PWM drive signals is greater than or equal to a minimum sampling time value, and a time interval between falling edges of relatively lagging two-phase drive signals in the multiphase PWM drive signals is greater than or equal to the minimum sampling time value.

2. The inverter control method of claim 1, wherein the PWM drive signal comprises a first phase drive signal, a second phase drive signal, and a third phase drive signal, the phase shifting method comprising:

and moving the rising edges and the falling edges of the second phase driving signal and the third phase driving signal phase by phase based on the fixed edges of the first phase driving signal.

3. The inverter control method according to claim 2, wherein a falling edge of the first phase drive signal is fixed, and a rising edge of the first phase drive signal is fixed based on a timing of the falling edge of the first phase drive signal and a pulse width of the first phase drive signal.

4. The inverter control method of claim 3, wherein the phase shifting method of the second phase drive signal comprises:

setting a falling edge of the second phase drive signal such that a time interval between a falling edge time of the second phase drive signal and a falling edge time of the first phase drive signal is a minimum sampling time value, and the falling edge of the second phase drive signal is advanced relative to the falling edge of the first phase drive signal, and fixing the falling edge of the second phase drive signal;

the rising edge of the second phase drive signal is fixed based on the falling edge time of the second phase drive signal and the pulse width of the second phase drive signal.

5. The inverter control method of claim 4, wherein the phase shifting method of the third phase driving signal comprises:

comparing rising edge moments of the first phase driving signal and the second phase driving signal, and selecting a phase driving signal with a relatively advanced rising edge of the first phase driving signal and the second phase driving signal as a first reference driving signal;

Setting the rising edge of the third phase driving signal so that the time interval between the rising edge moment of the third phase driving signal and the rising edge moment of the first reference driving signal is a minimum sampling time value, and the rising edge of the third phase driving signal is advanced relative to the rising edge of the first reference driving signal;

comparing the falling edge time of the first phase driving signal and the second phase driving signal, and selecting one phase driving signal with relatively advanced falling edge in the first phase driving signal and the second phase driving signal as a second reference driving signal;

comparing the falling edge time of the third phase driving signal with the falling edge time of the second reference driving signal, and directly fixing the rising edge and the falling edge of the third phase driving signal when the falling edge of the third phase driving signal is advanced relative to the falling edge of the second reference driving signal;

and when the falling edge of the third phase driving signal lags behind the falling edge of the second reference driving signal, shifting the phase of the third phase driving signal again so that the falling edge of the third phase driving signal is flush with the falling edge of the second reference driving signal, and then fixing the rising edge and the falling edge of the third phase driving signal.

6. The method of claim 2, wherein a rising edge of the first phase drive signal is fixed and a falling edge of the first phase drive signal is fixed based on a time of the rising edge of the first phase drive signal and a pulse width of the first phase drive signal.

7. The method of claim 6, wherein the second phase drive signal phase shifting method comprises:

setting a rising edge of the second phase drive signal such that a time interval between a rising edge time of the second phase drive signal and a rising edge time of the first phase drive signal is a minimum sampling time value, and the rising edge of the second phase drive signal lags with respect to the rising edge of the first phase drive signal, and fixing the rising edge of the second phase drive signal;

the falling edge of the second phase driving signal is fixed based on the rising edge time of the second phase driving signal and the pulse width of the second phase driving signal.

8. The method of claim 7, wherein the phase shifting method of the third phase drive signal comprises:

comparing the falling edge moments of the first phase driving signal and the second phase driving signal, and selecting a phase PWM driving signal with relatively lagging falling edge moments in the first phase driving signal and the second phase driving signal as a first reference driving signal;

Setting a falling edge of the third phase drive signal based on the first reference drive signal such that a time interval between a falling edge time of the third phase drive signal and a falling edge time of the first reference drive signal is a minimum sampling time value, and the falling edge of the third phase drive signal lags with respect to the falling edge of the first reference drive signal;

comparing rising edge moments of the first phase driving signal and the second phase driving signal, and selecting a phase driving signal with relatively lagging rising edge moments of the first phase driving signal and the second phase driving signal as a second reference driving signal;

comparing rising edge moments of the third phase driving signal and the second reference driving signal, and directly fixing rising edges and falling edges of the third phase driving signal when rising edges of the third phase driving signal lag relative to rising edges of the second reference driving signal;

and when the rising edge of the third phase driving signal is advanced relative to the rising edge of the second reference driving signal, shifting the phase of the third phase driving signal again so that the rising edge moment of the third phase driving signal is flush with the rising edge of the second reference driving signal, and then fixing the rising edge and the falling edge of the third phase driving signal.

9. The method of claim 1, further comprising sampling and reconstructing a dc bus current of the inverter.

10. An inverter control system comprising:

the control module is used for generating a multiphase PWM driving signal, setting a minimum sampling time value, shifting the phase of the PWM driving signal based on the minimum sampling time value, and driving the inverter by the PWM driving signal after the phase shifting;

in the phase shifting process of the phase shifting module, the pulse width of the multiphase PWM driving signal is unchanged; after the phase shifting, a time interval between rising edges of relatively leading two-phase drive signals in the multiphase PWM drive signals is greater than or equal to a minimum sampling time value, and a time interval between falling edges of relatively lagging two-phase drive signals in the multiphase PWM drive signals is greater than or equal to the minimum sampling time value.

11. The inverter control system of claim 10 wherein the PWM drive signals include a first phase drive signal, a second phase drive signal, and a third phase drive signal, the control module performing the steps of phase shifting the PWM drive signals:

12. The inverter control system of claim 11, wherein a falling edge of the first phase drive signal is fixed and a rising edge of the first phase drive signal is fixed based on a time of the falling edge of the first phase drive signal and a pulse width of the first phase drive signal.

13. The inverter control system of claim 12 wherein the control module performs the following steps to phase shift the second phase drive signal:

14. The inverter control system of claim 13, wherein the control module performs the following steps to phase shift the third phase drive signal:

15. The inverter control system of claim 11, wherein a rising edge of the first phase drive signal is fixed and a falling edge of the first phase drive signal is fixed based on a time of the rising edge of the first phase drive signal and a pulse width of the first phase drive signal.

16. The inverter control system of claim 15, wherein the control module performs the following steps to phase shift the second phase drive signal:

17. The inverter control system of claim 16, wherein the control module performs the following steps to phase shift the third phase drive signal:

18. The inverter control system of claim 10 wherein the control module further samples and reconstructs a dc bus current of the inverter.