CN112436750B - Control method and control circuit of inverter - Google Patents

Control method and control circuit of inverter Download PDF

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CN112436750B
CN112436750B CN202011073315.0A CN202011073315A CN112436750B CN 112436750 B CN112436750 B CN 112436750B CN 202011073315 A CN202011073315 A CN 202011073315A CN 112436750 B CN112436750 B CN 112436750B
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phase
sampling
current
inverter
pwm control
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CN112436750A (en
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曾志成
徐晖
吴春
柳洲
林森
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Hangzhou Silan Microelectronics Co Ltd
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Hangzhou Silan Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P21/00—Arrangements or methods for the control of electric machines by vector control, e.g. by control of field orientation
    • H02P21/0003—Control strategies in general, e.g. linear type, e.g. P, PI, PID, using robust control
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02P—CONTROL OR REGULATION OF ELECTRIC MOTORS, ELECTRIC GENERATORS OR DYNAMO-ELECTRIC CONVERTERS; CONTROLLING TRANSFORMERS, REACTORS OR CHOKE COILS
    • H02P21/00—Arrangements or methods for the control of electric machines by vector control, e.g. by control of field orientation
    • H02P21/14—Estimation or adaptation of machine parameters, e.g. flux, current or voltage

Abstract

The embodiment of the invention discloses a control method and a control circuit of an inverter. The control method comprises the following steps: setting a desired minimum sample time value; obtaining a duration value of an actual samplable window in each PWM control period; under the condition that the duration values of actual sampling windows in a plurality of continuous PWM control periods are all larger than or equal to the expected minimum sampling time value, sampling phase currents of any two phases in the inverter and reconstructing to obtain three-phase currents; and under the condition that the duration values of the actual sampling windows in a plurality of continuous PWM control periods are not satisfied to be larger than or equal to the expected minimum sampling time value, sampling the direct current bus current and reconstructing to obtain the three-phase current. The control method of the embodiment does not need to calculate the square root, not only can reduce the calculation capacity and cost of the microcontroller, but also can be suitable for current reconstruction sampling of different voltage modulation algorithms, and has wide application range.

Description

Control method and control circuit of inverter
Technical Field
The invention relates to the technical field of motor control, in particular to a control method and a control circuit of an inverter.
Background
With the rapid development of power electronic technology, a three-phase inverter system having a three-phase inverter as a main structure is widely used. The three-phase inverter system is a power electronic system that converts direct current into alternating current by using control methods such as SPWM (Sinusoidal Pulse Width Modulation), SVPWM (Space Vector Pulse Width Modulation), DPWM (Discontinuous Pulse Width Modulation), and the like, and is widely applied to communication, factory, and enterprise uninterruptible power supply systems.
The current detection of the three-phase inverter is an important feedback link in a control system, and is related to the vector control performance and the current-limiting protection capability of the three-phase inverter. The three-phase inverter can adjust the optimal control state of the three-phase inverter in real time only by accurately obtaining three-phase current in the full modulation ratio range.
The existing control methods of the three-phase inverter include the following steps: the first method is to install an isolated current sensor (e.g., a hall sensor) on the phase line of the three-phase inverter, and directly sample the current of the phase line, which has the disadvantage that the cost of the sensor is too high to be acceptable for some cost-effective systems. Secondly, sampling resistors are respectively installed on the lower bridge arms of the three-phase inverter to perform phase current sampling, and the method has the defects of more sampling channels and larger occupied resources. The third method is that peak current sampling is carried out on a sampling resistor connected in series with a direct current bus to reconstruct three-phase current, and the three-phase current finally passes through the direct current bus, so the current of the direct current bus can accurately reflect the change of the three-phase current.
Disclosure of Invention
In view of this, an object of the present invention is to provide a control method and a control circuit for an inverter, which have low requirements on the computing capability of a microcontroller, can reduce the computing cost of the microcontroller, and can be applied to current sampling reconstruction of different voltage modulation algorithms, and have a wide application range.
According to an aspect of an embodiment of the present invention, there is provided a control method of an inverter, including:
setting a desired minimum sample time value;
obtaining a duration value of an actual samplable window in each PWM control period;
under the condition that the duration values of the actual sampling windows in a plurality of continuous PWM control periods are all larger than or equal to the expected minimum sampling time value, sampling the phase currents of any two phases of the inverter and reconstructing to obtain three-phase currents;
and in the case that the duration values of the actual sampling windows in a plurality of continuous PWM control periods are not satisfied to be larger than or equal to the expected minimum sampling time value, sampling the direct current bus current and reconstructing to obtain three-phase current.
Optionally, the control method further includes:
in each PWM control period, judging whether the duration value is smaller than the expected minimum sampling time value;
if the duration value is smaller than the expected minimum sampling time value, sampling the direct current bus current and reconstructing to obtain a three-phase current;
if the duration value is greater than or equal to the expected minimum sampling time value, judging whether the duration values in a plurality of continuous PWM control periods adjacent to the current PWM control period are all greater than or equal to the expected minimum sampling time value;
and if the duration time values in a plurality of continuous PWM control periods adjacent to the current PWM control period are all larger than or equal to the expected minimum sampling time value, sampling the phase currents of any two phases of the inverter and reconstructing to obtain three-phase currents.
Optionally, in a case that the duration values of the actual samplable windows in a plurality of consecutive PWM control periods are not satisfied to be greater than or equal to the expected minimum sampling time value, sampling the dc bus current and reconstructing to obtain a three-phase current includes: and sampling the peak current of the direct current bus and reconstructing to obtain three-phase current.
Optionally, the consecutive plurality of PWM control periods includes all PWM control periods in at least one current fundamental period.
Optionally, the desired minimum sampling time value is set according to the following formula:
E＝Z+S+W
wherein E represents the expected minimum sampling time value, Z represents the current sampling signal oscillation time of the phase line end of the inverter, S represents the sampling and holding time of the sampling reconstruction module of the inverter, and W represents the sampling start delay time of the sampling reconstruction module of the inverter.
Optionally, the inverter includes multi-phase bridge arms connected in parallel between a positive end and a negative end of the dc power supply, each phase of the bridge arms includes power switching tubes respectively disposed on an upper bridge arm and a lower bridge arm of each phase of the bridge arms, the power switching tubes of the lower bridge arm of the phase sampled in the actual sampling window are in a conducting state under the action of a PWM control signal,
wherein obtaining a value for a duration of an actual sampleable window in each PWM control period comprises:
obtaining the delayed on-time and the delayed off-time of a lower bridge arm power switching tube of the inverter in the PWM control period and the dead time of a PWM control signal;
obtaining a time window which can be sampled in each PWM control period; and
and calculating the duration value of the actual sampling window in each PWM control period according to the delay on-time, the delay off-time, the dead time and the sampling time window.
Optionally, the duration value of the actual samplable window in each PWM control period is calculated according to the following formula:
R＝G-D-O+F
wherein R represents the duration value, G represents a time window in which sampling may be performed, D represents the dead time, O represents the delayed on-time, and F represents the delayed off-time.
Optionally, the control method further includes: the time window in which sampling can be performed is calculated according to the following formula:
G＝Ts-max(Ta，,Tb,Tc)
wherein, TsIndicating the PWM control period, T, of the PWM control signala、Tb、TcRespectively representing the conduction time, max (T), of the upper bridge arm power switching tube of the three-phase bridge arm of the inverter in each PWM control perioda,Tb,Tc) And the maximum value of the conduction time of the upper bridge arm power switching tube in the three-phase bridge arm of the inverter in each PWM control period is represented.
Optionally, the sampling and reconstructing the dc bus current to obtain a three-phase current includes:
dividing PWM control signals of an upper bridge arm power switching tube of the inverter into a maximum phase control signal, a middle phase control signal and a minimum phase control signal according to the conduction time of the upper bridge arm power switching tube in each PWM control period;
sampling a direct current bus current at a first time interval between edges of the maximum phase control signal and the intermediate phase control signal to obtain a phase current of a phase corresponding to the maximum phase control signal;
sampling a direct current bus current at a second time interval between edges of the minimum phase control signal and the intermediate phase control signal to obtain a phase current of a corresponding phase of the minimum phase control signal; and
and calculating the phase current of the bridge arm corresponding to the intermediate phase control signal according to the phase current of the phase corresponding to the maximum phase control signal and the phase current of the phase corresponding to the minimum phase control signal.
Optionally, the control method further includes: modulating a desired output voltage based on a voltage modulation algorithm to obtain the PWM control signal, the voltage modulation algorithm comprising SPWM, SVPWM, or DPWM.
According to another aspect of the embodiments of the present invention, there is provided a control circuit of an inverter, including:
a setting module for setting a desired minimum sampling time value;
the calculation module is used for obtaining the duration value of an actual sampling window in each PWM control period;
the first sampling reconstruction module is used for sampling and reconstructing phase currents of any two phases of the inverter to obtain three-phase currents under the condition that the duration values of the actual sampling windows in a plurality of continuous PWM control periods are all larger than or equal to the expected minimum sampling time value; and
and the second sampling reconstruction module is used for sampling the direct current bus current and reconstructing to obtain a three-phase current under the condition that the duration values of the actual sampling windows in a plurality of continuous PWM control periods are not larger than or equal to the expected minimum sampling time value.
Optionally, the control circuit further includes:
the first judgment module is used for judging whether the duration value is smaller than the expected minimum sampling time value or not in each PWM control period, and controlling the second sampling reconstruction module to sample the direct current bus current and reconstruct the direct current bus current to obtain a three-phase current when the duration value is smaller than the expected minimum sampling time value; and
and the second judging module is used for judging whether the duration values in a plurality of continuous PWM control periods adjacent to the current PWM control period are all larger than or equal to the expected minimum sampling time value when the duration values are larger than or equal to the expected minimum sampling time value, controlling the first sampling reconstruction module to sample any two-phase current in the inverter and reconstruct the phase current to obtain a three-phase current when the duration values in the plurality of continuous PWM control periods adjacent to the current PWM control period are all larger than or equal to the expected minimum sampling time value, and otherwise, selecting the second sampling reconstruction module to sample the direct current bus current and reconstruct the direct current bus current to obtain a three-phase current.
Optionally, the consecutive plurality of PWM control periods includes all PWM control periods in at least one current fundamental period.
Optionally, the setting module sets the expected minimum sampling time value according to the following formula:
E＝Z+S+W
wherein E represents the expected minimum sampling time value, Z represents the current sampling signal oscillation time of the phase line end of the inverter, S represents the sampling and holding time of the sampling reconstruction module of the inverter, and W represents the sampling start delay time of the sampling reconstruction module of the inverter.
Optionally, the inverter includes multi-phase bridge arms connected in parallel between a positive end and a negative end of the dc power supply, each phase of the bridge arms includes power switching tubes respectively disposed on an upper bridge arm and a lower bridge arm, the power switching tube of the lower bridge arm of the phase sampled in the actual sampling window is in a conducting state under the action of the PWM control signal,
the calculation module calculates the duration value of the actual sampling window in each PWM control period according to the following formula:
R＝G-D-O+F
wherein, R represents the duration value, G represents a time window capable of sampling, D represents the dead time of the PWM control signal, O represents the delay on-time of the lower bridge arm power switch tube of the inverter in the PWM control period, and F represents the delay off-time of the lower bridge arm power switch tube of the inverter in the PWM control period.
Optionally, the calculating module calculates the time window capable of sampling according to the following formula:
G＝Ts-max(Ta，,Tb,Tc)
wherein, TsRepresenting the PWM control period, Ta、Tb、TcRespectively representing the conduction time, max (T), of the upper bridge arm power switching tube of the three-phase bridge arm of the inverter in each PWM control perioda,Tb,Tc) And the maximum value of the conduction time of the upper bridge arm power switching tube of the multi-phase bridge arm of the inverter in each PWM control period is represented.
Optionally, dividing the PWM control signal of the upper arm power switching tube into a maximum phase control signal, a middle phase control signal and a minimum phase control signal according to the on-time of the upper arm of the inverter,
the first sampling reconstruction module is suitable for sampling a direct current bus current at a first time interval between edges of the maximum phase control signal and the intermediate phase control signal respectively to obtain a phase current of a phase corresponding to the maximum phase control signal, sampling the direct current bus current at a second time interval between edges of the minimum phase control signal and the intermediate phase control signal to obtain a phase current of a phase corresponding to the minimum phase control signal, and calculating to obtain a phase current of a phase corresponding to the intermediate phase control signal according to the phase current of the phase corresponding to the maximum phase control signal and the phase current of the phase corresponding to the minimum phase control signal.
Optionally, the control circuit is further configured to modulate the desired output voltage based on a voltage modulation algorithm to obtain the PWM control signal, where the voltage modulation algorithm includes SPWM, SVPWM, or DPWM.
Optionally, the second sampling reconstruction module is configured to sample a peak current of a dc bus in the inverter and reconstruct the peak current to obtain a three-phase current.
Optionally, the control circuit further includes: the first sampling unit is arranged on a direct-current bus of the inverter, and the second sampling reconstruction module is suitable for sampling through the first sampling unit to obtain direct-current bus current.
Optionally, the first sampling unit is selected from a sampling resistor or a current sensor.
Optionally, the control circuit further includes: the first sampling reconstruction module samples the current of the corresponding phase through the plurality of second sampling units to obtain the phase current.
Optionally, each second sampling unit includes a sampling resistor disposed on a bridge arm of the inverter, and the first sampling reconstruction module is adapted to sample voltage signals at two ends of the sampling resistor to obtain a current sampling signal of a phase current, and obtain the phase current of a corresponding phase according to the current sampling signal.
Optionally, each second sampling unit includes a current sensor disposed on a phase line of the inverter, and the first sampling reconstruction module samples through the current sensor to obtain a current sampling signal of a phase current, and obtains the phase current of a corresponding phase according to the current sampling signal.
Optionally, the first sampling reconstruction module is adapted to sample a voltage signal on an internal resistance of a power switch tube of a lower bridge arm of any two-phase bridge arm of the inverter to obtain phase currents of corresponding two phases.
The control method and the control circuit of the embodiment realize the switching of the sampling control mode by comparing the duration value of the actual sampling window in the PWM control period with the expected minimum sampling time value, do not need to calculate the square root, and are suitable for a low-cost microcontroller with weak computing capability.
Furthermore, the switching method of the embodiment is smoother and simpler, does not cause the system to switch back and forth between two sampling modes to reduce the control performance of the system, and can be applied to general voltage modulation algorithms such as SPWM and DPWM.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.
Fig. 1 shows a schematic view of a principle for controlling an electric machine with an inverter;
fig. 2 shows a schematic flow chart of a control method of an inverter according to a first embodiment of the invention;
FIG. 3 illustrates a waveform diagram of a PWM control signal during a PWM control period in accordance with an embodiment of the present invention;
fig. 4A to 4C respectively show waveform diagrams of three-phase PWM modulated waves obtained based on the SPWM, SVPWM and DPWM modulation schemes;
fig. 5A to 5C respectively show three kinds of structural schematic diagrams of an inverter according to a second embodiment of the present invention;
fig. 6 shows a schematic configuration diagram of a control circuit of an inverter according to a second embodiment of the present invention.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.
In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of components, are set forth in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.
It should be understood that in the following description, a "circuit" refers to a conductive loop formed by at least one element or sub-circuit through an electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.
Fig. 1 shows a schematic diagram of a conventional motor control using an inverter. As shown in fig. 1, the inverter 100 is implemented by, for example, a three-phase inverter, and includes a first phase arm a, a second phase arm B, and a third phase arm C, where each phase arm is formed by two power switching tubes connected in series (e.g., power switching tubes SW1-SW 6). Inverter 100 for converting dc power source VDCThe supplied direct current is converted into alternating current, and a modulation waveform is output by controlling the on and off of the power switching tubes SW1-SW6, thereby achieving the purpose of driving the motor 200.
Further, the inverter 100 controls the power switching tubes of the three-phase bridge arm to be turned on and off by a control method such as SVPWM, SPWM, or DPWM, for example, so as to convert the direct current into the alternating current.
It should be understood that the power switches SW1-SW6 in the inverter 100 are turned on in a complementary symmetrical manner, i.e., only one and only one power switch in the upper and lower arms of each phase of the inverter 100 is in a conducting state at the same time, and the PWM control signals provided to the upper and lower arms of the same phase have a complementary relationship. In the control process of the inverter 100, the power switching tube of the upper bridge arm of each phase is turned on, and the off state of the power switching tube of the lower bridge arm is represented by "1"; the power switch tube of the upper bridge arm of each phase is turned off, and the state that the power switch tube of the lower bridge arm is turned on is represented by "0". There are a total of eight switching states in inverter 100, as shown in table 1 below, including six fundamental voltage vectors U4, U6, U2, U3, U1, and U5, and two zero voltage vectors U0 and U7.
TABLE 1 space vector pulse width modulation algorithm voltage vector table
Figure BDA0002715856410000091
When a three-phase inverter is used for controlling a motor, three-phase current of the motor is required to be acquired frequently to perform closed-loop control, and the existing control method of the three-phase inverter has the technical problems of high cost, large occupied resource, insufficient effective vector action time in ultralow modulation ratio, noise introduced by phase shift and the like. Therefore, there is a need to improve the existing three-phase inverter to provide a universal and simple control method, which can be adapted to the current sampling and reconstruction of different voltage modulation algorithms.
Fig. 2 shows a schematic flow chart of a control method of an inverter according to a first embodiment of the invention. The inverter is implemented by an inverter 100 shown in fig. 1, for example, and includes a dc bus and a first phase arm a, a second phase arm B, and a third phase arm C connected in parallel to each other between a positive end and a negative end of a dc power supply, where each phase arm is composed of two power switching tubes connected in series (for example, power switching tubes SW1-SW6), and the power switching tubes SW1-SW6 are selected from IGBTs (Insulated Gate Bipolar transistors) or MOSFETs (Metal-Oxide-Semiconductor Field-Effect transistors, for example). The power switching tubes of the upper or lower leg of each phase are turned on and off based on a space vector pulse width modulation algorithm. As shown in fig. 2, the control method includes steps S01 to S06.
In step S01, a desired minimum sampling time value is set.
In step S02, the duration value of the actual samplable window in each PWM control period is calculated
In step S03, it is determined whether the duration value is less than a desired minimum sample time value within each PWM control period. In the case where the duration value is less than the desired minimum sample time value, continue to step S04; if the duration value is equal to or greater than the desired minimum sample time value, the process proceeds to step S05.
In step S04, the dc bus current in the inverter is sampled and reconstructed to obtain three-phase currents. Further, the method also comprises the step of sampling the peak current of the direct current bus current.
In step S05, it is determined whether the duration values in consecutive PWM control periods adjacent to the current PWM control period are each equal to or greater than the desired minimum sampling time value. If the duration values in a plurality of consecutive PWM control periods adjacent to the current PWM control period are all greater than or equal to the expected minimum sampling time value, continuing to step S06; otherwise, the process returns to step S04.
In step S06, the phase currents of any two phases of the inverter are sampled and reconstructed to obtain three-phase currents.
Specifically, the control method of this embodiment implements switching of the sampling mode by comparing the duration value of the actual sampling window in each PWM control period with the expected minimum sampling time value, and performs peak current sampling and reconstruction on the dc bus of the inverter to obtain the three-phase current when the duration value of the actual sampling window in the current PWM control period is smaller than the expected minimum sampling time value. Under the condition that the duration values of the actual sampling windows in all PWM control periods in one current fundamental wave period are larger than or equal to the expected minimum sampling time value, the phase currents of any two phases of the inverter are sampled, and the third phase current is reconstructed to obtain the three-phase current.
Fig. 4A to 4C respectively show waveform diagrams of three-phase PWM modulated waves obtained based on the SPWM, SVPWM, and DPWM modulation methods. In fig. 4A to 4C, the abscissa indicates the position of the fundamental wave voltage, the ordinate indicates the on-time of the upper arm of the multi-phase arm in the inverter, and A, B, C indicates the first phase arm, the second phase arm, and the third phase arm of the inverter, respectively. In addition, each current fundamental wave period includes a plurality of PWM control periods, the length of one current fundamental wave period is 2 pi, and since PWM modulation waveforms of different modulation schemes are different, it is necessary to determine the duration value of the actual samplable window of at least one fundamental wave current period.
Further, in step S01, it is necessary to obtain the oscillation time of the current sampling signal at the conduction instant of the lower bridge arm of any two-phase bridge arm of the inverter in advance, obtain the sample-hold time and the start-up sample delay time of the current sampling circuit in the inverter, and calculate the expected minimum sample time value according to the oscillation time of the current sampling signal, the sample-hold time and the start-up sample delay time. For example, the expected minimum sampling time value may be calculated according to the following formula:
E＝Z+S+W
wherein E represents the expected minimum sampling time value, Z represents the current sampling signal oscillation time of the phase line end of the inverter, S represents the sampling and holding time of the sampling reconstruction module of the inverter, and W represents the sampling start delay time of the sampling reconstruction module of the inverter.
Further, in step S02, it is required to obtain the delay on-time, the delay off-time, and the dead time of the lower arm power switching tube of the inverter, obtain a time window in which sampling can be performed in each PWM control period, and calculate a duration value of the actual samplable window in each PWM control period according to the delay on-time, the delay off-time, the dead time, and the time window in which sampling can be performed. For example, the duration value may be calculated according to the following formula:
R＝G-D-O+F
wherein R represents the duration value, G represents a time window in which sampling may be performed, D represents the dead time, O represents the delayed on-time, and F represents the delayed off-time. Further, the time window that can be sampled in each PWM control period can be calculated according to the following formula:
G＝Ts-max(Ta,Tb,Tc)
wherein, TsIndicating the PWM control period, T, of the PWM control signala、Tb、TcRespectively representing the conduction time, max (T), of the upper bridge arm of the three-phase bridge arm of the inverter in each PWM control perioda,Tb,Tc) And the maximum conduction time of an upper bridge arm of a three-phase bridge arm of the inverter in each PWM control period is represented.
Fig. 3 is a schematic diagram showing waveforms of PWM control signals in one PWM control period according to an embodiment of the present invention. In fig. 3, control signals PWMA-PWMC control the on and off of the upper arm power switching tubes of the first, second and third phase arms a, B and C, respectively, and T controls the inverter 100 in fig. 1a、TbAnd TcRespectively showing the high level time of the control signals PWMA-PWMC, namely the conduction time of the upper bridge arm power switching tubes of the first phase bridge arm A, the second phase bridge arm B and the third phase bridge arm C, and Ta>Tb>Tc，TsIndicating the PWM control period of the PWM control signal. Further, the control signal PWMA, the control signal PWMB, and the control signal PWMC are divided into a maximum phase control signal, an intermediate phase control signal, and a minimum phase control signal according to a high level time of the PWM control signal, and max (T)a,Tb,Tc) Indicating the high time of the maximum phase control signal, i.e. the active time T of the control signal PWMAaThereby can beThe time window over which sampling can be performed in the above equation is obtained as:
G＝Ts-Ta
the control method in this embodiment controls the signal according to the high level time T of the three-phase PWM control signala、TbAnd TcThe maximum value in the control method is calculated to obtain the duration value of the actual sampling window of the inverter, then the duration value is compared with the expected minimum sampling time value, and the sampling mode of the control circuit is switched according to the comparison result.
Further, the control method of this embodiment further includes: and under the condition that the duration values of the actual sampling windows in a plurality of continuous PWM control periods are not satisfied to be larger than or equal to the expected minimum sampling time value, sampling and reconstructing the direct-current bus current of the inverter according to the time intervals among the maximum phase control signal, the intermediate phase control signal and the minimum phase control signal to obtain the three-phase current of the inverter.
In particular, with continued reference to fig. 3, the dc bus current is sampled at a first time interval between edges of the maximum phase control signal and the intermediate phase control signal (i.e., between an upper edge of the maximum phase control signal and an upper edge of the intermediate phase control signal, or between a lower edge of the maximum phase control signal and a lower edge of the intermediate phase control signal) to obtain a phase current for the maximum phase control signal corresponding to the phase, which is the sampled current for the phase, at a second time interval between edges of the minimum phase control signal and the intermediate phase control signal (i.e., between an upper edge of the minimum phase control signal and an upper edge of the intermediate phase control signal, or between a lower edge of the minimum phase control signal and a lower edge of the intermediate phase control signal), and finally, calculating the phase current of the phase corresponding to the intermediate phase control signal according to the known phase currents of the two phases. Further, the phase current of the phase corresponding to the middle phase control signal is equal to the opposite number of the sum of the phase current of the phase corresponding to the maximum phase control signal and the phase current of the phase corresponding to the minimum phase control signal.
Further, the control method of the embodiment further includes: under the condition that the duration time values of the actual sampling windows in a plurality of continuous PWM control periods are all larger than or equal to the expected minimum sampling time value, when the power switch tubes of the lower bridge arms of the corresponding phases of the inverter are conducted, phase currents of any two phases of the inverter are sampled, and phase currents of a third phase are calculated according to the obtained phase currents of the two phases.
Specifically, taking a three-phase inverter as an example, the phase current of the third phase is equal to the opposite number of the sum of the sampled phase currents of the two phases.
Fig. 5A to 5C respectively show three kinds of structural schematic diagrams of an inverter according to a second embodiment of the present invention. As shown in fig. 5A to 5C, the motor system includes an inverter 100, a motor 200, a control circuit 300, and a first sampling unit 110 and a plurality of second sampling units 120 provided in the inverter 100.
Inverter 100 is used to drive motor 200. The inverter 100 is implemented, for example, by a three-phase inverter, and includes a first phase arm a, a second phase arm B, and a third phase arm C, each of which is composed of two power switching tubes connected in series (e.g., power switching tubes SW1-SW6), and the power switching tubes SW1-SW6 are selected from IGBTs (Insulated Gate Bipolar transistors) or MOSFETs (Metal-Oxide-Semiconductor Field-Effect transistors, for example). Inverter 100 for converting dc power source VDCThe supplied direct current is converted into alternating current, and modulated waves are output by controlling the on and off of the power switching tubes SW1-SW6, so that the purpose of driving the motor 200 is achieved.
Further, the inverter 100 controls the power switching tubes of the three-phase bridge arm to be turned on and off by a control method such as SVPWM, SPWM, or DPWM, for example, so as to convert the direct current into the alternating current.
It should be understood that the power switches SW1-SW6 in the inverter 100 are turned on in a complementary symmetrical manner, i.e., only one and only one power switch in the upper and lower arms of each phase of the inverter 100 is in a conducting state at the same time, and the PWM driving signals provided to the upper and lower arms of the same phase have a complementary relationship. In the control process of the inverter 100, the power switching tube of the upper bridge arm of each phase is turned on, and the off state of the power switching tube of the lower bridge arm is represented by "1"; the power switch tube of the upper bridge arm of each phase is turned off, and the state that the power switch tube of the lower bridge arm is turned on is represented by "0". There are a total of eight switching states in inverter 100 as shown in table 1 above.
Illustratively, the first sampling unit 110 is disposed on a dc bus of the inverter 100, and the number of the plurality of second sampling units 120 is two, and the two second sampling units are respectively disposed on any two phase lines of phase line ends of the inverter 100 or on a lower arm of any two phase arm. The control circuit 300 is configured to sample the dc bus current through the first sampling unit 110 to obtain a first phase current, a second phase current, and a third phase current, or sample the phase currents of any two phases of the inverter 100 through the plurality of second sampling units 120 to obtain the first phase current, the second phase current, and the third phase current.
As shown in fig. 5A, the second sampling unit 120 is a sampling resistor disposed on any two-phase bridge arm of the inverter 100, and the control circuit 300 obtains a current sampling signal of a phase current by sampling voltage signals at two ends of the sampling resistor connected in series to a lower bridge arm of any two-phase bridge arm, and obtains the phase current of the two phases according to the current sampling signal.
As shown in fig. 5B, the second sampling unit 120 is a current sensor disposed at the phase terminals of any two phases of the inverter 100, and the control circuit 300 obtains current sampling signals of phase currents by sampling the currents at the phase terminals of any two phases, and obtains the phase currents of the two phases according to the current sampling signals.
As shown in fig. 5C, the control circuit 300 may also directly sample the voltage signal of the internal resistance of the power switch tube of the lower arm of any two-phase arm of the inverter 100 to obtain the phase currents of the two phases.
In addition, in an embodiment, the first sampling unit 110 is a sampling resistor, the first sampling unit 110 is connected in series to the dc bus loop, and the control circuit 300 obtains a current sampling signal by sampling a voltage signal across the sampling resistor of the dc bus and performs reconstruction to obtain a three-phase current. In another embodiment, a current sensor is connected in series with a dc bus of the inverter, and the phase current is obtained by sampling and reconstructing a peak current signal of the dc bus.
As shown in fig. 6, the control circuit 300 includes a setting module 310, a calculating module 320, a first judging module 331, a second judging module 332, a first sample reconstructing module 340, and a second sample reconstructing module 350.
Wherein the setting module 310 is configured to set a desired minimum sample time value. Illustratively, the setting module 310 sets the desired minimum sample time value according to the following equation:
E＝Z+S+W
wherein E represents the expected minimum sampling time value, Z represents the current sampling signal oscillation time of the sampling reconstruction module of the inverter, S represents the sampling holding time of the sampling reconstruction module of the inverter, and W represents the sampling opening delay time of the sampling reconstruction module of the inverter.
The calculation module 320 is used to obtain the duration value of the actual samplable window in each PWM control period. The multi-phase bridge arms of the inverter 100 are connected in parallel between the positive end and the negative end of the dc power supply, and the upper bridge arm and the lower bridge arm of each phase of the bridge arm are respectively provided with a power switching tube, and the power switching tubes on the lower bridge arm of the phase sampled in the actual sampling window are in a conducting state under the action of a PWM control signal. The calculation module calculates the duration value of the actual sampling window in each PWM control period according to the following formula:
R＝G-D-O+F
wherein, R represents the duration value, G represents a time window which can be sampled in each PWM control period, D represents the dead time of the conduction of the power switch tube on the bridge arm, O represents the delay conduction time of the power switch tube on the bridge arm in one PWM control period, and F represents the delay turn-off time of the power switch tube on the bridge arm in one PWM control period.
Further, the calculating module 320 calculates the time window for sampling according to the following formula:
G＝Ts-max(Ta，,Tb,Tc)
wherein, TsIndicating the PWM control period, Ta、Tb、TcRespectively representing the conduction time, max (T), of the upper bridge arm of the three-phase bridge arm of the inverter in each PWM control perioda,Tb,Tc) And representing the maximum conduction time of the upper bridge arm in the three-phase bridge arms of the inverter in each PWM control period.
The first determining module 331 and the second determining module 332 are configured to determine whether the obtained duration value of the actual sampling window meets a preset condition, and start the first sampling reconstructing module 340 or the second sampling reconstructing module 350 according to the determination result.
Wherein the first sample reconstruction module 340 and the second sample reconstruction module 350 each comprise an analog-to-digital converter. The first sampling reconstruction module 340 is configured to sample and reconstruct the phase currents of any two phases in the inverter to obtain three-phase currents if the duration values of the actual samplable windows in a plurality of consecutive PWM control periods are all equal to or greater than the expected minimum sampling time value. The second sampling reconstruction module 350 is configured to sample and reconstruct the dc bus current (e.g., a peak current of the dc bus) to obtain a three-phase current if the duration value of the actual samplable window in a plurality of consecutive PWM control periods is not equal to or greater than the expected minimum sampling time value.
Specifically, the first determining module 331 is configured to determine whether the duration value is smaller than the expected minimum sampling time value in each PWM control period, and control the second sampling reconstructing module 350 to sample the dc bus current and reconstruct the dc bus current to obtain a three-phase current when the duration value is smaller than the expected minimum sampling time value. The second determining module 332 is configured to determine whether the duration values in multiple consecutive PWM control periods adjacent to the current PWM control period are all greater than or equal to the expected minimum sampling time value when the duration value is greater than or equal to the expected minimum sampling time value, and control the first sampling reconstructing module 340 to sample and reconstruct phase currents of any two phases in the inverter to obtain three-phase currents when the duration values in multiple consecutive PWM control periods adjacent to the current PWM control period are all greater than or equal to the expected minimum sampling time value, otherwise control the second sampling reconstructing module 350 to sample and reconstruct direct-current bus currents of the inverter to obtain three-phase currents.
Further, the first sampling reconstruction module 340 is configured to sample phase currents of any two phases of the inverter and calculate a phase current of a third phase according to the sampled phase currents, when the duration values of the actual samplable windows in a plurality of consecutive PWM control periods are all equal to or greater than the expected minimum sampling time value.
Specifically, taking a three-phase inverter as an example, the phase current of the third phase is equal to the opposite of the sum of the phase currents of the two phases that have been obtained.
Furthermore, the PWM control signals of the upper arm power switching tubes of the inverter 100 are divided into a maximum phase control signal, an intermediate phase control signal and a minimum phase control signal according to the on-time of the upper arm, and the second sampling reconfiguration module 350 is configured to sample and reconfigure the dc bus current of the inverter according to the time interval between the maximum phase control signal, the intermediate phase control signal and the minimum phase control signal to obtain the phase current of each phase of the inverter when the duration values of the actual samplable windows in a plurality of consecutive PWM control periods are not equal to or greater than the expected minimum sampling time value.
Specifically, the second sampling reconstruction module 350 samples the current of the direct current bus at a first time interval between the edges of the maximum phase control signal and the intermediate phase control signal, the value output by the analog-to-digital converter in the second sampling reconstruction module 350 is the phase current of the phase corresponding to the maximum phase control signal, the current of the direct current bus is sampled at a second time interval between the minimum phase control signal and the intermediate phase control signal, the opposite number of the values output by the analog-to-digital converter in the second sampling reconstruction module 350 is the phase current of the phase corresponding to the minimum phase control signal, and finally, the phase current of the phase corresponding to the intermediate phase control signal is calculated according to the phase currents of the two phases. For example, the phase current of the phase corresponding to the middle phase control signal is equal to the opposite number of the sum of the phase current of the phase corresponding to the maximum phase control signal and the phase current of the phase corresponding to the minimum phase control signal.
It should be understood that the control method and control circuit of embodiments of the present invention are applicable not only to current sampling of three-phase inverters, but also to current sampling of multiphase inverters. Therefore, modifications of the multiphase inverter based on the technical idea of the present invention also fall into the protection scope of the present invention.
In summary, the control method and the control circuit of the present embodiment implement switching of the sampling control mode by comparing the duration value of the actual sampling window in the PWM control period with the expected minimum sampling time value, and do not need to calculate the square root, so the method and the control circuit can be applied to a low-cost microcontroller with weak computing capability.
Furthermore, the switching method of the embodiment is smoother and simpler, does not cause the system to switch back and forth between two sampling modes to reduce the control performance of the system, and can be applied to general voltage modulation algorithms such as SPWM and DPWM.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims (25)

1. A control method of an inverter, characterized by comprising:
setting a desired minimum sample time value;
obtaining a duration value of an actual samplable window in each PWM control period;
under the condition that the duration values of the actual sampling windows in a plurality of continuous PWM control periods are all larger than or equal to the expected minimum sampling time value, sampling the phase currents of any two phases of the inverter and reconstructing to obtain three-phase currents;
and in the case that the duration values of the actual sampling windows in a plurality of continuous PWM control periods are not satisfied to be larger than or equal to the expected minimum sampling time value, sampling the direct current bus current and reconstructing to obtain three-phase current.
2. The control method according to claim 1, characterized by further comprising:
in each PWM control period, judging whether the duration value is smaller than the expected minimum sampling time value;
if the duration value is smaller than the expected minimum sampling time value, sampling the direct current bus current and reconstructing to obtain a three-phase current;
if the duration value is greater than or equal to the expected minimum sampling time value, judging whether the duration values in a plurality of continuous PWM control periods adjacent to the current PWM control period are all greater than or equal to the expected minimum sampling time value;
and if the duration time values in a plurality of continuous PWM control periods adjacent to the current PWM control period are all larger than or equal to the expected minimum sampling time value, sampling the phase currents of any two phases of the inverter and reconstructing to obtain three-phase currents.
3. The control method of claim 1, wherein the sampling and reconstructing the dc bus current to obtain a three-phase current without satisfying that the duration values of the actual samplable windows in the consecutive plurality of PWM control periods are all equal to or greater than the desired minimum sampling time value comprises: and sampling the peak current of the direct current bus and reconstructing to obtain three-phase current.
4. The control method of claim 1, wherein the consecutive plurality of PWM control periods comprises all PWM control periods in at least one current fundamental period.
5. The control method of claim 1, wherein the desired minimum sample time value is set according to the following formula:
E＝Z+S+W
wherein E represents the expected minimum sampling time value, Z represents the current sampling signal oscillation time of the phase line end of the inverter, S represents the sampling and holding time of the sampling reconstruction module of the inverter, and W represents the sampling start delay time of the sampling reconstruction module of the inverter.
6. The control method according to claim 1, wherein the inverter comprises multi-phase bridge arms connected in parallel between a positive terminal and a negative terminal of the DC power supply, each phase bridge arm comprises power switching tubes respectively arranged at an upper bridge arm and a lower bridge arm of each phase bridge arm, the power switching tubes of the lower bridge arm of the phase sampled within the actual samplable window are in a conducting state under the action of a PWM control signal,
wherein obtaining a value for a duration of an actual sampleable window in each PWM control period comprises:
obtaining the delayed on-time and the delayed off-time of a lower bridge arm power switching tube of the inverter in the PWM control period and the dead time of a PWM control signal;
obtaining a time window which can be sampled in each PWM control period; and
and calculating the duration value of the actual sampling window in each PWM control period according to the delay on-time, the delay off-time, the dead time and the sampling time window.
7. The control method according to claim 6, wherein the value of the duration of the actual sampleable window in each PWM control period is calculated according to the following formula:
R＝G-D-O+F
wherein R represents the duration value, G represents a time window in which sampling may be performed, D represents the dead time, O represents the delayed on-time, and F represents the delayed off-time.
8. The control method according to claim 7, characterized by further comprising: the time window in which sampling can be performed is calculated according to the following formula:
G＝Ts-max(Ta,Tb,Tc)
wherein, TsIndicating PWM control period of PWM control signalPeriod T ofa、Tb、TcRespectively representing the conduction time, max (T), of the upper bridge arm power switching tube of the three-phase bridge arm of the inverter in each PWM control perioda,Tb,Tc) And the maximum value of the conduction time of the upper bridge arm power switching tube in the three-phase bridge arm of the inverter in each PWM control period is represented.
9. The control method of claim 6, wherein the sampling and reconstructing the DC bus current to obtain three-phase currents comprises:
dividing PWM control signals of an upper bridge arm power switching tube of the inverter into a maximum phase control signal, a middle phase control signal and a minimum phase control signal according to the conduction time of the upper bridge arm power switching tube in each PWM control period;
sampling a direct current bus current at a first time interval between edges of the maximum phase control signal and the intermediate phase control signal to obtain a phase current of a phase corresponding to the maximum phase control signal;
sampling a direct current bus current at a second time interval between edges of the minimum phase control signal and the intermediate phase control signal to obtain a phase current of a corresponding phase of the minimum phase control signal; and
and calculating the phase current of the bridge arm corresponding to the intermediate phase control signal according to the phase current of the phase corresponding to the maximum phase control signal and the phase current of the phase corresponding to the minimum phase control signal.
10. The control method according to claim 6, characterized by further comprising: modulating a desired output voltage based on a voltage modulation algorithm to obtain the PWM control signal, the voltage modulation algorithm comprising SPWM, SVPWM, or DPWM.
11. A control circuit for an inverter, the control circuit comprising:
a setting module for setting a desired minimum sampling time value;
the calculation module is used for obtaining the duration value of an actual sampling window in each PWM control period;
the first sampling reconstruction module is used for sampling and reconstructing phase currents of any two phases of the inverter to obtain three-phase currents under the condition that the duration values of the actual sampling windows in a plurality of continuous PWM control periods are all larger than or equal to the expected minimum sampling time value; and
and the second sampling reconstruction module is used for sampling the direct current bus current and reconstructing to obtain the three-phase current under the condition that the duration values of the actual sampling windows in a plurality of continuous PWM control periods are not satisfied to be larger than or equal to the expected minimum sampling time value.
12. The control circuit of claim 11, further comprising:
the first judgment module is used for judging whether the duration value is smaller than the expected minimum sampling time value or not in each PWM control period, and controlling the second sampling reconstruction module to sample the direct current bus current and reconstruct the direct current bus current to obtain a three-phase current when the duration value is smaller than the expected minimum sampling time value; and
and the second judging module is used for judging whether the duration values in a plurality of continuous PWM control periods adjacent to the current PWM control period are all larger than or equal to the expected minimum sampling time value when the duration values are larger than or equal to the expected minimum sampling time value, controlling the first sampling reconstruction module to sample any two-phase current in the inverter and reconstruct the phase current to obtain a three-phase current when the duration values in the plurality of continuous PWM control periods adjacent to the current PWM control period are all larger than or equal to the expected minimum sampling time value, and otherwise, selecting the second sampling reconstruction module to sample the direct current bus current and reconstruct the direct current bus current to obtain a three-phase current.
13. The control circuit of claim 11, wherein the consecutive plurality of PWM control periods comprises all PWM control periods of at least one current fundamental period.
14. The control circuit of claim 11, wherein the setting module sets the desired minimum sample time value according to the following equation:
E＝Z+S+W
wherein E represents the expected minimum sampling time value, Z represents the current sampling signal oscillation time of the phase line end of the inverter, S represents the sampling and holding time of the sampling reconstruction module of the inverter, and W represents the sampling start delay time of the sampling reconstruction module of the inverter.
15. The control circuit of claim 11, wherein the inverter comprises multi-phase legs connected in parallel between a positive terminal and a negative terminal of the DC supply, each phase leg comprising power switching tubes respectively disposed in an upper leg and a lower leg, the power switching tubes of the lower leg of the phase sampled within the actual samplable window being in a conducting state under the action of the PWM control signal,
the calculation module calculates the duration value of the actual sampling window in each PWM control period according to the following formula:
R＝G-D-O+F
wherein, R represents the duration value, G represents a time window capable of sampling, D represents the dead time of the PWM control signal, O represents the delay on-time of the lower bridge arm power switch tube of the inverter in the PWM control period, and F represents the delay off-time of the lower bridge arm power switch tube of the inverter in the PWM control period.
16. The control circuit of claim 15, wherein the calculation module calculates the time window over which sampling can be performed according to the following equation:
G＝Ts-max(Ta,Tb,Tc)
wherein, TsRepresenting the PWM control period, Ta、Tb、TcRespectively representing the conduction time, max (T), of the upper bridge arm power switching tube of the three-phase bridge arm of the inverter in each PWM control perioda,Tb,Tc) And the maximum value of the conduction time of the upper bridge arm power switching tube of the multi-phase bridge arm of the inverter in each PWM control period is represented.
17. The control circuit of claim 16, wherein the PWM control signals of the upper arm power switching tubes are divided into a maximum phase control signal, a middle phase control signal, and a minimum phase control signal according to the on-time of the upper arm of the inverter,
the first sampling reconstruction module is suitable for sampling a direct current bus current at a first time interval between edges of the maximum phase control signal and the intermediate phase control signal respectively to obtain a phase current of a phase corresponding to the maximum phase control signal, sampling the direct current bus current at a second time interval between edges of the minimum phase control signal and the intermediate phase control signal to obtain a phase current of a phase corresponding to the minimum phase control signal, and calculating to obtain a phase current of a phase corresponding to the intermediate phase control signal according to the phase current of the phase corresponding to the maximum phase control signal and the phase current of the phase corresponding to the minimum phase control signal.
18. The control circuit of claim 15, wherein the control circuit is further configured to modulate a desired output voltage based on a voltage modulation algorithm to obtain the PWM control signal, the voltage modulation algorithm comprising SPWM, SVPWM, or DPWM.
19. The control circuit of claim 11, wherein the second sampling reconstruction module is configured to sample a peak current of a dc bus in the inverter and reconstruct a three-phase current.
20. The control circuit of claim 11, further comprising:
the first sampling unit is arranged on a direct-current bus of the inverter, and the second sampling reconstruction module is suitable for sampling through the first sampling unit to obtain direct-current bus current.
21. The control circuit of claim 20, wherein the first sampling unit is selected from a sampling resistor or a current sensor.
22. The control circuit of claim 11, further comprising:
the first sampling reconstruction module samples the current of the corresponding phase through the plurality of second sampling units to obtain the phase current.
23. The control circuit according to claim 22, wherein each of the second sampling units includes a sampling resistor disposed on a bridge arm of the inverter, and the first sampling reconstruction module is adapted to sample a voltage signal across the sampling resistor to obtain a current sampling signal of a phase current, and obtain the phase current of a corresponding phase according to the current sampling signal.
24. The control circuit according to claim 22, wherein each of the second sampling units includes a current sensor disposed on a phase line of the inverter, and the first sampling reconstruction module performs sampling by the current sensor to obtain a current sampling signal of a phase current, and obtains the phase current of a corresponding phase according to the current sampling signal.
25. The control circuit of claim 11, wherein the first sampling reconstruction module is adapted to sample a voltage signal across a power switch tube resistor of a lower leg of any two-phase leg of the inverter to obtain phase currents of the corresponding two phases.
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Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11289771A (en) * 1998-03-13 1999-10-19 Internatl Rectifier Corp Linear current sensing circuit for motor controller
WO2006074120A2 (en) * 2005-01-03 2006-07-13 International Rectifier Corporation Circuit to improve motor phase current reconstruction via dc link
CN101515764A (en) * 2009-04-08 2009-08-26 宁波德斯科电子科技有限公司 Current sampling circuit used for frequency converter and sampling method thereof
CN105450095A (en) * 2015-12-16 2016-03-30 四川长虹电器股份有限公司 Single-resistor current sampling method and air conditioning device
CN105577062A (en) * 2015-12-31 2016-05-11 美的集团武汉制冷设备有限公司 Single current sensor based three-phase current reconstruction method and device
EP3062428A2 (en) * 2015-02-28 2016-08-31 Rockwell Automation Technologies, Inc. Inverter phase current reconstruction apparatus and methods
CN106452261A (en) * 2016-10-19 2017-02-22 南京理工大学 BCPWM based phase current reconstruction method and device
CN110868123A (en) * 2018-08-09 2020-03-06 北京大学 Motor asymmetric SVPWM reconstruction method based on zero vector insertion
CN110912437A (en) * 2019-12-02 2020-03-24 青岛大学 Single current sampling type three-phase power conversion circuit

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6984953B2 (en) * 2003-01-20 2006-01-10 International Rectifier Corporation Method and apparatus for reconstructing motor current from DC bus current
CN101769953B (en) * 2010-01-14 2012-10-17 东元总合科技（杭州）有限公司 Phase current detection method of motor based on direct-current bus current
CN106443133B (en) * 2016-10-31 2019-02-15 广东美的制冷设备有限公司 Air-conditioning system, the current sample method and apparatus of three-phase inverting circuit

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11289771A (en) * 1998-03-13 1999-10-19 Internatl Rectifier Corp Linear current sensing circuit for motor controller
WO2006074120A2 (en) * 2005-01-03 2006-07-13 International Rectifier Corporation Circuit to improve motor phase current reconstruction via dc link
CN101515764A (en) * 2009-04-08 2009-08-26 宁波德斯科电子科技有限公司 Current sampling circuit used for frequency converter and sampling method thereof
EP3062428A2 (en) * 2015-02-28 2016-08-31 Rockwell Automation Technologies, Inc. Inverter phase current reconstruction apparatus and methods
CN105450095A (en) * 2015-12-16 2016-03-30 四川长虹电器股份有限公司 Single-resistor current sampling method and air conditioning device
CN105577062A (en) * 2015-12-31 2016-05-11 美的集团武汉制冷设备有限公司 Single current sensor based three-phase current reconstruction method and device
CN106452261A (en) * 2016-10-19 2017-02-22 南京理工大学 BCPWM based phase current reconstruction method and device
CN110868123A (en) * 2018-08-09 2020-03-06 北京大学 Motor asymmetric SVPWM reconstruction method based on zero vector insertion
CN110912437A (en) * 2019-12-02 2020-03-24 青岛大学 Single current sampling type three-phase power conversion circuit

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