CN117393604A - SiC VDMOSFET structure with suppressed gate-source voltage overshoot with increased JFET region source contact - Google Patents

SiC VDMOSFET structure with suppressed gate-source voltage overshoot with increased JFET region source contact Download PDF

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CN117393604A
CN117393604A CN202311447930.7A CN202311447930A CN117393604A CN 117393604 A CN117393604 A CN 117393604A CN 202311447930 A CN202311447930 A CN 202311447930A CN 117393604 A CN117393604 A CN 117393604A
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type semiconductor
semiconductor region
gate
region
sic
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许一力
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Hangzhou Spectro Crystal Semiconductor Technology Co ltd
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Hangzhou Spectro Crystal Semiconductor Technology Co ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7804—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a pn-junction diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure

Abstract

The invention discloses a SiC VDMOSFET structure with a function of inhibiting gate-source voltage overshoot, which is added with source contact of a JFET region, and comprises a plurality of strip-shaped MOS cells connected in parallel, wherein at least one of the MOS cells is provided with N+/P+/polySi back-to-back diodes, the N+/P+/polySi back-to-back diodes are naturally added by utilizing the basic structure of the MOS cells, the area of a source region is saved, the current density is higher, the effect of effectively inhibiting the voltage overshoot by utilizing tunneling effect when the gate source is overvoltage is realized, siC MOS gate oxide is protected from being degraded or damaged by extremely high voltage stress impact, in addition, a Schottky junction is introduced into the region in the same cell to form Schottky contact, on one hand, the dead area of a G electrode and a D electrode is reduced, the Crss of a silicon carbide VDMOSFET is greatly reduced, the switching loss of the device is further greatly reduced, and on the other hand, the top end of the region adopts the Schottky contact, the starting voltage of a body diode of the silicon carbide MOSFET device is greatly reduced, and the forward voltage drop of the body diode is further reduced.

Description

SiC VDMOSFET structure with suppressed gate-source voltage overshoot with increased JFET region source contact
Technical Field
The invention relates to the technical field of gate-source voltage overshoot improvement in a chip structure of a SiC MOSFET device, in particular to a SiC VDMOSFET structure with a function of inhibiting gate-source voltage overshoot, wherein the SiC VDMOSFET structure is used for increasing source contact of a JFET region.
Background
The SiC MOSFET device has the remarkable advantages of high frequency and low loss, and has very wide application in the fields of electric automobiles, photovoltaic inverters, charging piles and the like. However, the extremely fast switching speed of the SiC MOSFET causes the problem that the device is extremely easy to generate gate-source voltage overshoot in the switching-on and switching-off processes, so that the SiC MOS gate oxide bears extremely high voltage stress, and the phenomenon that the gate oxide performance is degraded and even the gate is damaged easily occurs in the long-term use process. In order to suppress the problem of gate-source voltage overshoot during switching, methods such as increasing the gate driving resistance to reduce the switching speed and externally connecting a zener diode between the gate and source electrodes are generally employed. Although the problem of voltage overshoot in the switching process is effectively relieved by increasing the gate driving resistance, the longer switching time not only increases the switching loss, but also cannot fully exert the performance advantage of the high-speed switch of the SiCNOSFET. Similarly, connecting a zener diode externally between the gate and source electrodes increases the capacitance between the gate and source electrodes, reducing the switching speed of the SiC MOSFET. In addition, since the external zener diode is usually a commercial device with a fixed model, the voltage stabilizing performance, parasitic capacitance and the like of the external zener diode cannot be directly and optimally matched with the SiC MOSFET, and the full play of the performance of the SiC MOSFET device is severely limited. Fig. 1 and 2 illustrate two common methods of suppressing voltage overshoot during the fast switching of a SiC MOSFET. The prior art that the cell structure of the SiCNOSFET utilizes natural back-to-back diodes to realize voltage stabilizing effect and does not change the size of the device has not been leaked, in addition, in consideration of the performance aspect of the device, the body diode of the traditional VDMOSFET device mainly consists of PN junctions, and the starting voltage of the traditional VDMOSFET device is relatively large. The Crss of the conventional VDMOSFET is also large because of the large facing area of the gate (G-pole) and drain (D-pole). The parameters of Ciss, coss and the like of the device are directly caused to be larger because of larger Crss, so that the switching loss of the device is increased, and the patent provides an omnibearing performance solution for the SiC MOSFET device.
Disclosure of Invention
1. Accordingly, the present invention is directed to a SiC VDMOSFET structure with increased JFET region source contact for suppressing gate-source voltage overshoot, which is configured by monolithically integrating an n+/p+/polySi structure between the gate and the source in the cell of the original SiC VDMOSFET, to construct two back-to-back clamp diodes, one of which is an n+/p+ diode and the other of which is a p+/polySi heterojunction diode, so as to avoid the overvoltage stress of the gate-source electrode due to severe oscillation during the switching process. In addition, the N+/P+/polySi structure integrated on the chip can directly realize the optimal matching of voltage stabilizing performance, parasitic capacitance parameters and SiC MOSFET performance through the methods of process parameter optimization, layout design, optimization and the like, so that the voltage overshoot in the quick switching process of the SiC MOSFET can be effectively restrained, the design and optimization of a high-speed drive control circuit of the SiC MOSFET are greatly simplified, the dead area of a G pole and a D pole is reduced by splitting a polysilicon gate at the top end of a JFET region of the VDMOSFET, the Crss of the silicon carbide VDMOSFET is greatly reduced, the switching loss of the device is further greatly reduced, the Schottky contact is adopted at the top end of the JFET region, the starting voltage of a body diode of the silicon carbide MOSFET device is greatly reduced, and the forward voltage drop of the body diode is further reduced.
To solve the above technical problems, the present invention provides a SiC VDMOSFET structure with a gate-source voltage overshoot suppression for increasing source contact of JFET region, comprising a plurality of parallel-connected stripe-shaped MOS cells, at least one of the MOS cells having n+/p+/polySi back-to-back diodes therein, the n+/p+/polySi back-to-back diodes comprising a p+2 type semiconductor region formed in an n+ type semiconductor region on one side of the MOS cells by ion implantation, ohmic contacts of the n+ type semiconductor region shorting the source to form n+/p+ junction diodes on the source side, the p+2 type semiconductor region directly contacting one end polysilicon gate of the MOS cell to form p+/polySi heterojunction diodes; the MOS cell is provided with a JFET region, the position of the polysilicon gate on the JFET region is broken to form two sections of polysilicon gates, and the source electrode is in direct contact with the JFET region through the two sections of polysilicon gates to form a Schottky junction.
In some embodiments, the p+2 type semiconductor region is located in the middle or not near the side of the n+ type semiconductor region.
In some embodiments, preferably, the polysilicon gate is located directly above the p+2 type semiconductor region and penetrates through the gate oxide layer of the MOS cell and is connected with the gate oxide layer, and the polysilicon gate is only in contact with the p+2 type semiconductor region.
In some embodiments, preferably, the SiC VDMOSFET includes a silicon carbide epitaxial layer, a P-type semiconductor region with equidistant well-shaped distribution is formed on the silicon carbide epitaxial layer by ion implantation, a p+1-type semiconductor region is formed in the middle of the P-type semiconductor region by ion implantation with the same extremely high concentration, an n+ type semiconductor region located at two sides of the p+1-type semiconductor region is formed on the P-type semiconductor region by ion implantation, a JFET region is formed between adjacent P-type semiconductor regions, a gate oxide layer is deposited on the JFET region, the gate oxide layer covers at least a P-type semiconductor region including at least a region and the n+ type semiconductor region, a polysilicon gate is deposited on the gate oxide layer, a dielectric layer is deposited on the polysilicon gate, and a source is uniformly deposited on the P-type semiconductor region, the n+ type semiconductor region and the dielectric layer, wherein, for facilitating understanding of MOS cells, a semiconductor cell region covered under the polysilicon gate and within a two symmetrical NPN structure regions for forming a switching path is defined as a MOS cell.
In some embodiments, preferably, the gate oxide layer is also broken by the schottky junction to form a dielectric layer 1 and a dielectric layer 2 respectively located below the two sections of the polysilicon gate, and the dielectric layer is also broken and respectively forms a dielectric layer 1 and a dielectric layer 2 respectively wrapping the two sections of the polysilicon gate.
In some embodiments, a preferred approach is one in which the p+1-type semiconductor region and the p+2-type semiconductor region are implanted with the same ions.
In some embodiments, preferably, the silicon carbide epitaxial layer has an N substrate below, and a drain below the N substrate.
In some embodiments, preferably, the P-type semiconductor region is implanted with Al ions or B ions, the p+1-type semiconductor region and the p+2-type semiconductor region are implanted with Al ions or B ions with extremely high concentration, and the n+ type semiconductor region is implanted with P ions or N ions with extremely high concentration.
In some embodiments, the dielectric layer is preferably SiO 2 。
Compared with the prior art, the invention has the following advantages:
1. according to the invention, an N-SiC/P-SiC structure in a SiC MOSFET cell structure is utilized, and a P-SiC/polySi heterojunction is constructed, so that the integration of back-to-back clamp diodes between gate and source electrodes can be realized in a simple and efficient manner. The original PN junction part can be used as a surge injection part of the existing body diode. The structure is equivalent to changing a body diode of the original structure from a PN junction diode into a Schottky diode with an anti-surge current function, greatly improving the characteristics of the body diode of the device, separating a polysilicon gate of a JFET region, reducing the coverage area of a gate, directly reducing the Crss of the device, further reducing a series of electrical parameter values of Ciss, coss, qg, eon, eoff and the like of the device, enabling the performance of the device to be more excellent, protecting the device from various aspects and improving the practicability of the device in all directions.
2. When the structure is monolithically integrated with the N-SiC/P-SiC/polySi structure, the gate polysilicon in part of cell structures is directly contacted with the P-SiC to form a heterojunction diode in the layout design of the SiC MOSFET chip, and ohmic contact and source metal on an N+ type semiconductor region beside the P-SiC are short-circuited, so that the N-SiC/P-SiC/polySi structure can be locally formed in the layout, and the practical implementation method is simple, convenient and feasible.
3. Forward and reverse overvoltage protection between the gate and source electrodes of the SiC MOSFET can be realized at the same time.
4. Through structure or process optimization, the best matching of the SiC MOSFET and the integrated N-SiC/P-SiC/polySi structure performance is easy to realize.
5. The monolithic integrated structure process of the invention is completely compatible with the SiC MOSFET, and has low realization cost and high performance.
6. The structure of the invention is integrated with the N-SiC/P-SiC/polySi structure into the P-WELL, thereby saving the area of the source region and having larger current density.
Drawings
Fig. 1 is a diagram of a conventional SiC MOSFET local on-chip structure in which a drive resistor is regulated to suppress gate-source voltage overshoot.
Fig. 2 is a partial on-chip structure diagram of a SiC MOSFET with a conventional external zener diode to suppress gate-source voltage overshoot.
Fig. 3 is a schematic diagram of a partial cross-sectional structure of a SiC VDMOSFET of the present invention.
Detailed Description
In order to facilitate understanding of the technical scheme of the present invention, the following detailed description is made with reference to the accompanying drawings and specific embodiments.
Referring to fig. 3, in the present embodiment, there is provided a conventional SiC VDMOSFET structure including a plurality of stripe-shaped MOS cells connected in parallel, in order to facilitate understanding of the MOS cells, a semiconductor region within a range of two symmetrical NPN structures covered under a polysilicon gate electrode for forming a switching path is defined as a MOS cell, a structure of one cell is specifically described below, in the SiC VDMOSFET, a silicon carbide epitaxial layer is included, P-type semiconductor regions are formed on the silicon carbide epitaxial layer by ion implantation to be equally spaced in a well shape, a P +1 type semiconductor region is formed in the middle of the P-type semiconductor region by ion implantation of the same extremely high concentration, N + type semiconductor regions are formed on both sides of the P +1 type semiconductor region by ion implantation, a JFET region is formed between adjacent P-type semiconductor regions, a gate oxide layer is deposited on the JFET region, the gate oxide layer covers the P-type semiconductor region at least comprising JFET region and N+ type semiconductor region, polysilicon gate is deposited on the gate oxide layer, medium layer is deposited on the polysilicon gate, source is uniformly deposited on the P-type semiconductor region, N+ type semiconductor region, medium layer, N substrate is arranged under the silicon carbide epitaxial layer, drain is arranged under the N substrate, in the invention, the P-type semiconductor region is implanted with Al ion or B ion, P+1 type semiconductor region and P+2 type semiconductor region are implanted with Al ion or B ion with extremely high concentration, N+ type semiconductor region is implanted with P ion or N ion with extremely high concentration, in the embodiment, the P-type semiconductor region is implanted with Al ion, P+1 type semiconductor region and P+2 type semiconductor region are implanted with Al ion with extremely high concentration, N+ type semiconductor region is implanted with extremely high concentrationP ion with concentration, and SiO as dielectric layer 2 。
In the present invention, at least one MOS cell has an N+/P+/polySi back-to-back diode, in this embodiment, two consecutive cells have an N+/P+/polySi back-to-back diode, the N+/P+/polySi back-to-back diode comprises a P+2 type semiconductor region formed in an N+ type semiconductor region at one side of the MOS cell by ion implantation, the P+2 type semiconductor region is positioned at the middle part or not close to the side in the N+ type semiconductor region, i.e. the N+ type semiconductor region is left at two sides of the P+2 type semiconductor region, in the present invention, the P+1 type semiconductor region and the P+2 type semiconductor region are implanted into the same Al ions, the ohmic contact source of the N+ type semiconductor region is shorted to form an N+/P+ junction diode at the source side, the P+2 type semiconductor region is directly contacted with one end polysilicon gate of the MOS cell, the polysilicon gate is located on the upper part of the P+2 type semiconductor region and penetrates through the gate oxide layer of the MOS cell and is connected with the P+2 type semiconductor region, namely, the polysilicon gate is only partially connected to the P+2 type semiconductor region on the basis of not influencing the basic performance of the MOS cell, other gate oxide layers and basic switch structures of the MOS cell are not influenced to form a P+/poly Si heterojunction diode, in addition, the part of the polysilicon gate located on the JFET region is broken to form two sections of polysilicon gates, the polysilicon gates at two ends are respectively located on corresponding channels to ensure the gate function, the source electrode is directly contacted with the JFET region through the two sections of polysilicon gates to form a Schottky junction, the gate oxide layer is also broken by the Schottky junction to form the polysilicon gates respectively located below the two sections of polysilicon gates, the dielectric layer is broken and forms a dielectric layer 1 and a dielectric layer 2 which wrap two sections of the polycrystalline silicon grid respectively, and the polycrystalline silicon grid at the top end of the JFET region of the VDMOSFET is split, so that on one hand, the facing area of the G electrode and the D electrode is reduced, the grid coverage area is reduced, the Crss of the device is directly reduced, a series of electrical parameter values such as Ciss, coss, qg, eon, eoff of the device are further reduced, the device performance is more excellent, the switching loss of the device is further greatly reduced, on the other hand, the Schottky contact is adopted at the top end of the JFET region, the starting voltage of the body diode of the silicon carbide MOSFET device can be greatly reduced, the forward voltage drop of the body diode is reduced, the Schottky contact end is introduced into the JFET region during operation, the Schottky junction formed by the Schottky contact is firstly started when the body diode is connected with the forward voltage, the PN junction diode is started when the voltage is continuously increased, and the resistance is further reduced. The original PN junction part can be used as a surge injection part of the existing body diode. The structure is equivalent to changing the body diode with the original structure from a PN junction diode into a Schottky diode with the surge current resistance function, and the body diode characteristic of the device is greatly improved. During manufacturing, only a P+ type semiconductor region is added into an N+ type semiconductor region in a part of cell structure in the layout design of the SiC MOSFET chip, then grid polysilicon is directly contacted with P-SiC to form a heterojunction diode, ohmic contact on an N well beside the P-SiC is in short circuit with source metal, an N-SiC/P-SiC/poly Si structure is formed locally in the layout, and two back-to-back clamping diodes are constructed between gate source electrodes. In operation, as the doping concentration at two sides of the N+P+ junction is extremely high, the effect of clamping voltage stabilization can be realized, meanwhile, the potential barrier height of the P-SiC/polySi heterojunction diode is limited, the effect of clamping voltage stabilization also exists, the effect of clamping voltage stabilization can be realized, and when the grid source electrode is in forward overvoltage, the P-SiC/polySi heterojunction structure has tunneling, so that the SiC MOS grid oxide is prevented from being subjected to forward overvoltage stress; when the grid source electrode is in negative overvoltage, tunneling occurs in the N+ (source side) P+ reverse bias structure, so that the grid oxide of the SiC MOS is prevented from being subjected to negative overvoltage stress, voltage overshoot is effectively restrained by utilizing tunneling effect when the grid source is in overvoltage, and the grid oxide of the SiC MOS is prevented from being degraded or damaged due to extremely high voltage stress. In addition, the optimal adaptation performance adjustment invention can be realized by adjusting the doping concentration and other methods, so that the integrated structure is ensured to have the expected clamping capability, and the optimal performance matching with the SiC MOSFET is realized. The on-chip integrated N-SiC/P-SiC/polySi structure is integrated into the P-WELL, so that the single repeated cell size is greatly reduced, the source area is saved, and the current density is higher.
The foregoing is merely a preferred embodiment of the present invention, and the scope of the invention is defined by the claims, and those skilled in the art should also consider the scope of the present invention without departing from the spirit and scope of the invention.

Claims (7)

1. SiC VDMOSFET structure with suppressed gate-source voltage overshoot with increased source contact of JFET region comprising a plurality of parallel connected stripe-shaped MOS cells characterized in that at least one of said MOS cells has n+/p+/polySi back-to-back diode comprising p+2 type semiconductor region formed in n+ type semiconductor region on one side of said MOS cell by ion implantation, ohmic contact of said n+ type semiconductor region shorting source to form n+/p+ junction diode on source side, said p+2 type semiconductor region directly contacting one end polysilicon gate of MOS cell to form p+/polySi heterojunction diode;
the MOS cell is provided with a JFET region, the position of the polysilicon gate on the JFET region is broken to form two sections of polysilicon gates, and the source electrode is in direct contact with the JFET region through the two sections of polysilicon gates to form a Schottky junction.
2. The SiC VDMOSFET structure of claim 1 having a gate-source voltage overshoot suppression for increasing the source contact of the JFET region, wherein the P +2 semiconductor region is located in the middle or not near the sides of the N + semiconductor region.
3. The SiC VDMOSFET structure of claim 1 having a gate-source voltage overshoot suppression for increasing the source contact of the JFET region, wherein said polysilicon gate is located directly above said p+2 type semiconductor region and extends through and connects to the gate oxide layer of said MOS cell, said polysilicon gate being in contact with only said p+2 type semiconductor region.
4. The SiC VDMOSFET structure of claim 1, wherein the SiC VDMOSFET structure comprises a silicon carbide epitaxial layer, a P-type semiconductor region is formed on the silicon carbide epitaxial layer by ion implantation, the P-type semiconductor region is formed in the middle of the P-type semiconductor region by ion implantation with the same extremely high concentration, a p+1-type semiconductor region is formed on the P-type semiconductor region by ion implantation, the n+ type semiconductor regions are formed on both sides of the p+1-type semiconductor region, the NPN region is formed between adjacent P-type semiconductor regions, a gate oxide layer is deposited on the JFET region, the gate oxide layer covers the P-type semiconductor region at least comprising the JFET region and the n+ type semiconductor region, the polysilicon gate is deposited on the gate oxide layer, a dielectric layer is deposited on the polysilicon gate, the P-type semiconductor region, the n+ type semiconductor region and the dielectric layer are uniformly deposited, wherein for understanding the MOS cell is defined as a polysilicon cell structure in which two symmetrical channel regions are formed under the JFET region;
the P+1 type semiconductor region and the P+2 type semiconductor region are implanted into the same ion;
the gate oxide layer is also broken by the Schottky junction to form a dielectric layer 1 and a dielectric layer 2 which are respectively positioned below the two sections of the polysilicon gate, and the dielectric layer is also broken and respectively wraps the two sections of the polysilicon gate.
5. The SiC VDMOSFET structure with suppressed gate-source voltage overshoot of the increased source contact of the JFET region of claim 4, wherein the silicon carbide epitaxial layer has an N substrate below and a drain below the N substrate.
6. The SiC VDMOSFET structure of claim 4 wherein the P-type semiconductor region implanted ions are Al ions or B ions, the P +1 type semiconductor region and the P +2 type semiconductor region are implanted with very high concentrations of Al ions or B ions, and the N + type semiconductor region is implanted with very high concentrations of P ions or N ions.
7. The SiC VDMOSFET structure of claim 4 having a gate-source voltage overshoot suppression for increasing source contact of a JFET region, wherein said dielectric layer is SiO 2 。
CN202311447930.7A 2023-11-02 2023-11-02 SiC VDMOSFET structure with suppressed gate-source voltage overshoot with increased JFET region source contact Pending CN117393604A (en)

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