CN117393475B - Multi-project wafer automatic sorting method based on multi-stage sorting map - Google Patents
Multi-project wafer automatic sorting method based on multi-stage sorting map Download PDFInfo
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Abstract
The multi-project wafer automatic sorting method based on the multi-project sorting map constructs a first-stage sorting map according to the specification of the multi-project wafer, and region positioning information of each unit rectangular region in a sorting coordinate system can be determined through the mapping processing of the first-stage sorting map and chip arrangement information of the multi-project wafer; and then, constructing a two-stage sorting map of each unit rectangular area according to chip arrangement information in a single wafer partition and chip specifications of each chip, and determining physical coordinates of each chip in a sorting coordinate system according to area positioning information of each unit rectangular area and the two-stage sorting map of each unit rectangular area so as to realize automatic sorting of chips in a plurality of wafers, thereby being beneficial to improving the automation degree and sorting efficiency of multi-project wafer sorting.
Description
Technical Field
The application relates to the field of semiconductor devices, in particular to a multi-project wafer automatic sorting method based on a multi-stage sorting map.
Background
With the rapid development of the integrated circuit industry, in order to reduce production and testing costs, multi-project wafers (Multi Project Wafer, MPW) are often used in the Prototype (Prototype) design stage. The multi-project wafer is a special wafer, the common wafer only comprises one type of chips, the multi-project wafer places a plurality of integrated circuit designs using the same process on the same wafer, after manufacturing is completed, each integrated circuit design can obtain a plurality of chip samples, so that a plurality of different types of chips are integrated on the same multi-project wafer for experiments and tests in a design stage, thereby effectively improving the production test efficiency and reducing the production test cost.
When manufacturing the multi-project wafer, the same mask is utilized to expose the multi-project wafer in sequence, one rectangular area is exposed each time, the exposure of the next rectangular area is continued after the exposure of one rectangular area is completed, and the process is circulated until the whole wafer is exposed. Therefore, the structure of the multi-project wafer is shown in fig. 1, and the multi-project wafer includes a plurality of repeated wafer partitions arranged in sequence, and each wafer partition is a rectangular area exposing the multi-project wafer at a time. In fig. 1, four chips A, B, C, D are formed in each wafer partition, and fig. 1 shows that the four chips are of different types by different graphic symbols, instead of showing actual specifications of the respective chips.
When different types of chips on the multi-project wafer are sorted, the chip arrangement information is required to be dependent, and considering the universality on different wafer sorting machines, the chip arrangement information of the multi-project wafer at present usually adopts text or xlsx file format, and the logic position relationship among the different types of chips is indicated in a digital form. For example, the number 1 indicates one type of chip 1 and the number 2 indicates another type of chip 2, and the chip arrangement information records contents such as 1222, which indicates that the chips 1, 2 are arranged in sequence on a multi-project wafer. However, in practice, the planar dimensions of the different types of chips integrated on the multi-project wafer are often different, for example, in the above example, the planar length of the chip 1 may be 2 times that of the chip 2, and the chip arrangement information of the existing multi-project wafer cannot show the planar dimensions of the different types of chips, so in order to avoid sorting errors, it is generally currently used to manually locate one wafer partition, then sequentially select each chip in the wafer partition, and after the current wafer partition is selected, manually locate the next wafer partition to sequentially select, which is time-consuming and labor-consuming, and affects the sorting efficiency of the multi-project wafer.
Disclosure of Invention
The application provides a multi-project wafer automatic sorting method based on a multi-stage sorting map aiming at the problem that the sorting efficiency of the existing multi-project wafer is lower, and the technical scheme of the application is as follows:
the multi-project wafer automatic sorting method based on the multi-stage sorting map comprises the following steps:
constructing a first-level sorting map according to the specifications of the multi-project wafers, wherein the first-level sorting map is a global circular area filled by unit rectangular areas, the specifications of all the unit rectangular areas are the same as the sizes of the partitions of each wafer in the multi-project wafers, and the sizes of the global circular area are the same as the sizes of the wafers of the multi-project wafers;
carrying out mapping processing on the first-level sorting map and chip arrangement information of the multi-project wafer, determining the corresponding relation between each unit rectangular area in the first-level sorting map and the wafer partition in the multi-project wafer, and determining the position information of the area vertex of each unit rectangular area in a sorting coordinate system as the area positioning information of the unit rectangular area;
according to chip arrangement information in a single wafer partition in a multi-item wafer and chip specifications of each chip, constructing a secondary classification map of a unit rectangular area, wherein the secondary classification map indicates the relative arrangement area of each chip in the unit rectangular area in each unit rectangular area, and multiplexing the constructed secondary classification map to obtain secondary classification maps corresponding to other unit rectangular areas;
And determining physical coordinates of each chip in the multi-project wafer in a sorting coordinate system according to the area positioning information of each unit rectangular area in the primary sorting map and the secondary sorting map of each unit rectangular area, and picking and sorting the chips in the multi-project wafer according to the physical coordinates of each chip in the sorting coordinate system.
The further technical scheme is that the construction of the two-level classification map for obtaining a unit rectangular area comprises the following steps:
dividing each unit rectangular area into cells according to a row-column format, wherein the length of each unit rectangular area is M, the width of each unit rectangular area is N, the length of each unit cell is M, the width of each unit cell is N, each unit rectangular area comprises k1 columns of unit cells along the length direction, each unit rectangular area comprises k2 columns of unit cells along the width direction, M=m×k1, N=m×k2, and k1 and k2 are integer parameters;
according to the chip arrangement information in the single wafer partition and the chip specification of each chip, determining all cells occupied by each chip in a unit rectangular area, storing row and column information of the cells occupied by each chip in the unit rectangular area, and constructing and obtaining a two-stage classification map of the unit rectangular area.
The further technical scheme is that determining all cells occupied by each chip in a rectangular unit area comprises:
determining the relative arrangement positions of the chips in the unit rectangular area according to the chip arrangement information in the single wafer partition, determining the number of the unit cells respectively occupied along the row-column direction at the corresponding relative arrangement positions according to the chip specification of each chip, and determining to obtain all the unit cells occupied by each chip in the unit rectangular area.
The further technical scheme is that the determining of the physical coordinates of each chip in the multi-item wafer in the sorting coordinate system comprises the following steps:
determining a unit cell where the gravity center position of the chip is located as a gravity center unit cell of the chip according to the unit cell occupied by each chip in the unit rectangular area;
according to the row and column information of the center of gravity unit cell of each chip in the unit rectangular area, determining the coordinates of the center of gravity unit cell of the chip in the local coordinate system of the unit rectangular area;
and according to the coordinates of the center of gravity unit cell of each chip in the local coordinate system of the unit rectangular area, combining the area positioning information of the unit rectangular area, and converting the coordinate system of the local coordinate system and the coordinate system of the sorting coordinate system to obtain the coordinates of the center of gravity unit cell of the chip in the sorting coordinate system as the physical coordinates of the corresponding chip in the sorting coordinate system.
The automatic multi-project wafer sorting method based on the multi-stage sorting map further comprises the following steps:
detecting whether a sorting map corresponding to the product specification of the multi-project wafer to be sorted exists or not, wherein the sorting map comprises a first-stage sorting map and a second-stage sorting map of each unit rectangular area, and the multi-project wafer with the same product specification is completely the same;
when a sorting map corresponding to the product specification of the multi-project wafer to be sorted does not exist, constructing a sorting map of the multi-project wafer to be sorted, sorting the multi-project wafer to be sorted based on the constructed sorting map, and storing the constructed sorting map corresponding to the product specification of the multi-project wafer to be sorted;
and when the sorting map corresponding to the product specification of the multi-project wafer to be sorted exists, directly calling the sorting map corresponding to the product specification of the multi-project wafer to be sorted, and sorting the multi-project wafer to be sorted.
The further technical scheme is that the picking and sorting of the chips in the wafers with multiple items comprises the following steps:
for small-size chips with the chip specifications not reaching the size threshold, controlling a pickup mechanism to sequentially move to physical coordinates of each small-size chip in the same unit rectangular region in a sorting coordinate system, and sequentially picking and sorting each small-size chip in a wafer partition corresponding to the unit rectangular region; after picking and sorting are completed on all small-size chips in the wafer partition corresponding to one unit rectangular area, picking and sorting are sequentially carried out on the small-size chips in the wafer partition corresponding to the next unit rectangular area;
After picking up and sorting small-size chips in all wafer partitions in the multiple project wafers, for large-size chips with the chip specifications reaching a size threshold, controlling a picking mechanism to sequentially move to physical coordinates of each large-size chip in the multiple project wafers in a sorting coordinate system, and sequentially picking up and sorting the large-size chips in each wafer partition in the multiple project wafers.
The further technical scheme is that the picking and sorting of the small-size chips in the wafer partition corresponding to each unit rectangular area further comprises:
controlling the pick-up mechanism to move to the area positioning information of the unit rectangular area and repositioning the area vertex of the unit rectangular area to obtain corrected area positioning information of the unit rectangular area; and determining the physical coordinates of each small-size chip in the unit rectangular area according to the corrected area positioning information of the unit rectangular area and the secondary classification map of the unit rectangular area, and controlling the pickup mechanism to sequentially move to the physical coordinates of each small-size chip in the unit rectangular area for pickup and separation.
The further technical scheme is that the control of the picking mechanism to move to the physical coordinates of each chip in the sorting coordinate system to pick and sort the chips comprises the following steps:
The picking mechanism is controlled to move to a physical coordinate position of the chip in a sorting coordinate system, the chip to be picked is jacked up by a thimble unit with the thimble type matched with the chip specification of the chip to be picked, and the chip to be picked is sucked by a suction nozzle with the aperture matched with the chip specification of the chip to be picked, so that the picking and sorting of the chip to be picked are completed; the quantity and arrangement form of the ejector pins arranged at the end parts of the ejector pin units of different ejector pin types are at least different.
The further technical scheme is that the picking and sorting of the chips further comprises:
when the thimble type of the current thimble unit is not matched with the chip specification of the chip to be picked up, controlling the thimble lifting platform to drive the current thimble unit to descend, wherein the current thimble unit is clamped into clamping grooves on the side wall of a thimble library base through buckles on the side wall in the descending process, a plurality of clamping grooves are formed in the circumference of the thimble library base, and thimble units of different thimble types are clamped at the positions of each clamping groove; the thimble lifting platform continues to descend to the lower limit preset position and is separated from the current thimble unit, the thimble library base is controlled to circumferentially rotate until a thimble type target thimble unit matched with the chip specification of the chip to be picked rotates to the position above the thimble lifting platform, the thimble lifting platform is controlled to ascend and contact with the target thimble unit to drive the target thimble unit to ascend, the buckle of the target thimble unit is separated from the clamping groove on the side wall of the thimble library base in the ascending process, the thimble lifting platform continues to ascend to the upper limit preset position, and the switching from the current thimble unit to the target thimble unit is completed.
The automatic multi-project wafer sorting method based on the multi-stage sorting map further comprises the following steps:
in the process of picking and sorting chips in a plurality of item wafers, displaying a real-time picking state based on a first-stage sorting map and a second-stage sorting map, wherein the first-stage sorting map displays a unit rectangular area corresponding to a wafer partition in which all chips are sorted as a first state, and displays a unit rectangular area corresponding to a wafer partition in which the chips are not sorted as a second state; and a second-level sorting map which comprises a unit rectangular area corresponding to the wafer partition where the chip which is currently being picked up is displayed, wherein the opposite arrangement area of the chip which is already picked up is displayed as a first color in the second-level sorting map which is currently displayed, and the opposite arrangement areas of the other chips which are not yet picked up are respectively displayed as different other colors according to different chip types.
The beneficial technical effects of this application are:
the method constructs a first-stage sorting map of the multi-stage wafer to indicate information of each unit rectangular area, and constructs a second-stage sorting map of each unit rectangular area to indicate information of each chip in a wafer partition corresponding to the unit rectangular area, so that physical coordinates of each chip can be determined by combining the first-stage sorting map and the second-stage sorting map to realize automatic sorting of the chips in the multi-stage wafer, and the method is beneficial to improving the automation degree and sorting efficiency of multi-stage wafer sorting.
Drawings
FIG. 1 is a schematic diagram of a multi-project wafer.
Fig. 2 is a method flow diagram of a multi-project automated wafer sorting method based on a multi-stage sort map in accordance with one embodiment of the present application.
Fig. 3 is a schematic diagram of the primary sort map and the secondary sort map constructed in the present application.
Fig. 4 is a schematic diagram of a construction flow of the first-level sort map constructed in the present application.
Fig. 5 is a method flow diagram of a multi-project automated wafer sort method based on a multi-stage sort map in another embodiment of the present application.
Fig. 6 is a schematic view of several common thimble types.
FIG. 7 is a schematic diagram of a switching flow from current ejector unit 710 to target ejector unit 760.
FIG. 8 is an enlarged view of a portion of the snap fit engagement of the snap 720 on the side wall of the current ejector unit 710 with the snap groove 740 on the side wall of the ejector base 730.
Detailed Description
The following describes the embodiments of the present application further with reference to the accompanying drawings.
The application discloses a multi-project wafer automatic sorting method based on a multi-stage sorting map, please refer to a flowchart shown in fig. 2, the multi-project wafer automatic sorting method based on the multi-stage sorting map comprises:
and step 1, constructing a first-level sorting map according to the specifications of the multi-project wafers.
The specification of the multi-project wafer includes the wafer size of the multi-project wafer and the size of each wafer partition in the multi-project wafer. Wafer sizes for multi-project wafers are common such as 6inch, 8 inch, 10inch, etc. According to the current general structure, each wafer partition is of a rectangular structure, and then the size of each wafer partition comprises a length and a width, the length of each wafer partition is defined as M, the width of each wafer partition is defined as N, the units of M and N are all mm, and the specific values of M and N are determined according to the specifications of actual multi-project wafers. For example, in one example, each wafer partition has a length m=21 mm and a width n=16 mm.
The constructed first-level sort map is a global circular region filled internally by a unit rectangular region, please refer to the schematic diagram shown in fig. 3. The specifications of the unit rectangular areas are the same as those of each wafer partition in the multiple wafers, namely the length of each unit rectangular area is M, and the width of each unit rectangular area is N. The global circular area has the same size as the wafer of the multi-project wafer.
One method of constructing a first class sort map includes, referring to the schematic diagram of fig. 4:
(1) The effective target surface radius corresponding to the wafer size is determined, for example, the effective target surface radius is 101.6mm when the wafer size is 6inch, which is a prior art, and will not be described herein.
(2) Generating a unit rectangular area according to the size of the wafer partition, copying and filling the unit rectangular area along the length-width direction by taking the unit rectangular area as a minimum repeated unit to form a background rectangular area with a plurality of unit rectangular areas distributed according to a row-column structure, cutting out a global circular area with an effective target surface radius from the background rectangular area, reserving the unit rectangular area in the global circular area, removing the unit rectangular area outside the global circular area and at the boundary, and constructing to obtain the first-level sorting map shown in figure 3.
And 2, carrying out mapping processing on the first-level sorting map and chip arrangement information of the multi-project wafer, determining the corresponding relation between each unit rectangular area in the first-level sorting map and the wafer partition in the multi-project wafer, and determining the position information of the area vertex of each unit rectangular area in a sorting coordinate system as the area positioning information of the unit rectangular area.
As described in the background section, the chip arrangement information of the multi-project wafer may describe the logic positional relationship between the chips of different types, and for the multi-project wafer, the chips of different types are generally compactly arranged in a wafer partition according to a relatively regular form, so that the integration level can be improved, and therefore, the chips in the wafer partition are basically arranged in a row and column form. Because each wafer partition is identical, the chip arrangement information in each wafer partition is identical, so that the chip arrangement information in each wafer partition can be determined, then the unit rectangular area in the first-level sorting map can be corresponding to the wafer partition in the multi-project wafer by using a map drawing mode, and therefore the position information of the area vertex of one unit rectangular area in the sorting coordinate system is determined to obtain the area positioning information of one unit rectangular area, and the size of the unit rectangular area is known, so that the area positioning information of other unit rectangular areas can be directly expanded and obtained. The area vertex of the unit rectangular area can be at least one of four vertices of the unit rectangular area, and the upper left corner vertex of the unit rectangular area is generally selected in actual operation.
And 3, constructing a two-stage classification map of the unit rectangular area according to chip arrangement information in a single wafer partition in the multi-project wafer and the chip specification of each chip. The constructed two-level distribution map of each unit rectangular area indicates the arrangement area of each chip in the unit rectangular area.
Considering that all wafer partitions in the multi-project wafer are completely identical, including identical size and identical internal chip arrangement, after the secondary sorting map of one unit rectangular area is constructed, the secondary sorting map of other unit rectangular areas is not required to be repeatedly constructed, and the constructed secondary sorting map is directly multiplexed to obtain the secondary sorting map corresponding to other unit rectangular areas.
In one embodiment, first, each unit rectangular area is divided into units according to a row-column format, wherein each unit is m in length, n in width, and m and n are all mm. Each unit rectangular area is divided into k1 columns of unit cells along the length direction, each unit rectangular area comprises k2 columns of unit cells along the width direction, and m=m×k1, n=m×k2, and k1 and k2 are integer parameters.
The values of m and n can be customized, and m and n can be equal or unequal. Common chips are typically larger than 1mm by 1mm, such as 1.2mm by 1.2mm, and some special smaller size chips, such as 0.8mm by 0.8mm, or currently the smallest chip has 0.25mm by 0.25mm. Therefore, the value of m and n can be generally 0.25mm or 0.4mm, or the like, or the smaller the value of m and n is 0.1mm or 0.05mm, the higher the processing precision is, but the larger the operation amount and the high operation complexity are caused, and the user can practically and custom select according to the needs. A schematic diagram of a cell divided into partial regions in a rectangular region of a cell is shown in fig. 3.
After the unit rectangular area is subjected to unit cell division, all the unit cells occupied by each chip in the unit rectangular area can be determined according to the chip arrangement information in the single wafer partition and the chip specification of each chip, the row and column information of the unit cells occupied by each chip in the unit rectangular area is stored, and a two-stage distribution map of the unit rectangular area is constructed. When in storage, the chip identification and the row and column information of the cells occupied by the chip are stored correspondingly in a key value pair mode according to a dictionary format.
In one embodiment, the method for determining the unit cell occupied by each chip in a unit rectangular area comprises the following steps: the arrangement position of each chip in the unit rectangular area is determined according to the chip arrangement information in the single wafer partition, and the number of the unit cells respectively occupied along the row-column direction at the corresponding arrangement position is determined according to the chip specification of each chip, so that all the unit cells occupied by each chip in the unit rectangular area are determined. According to the difference of the values of m and n, the ratio of the size of the chip in the length-width direction to the size of the cells may or may not be an integer, and when the ratio is not an integer, the number of occupied cells is determined by a way of rounding upwards.
The chip specifications of the different types of chips are the same or different. The chip specification includes the planar shape and the size of the chip, and the planar shape of the chip on the multi-project wafer in the present application is a common rectangle or a common special shape, and the current common special shape is an L-shape, as in the example of fig. 3, the chip type 3 is an L-shaped chip. For a chip with a rectangular planar shape, the number of columns of occupied cells can be determined according to the length of the chip, and the number of rows of occupied cells can be determined according to the width of the chip. For the chip with the L-shaped plane shape, the number of columns of the cells occupied by the vertical side can be determined according to the length of the vertical side of the chip, the number of rows of the cells occupied by the vertical side can be determined according to the width of the vertical side of the chip, the number of columns of the cells occupied by the horizontal side can be determined according to the length of the horizontal side of the chip, and the number of rows of the cells occupied by the horizontal side can be determined according to the width of the horizontal side of the chip, so that all the cells occupied by the chip with the L-shaped plane shape can be determined.
Referring to fig. 3, the chip arrangement information in each wafer partition indicates that the first horizontal row in the wafer partition is 11122, that is, 3 chips of chip type 1 and 2 chips of chip type 2 are sequentially arranged. The chip arrangement information also indicates that the second row in the wafer partition is 344, that is, one chip of chip type 3 and 2 chips of chip type 4 are sequentially arranged. The chip arrangement information also indicates that the third row in the wafer partition is 344, that is, one chip of chip type 3 and 2 chips of chip type 4 are sequentially arranged. Fig. 3 also shows the ranges of the unit cells occupied by the specifications of the four different types of chips, namely, chip type 1 to chip type 4, respectively, and fig. 3 takes the example that the specifications of the four types of chips are different. And determining row and column information of the cells occupied by each chip by combining the arrangement position of each chip in the rectangular unit area indicated by the chip arrangement information. For example, in fig. 3, a first chip X in the rectangular area of the unit from the top left corner belongs to chip type 1, and according to the chip specification of chip type 1, it can be determined that the chip X occupies 4 rows and 5 columns of cells, that is, it can be determined that the row information of all the cells occupied by the chip X in the rectangular area of the unit includes all 20 row information of the first row, the first column, the fourth row and the fifth column, where for simplicity of illustration, the chip identifier of the chip X is actually stored corresponding to the 20 row information. The row and column information of the cells occupied by the other chips can be determined by the same method, so that a schematic diagram of the cells occupied by the chips displayed by the obtained two-level hierarchical map is determined as shown in fig. 3. Wherein, the blank in the secondary sorting map represents the Dummy chip.
And 4, determining physical coordinates of each chip in the multi-project wafer in a sorting coordinate system according to the area positioning information of each unit rectangular area in the primary sorting map and the secondary sorting map of the unit rectangular areas, and picking and sorting the chips in the multi-project wafer according to the physical coordinates of each chip in the sorting coordinate system.
The arrangement area of each chip in the unit rectangular area is determined in the above step, and the physical coordinates of each chip in the sorting coordinate system can be obtained through a coordinate conversion mode by combining the area positioning information of the unit rectangular area in the sorting coordinate system. Based on the thought, on the basis of representing the arrangement area of each chip in the unit rectangular area by using the row and column information of the cells, firstly, determining the unit cell where the center of gravity of the chip is located according to the unit cell occupied by each chip in the unit rectangular area as the center of gravity unit cell of the chip, as described above, the chip in the application may be a regular chip or an irregular chip, the geometric center of the regular chip is often the center of gravity of the chip, but the geometric center of the irregular chip such as an L-shaped chip is not the center of gravity of the chip, and in consideration of the subsequent picking, the picking has better picking stability at the center of gravity of the chip, so that the unit cell where the center of gravity of the chip is located is determined in this step, and the unit cell where the center of gravity of the chip is located can be determined according to a mathematical method based on the distribution condition of the number of the unit cells.
And determining the coordinates of the barycenter unit cells of the chips in the local coordinate system of the unit rectangular area where the barycenter unit cells of the chips are currently located according to the row and column information of the barycenter unit cells of each chip in the unit rectangular area. And then according to the coordinates of the center of gravity unit lattice of each chip in the local coordinate system of the unit rectangular area, combining the area positioning information of the unit rectangular area, and converting the coordinate system of the local coordinate system and the coordinate system of the sorting coordinate system to obtain the coordinates of the center of gravity unit lattice of the chip in the sorting coordinate system as the physical coordinates of the corresponding chip in the sorting coordinate system. Transformation solution of the coordinate system is also a common mathematical method, and will not be described here.
In another embodiment, in the process of picking and sorting chips in a plurality of wafers, a real-time picking state is displayed based on a first-stage sorting map and a second-stage sorting map, wherein the first-stage sorting map displays a unit rectangular area corresponding to a wafer partition which has already been sorted into a first state and displays a unit rectangular area corresponding to a wafer partition which has not yet been sorted into a second state. In addition, a second-level separation map of a unit rectangular area corresponding to the wafer partition where the chip which is currently being picked up is displayed, the arrangement area of the chip which is already picked up is displayed as a first color in the second-level separation map which is currently displayed, and the arrangement areas of other chips which are not yet picked up are respectively displayed as different other colors according to different chip types, so that the picking up and sorting process can be clearly and intuitively displayed.
Optionally, in practical application, multiple sorting tasks are often performed on the same wafer with multiple items, and the built sorting map can be directly stored and called, and the sorting map comprises a first-level sorting map and a second-level sorting map of each unit rectangular area. When a multi-project wafer to be sorted is required to be sorted, referring to the flowchart of fig. 5, it is first detected whether a sorting map corresponding to the product specification of the multi-project wafer to be sorted exists, and the multi-project wafers with the same product specification are identical. When a sorting map corresponding to the product specification of the multi-project wafer to be sorted does not exist, the sorting map of the multi-project wafer to be sorted is built according to the method provided by the application, the multi-project wafer to be sorted is sorted based on the built sorting map, and the built sorting map is stored corresponding to the product specification of the multi-project wafer to be sorted. And when the sorting map corresponding to the product specification of the multi-project wafer to be sorted exists, directly calling the sorting map corresponding to the product specification of the multi-project wafer to be sorted, and sorting the multi-project wafer to be sorted. Therefore, the sorting map is only required to be built once aiming at one product specification, and the built sorting map can be reused.
After the physical coordinates of the chips are determined by constructing the sorting map, the chips can be picked and sorted based on the sorting map according to the existing picking method. In view of the diversity of chip specifications in multi-project wafers, in another embodiment, a pick-and-sort method is also optimized for multi-project wafers, comprising:
the chips in the wafer with multiple items are divided into two types according to the chip specification by adopting different picking and sorting methods:
(1) For small-size chips with the chip specifications not reaching the size threshold, the pick-up mechanism is controlled to sequentially move to the physical coordinates of each small-size chip in the same unit rectangular area in the sorting coordinate system, and each small-size chip in the wafer partition corresponding to the unit rectangular area is sequentially picked up and sorted. And after all small-size chips in the wafer partition corresponding to one unit rectangular area are picked and sorted, picking and sorting are sequentially carried out on the small-size chips in the wafer partition corresponding to the next unit rectangular area. I.e. small-sized chips are picked up in sequential divisions according to wafer division.
(2) After all small-size chips in all wafer partitions are picked up, for large-size chips with the chip specification reaching a size threshold, as the influence of blue film deformation caused in the chip picking process on the positions of the large-size chips is not great, a picking mechanism is controlled to sequentially move to physical coordinates of each large-size chip in a sorting coordinate system in a multi-project wafer, and picking and sorting are sequentially carried out on the large-size chips in each wafer partition in the multi-project wafer, namely, global unified picking is carried out on the large-size chips on the whole multi-project wafer.
The size threshold may be set by user-definition, for example, a large-size chip is generally configured with a maximum size exceeding 0.8mm or 1mm, or a small-size chip is otherwise configured, and in the current application, a large-size chip is generally configured with an L-shaped chip, and other conventional rectangular chips are mostly small-size chips.
Because the influence of the blue film deformation caused in the chip picking process on the position of the small-size chip is larger, in order to pick up the accuracy, the influence of the blue film deformation is reduced by adopting a partition picking mode, and the picking accuracy of the small-size chip is improved. In addition, in another embodiment, when the chips in each wafer partition are picked up, the pick-up mechanism is controlled to move to the area positioning information of the unit rectangular area and reposition the area vertex of the unit rectangular area to obtain corrected area positioning information of the unit rectangular area, that is, the corrected area positioning information is sequentially corrected to correct the influence caused by the blue film deformation. And then determining the physical coordinates of each small-size chip in the unit rectangular area according to the corrected area positioning information of the unit rectangular area and the second-level classification map of the unit rectangular area, and then controlling the pickup mechanism to sequentially move to the physical coordinates of each small-size chip in the unit rectangular area for pickup and sorting, so that the pickup accuracy of the small-size chips can be further improved.
In addition, whether the chip is a large-size chip or a small-size chip, because of the variability of the chip specification, if the same pick-up mechanism is adopted for picking up, the pick-up reliability can be affected, for example, when the chip size is large, if the aperture of a suction nozzle is too small, the suction nozzle is easy to absorb and unstable, and for an L-shaped chip, for example, if a single ejector pin is adopted for ejecting the L-shaped chip, the chip is easy to incline. The method for picking and sorting any chip comprises the following steps:
and controlling the pick-up mechanism to move to a physical coordinate position of the chip in the sorting coordinate system, then jacking the chip by using a thimble unit with a thimble type matched with the chip specification of the chip to be picked up, and sucking the chip by using a suction nozzle with a suction nozzle aperture matched with the chip specification of the chip to be picked up, so as to finish the pick-up and sorting of the chip. At least one of the number and arrangement form of the ejector pins arranged at the end of the ejector pin units of different ejector pin types is different, for example, please refer to (a), (b) and (c) in fig. 6, which respectively show schematic diagrams of three common ejector pin types, the outline represents the ejector pin units, the specifications of the three ejector pin units are the same, and the black dots represent the positions of the ejector pins arranged at the end of the ejector pin units. The thimble types and the suction nozzle apertures matched with different chip specifications are preset in a customized mode.
In order to realize the functions, when the thimble type of the currently used thimble unit is matched with the chip specification of the chip to be picked up, the current thimble unit is kept unchanged; when the thimble type of the currently used thimble unit is not matched with the chip specification of the chip to be picked up, the control is switched to the thimble unit matched with the chip specification of the chip to be picked up. Likewise, when the aperture of the currently used suction nozzle is matched with the chip specification of the chip to be picked up, the current suction nozzle is kept unchanged; when the aperture of the currently used suction nozzle is not matched with the chip specification of the chip to be picked up, the control is switched to the suction nozzle matched with the chip specification of the chip to be picked up.
In another embodiment, a thimble unit switching mechanism for switching thimble units of different thimble types is further provided, please refer to the switching diagrams of the thimble unit switching mechanism shown in fig. 7 and fig. 8, when the thimble type of the current thimble unit 710 is not matched with the chip specification of the chip to be picked up, the thimble lifting platform is controlled to drive the current thimble unit 710 to be used currently to descend, and fig. 7 does not show the thimble lifting platform, and it can be understood by those skilled in the art that the thimble lifting platform is a platform located below the current thimble unit 710. The current thimble unit 710 is clamped into the clamping groove 740 of the side wall of the thimble library base 730 through the clamping buckle 720 of the side wall in the descending process.
The thimble library base 730 is circumferentially provided with a plurality of clamping grooves 740, and thimble units of different thimble types are clamped at each clamping groove 740, and the thimble types except for the end parts of the thimble units are different in other specifications. Referring to the partial enlarged view of fig. 8, a matching schematic diagram of the buckle 720 on the side wall of the current thimble unit 710 and the card slot 740 on the side wall of the thimble library base 730 is shown, the buckle 720 protrudes downward, and the card slot 740 is slotted upward, so that the buckle 720 can be inserted into the card slot 740 to realize the matching and clamping when the current thimble unit 710 descends, as shown in fig. 8, the state diagram of the buckle 720 of the current thimble unit 710 not being inserted into the card slot 740 is shown, and the state diagram of the buckle 720 being inserted into the card slot 740 along with the descending.
The thimble lifting platform continues to descend to the lower limit preset position and is separated from the current thimble unit 710, and at this time, the current thimble unit 710 is fixedly clamped in the clamping groove 740 of the thimble storage base 730. Then, the driving motor 750 is used to control the ejector base 730 to rotate circumferentially until the ejector pin type target ejector pin unit 760 matched with the chip specification of the chip to be picked rotates to the upper part of the ejector pin lifting platform, the ejector pin lifting platform is controlled to lift and contact with the target ejector pin unit 760 to drive the target ejector pin unit 760 to lift, and the buckle of the target ejector pin unit 760 is disengaged from the clamping groove on the side wall of the ejector base 730 in the lifting process, so that as can be understood by those skilled in the art, contrary to the state shown in fig. 8, the application is not separately illustrated. The ejector pin lifting platform continues to rise to the upper limit preset position, and the switching from the current ejector pin unit 710 to the target ejector pin unit 760 is completed.
What has been described above is only a preferred embodiment of the present application, which is not limited to the above examples. It is to be understood that other modifications and variations which may be directly derived or contemplated by those skilled in the art without departing from the spirit and concepts of the present application are to be considered as being included within the scope of the present application.
Claims (10)
1. The multi-project wafer automatic sorting method based on the multi-stage sorting map is characterized by comprising the following steps of:
constructing a first-level sorting map according to the specifications of the multi-project wafers, wherein the first-level sorting map is a global circular area filled with unit rectangular areas, the specifications of all the unit rectangular areas are the same and the sizes of the wafer partitions in the multi-project wafers are the same, and the sizes of the global circular areas are the same as the sizes of the wafers of the multi-project wafers;
carrying out mapping processing on the primary sorting map and chip arrangement information of the multi-project wafer, determining the corresponding relation between each unit rectangular area in the primary sorting map and the wafer partition in the multi-project wafer, and determining the position information of the area vertex of each unit rectangular area in a sorting coordinate system as the area positioning information of the unit rectangular area;
Constructing a secondary classification map of a unit rectangular area according to chip arrangement information in a single wafer partition in the multi-project wafer and chip specifications of each chip, wherein the secondary classification map indicates arrangement areas of each chip in the unit rectangular area in each unit rectangular area, and multiplexing the constructed secondary classification map to obtain secondary classification maps corresponding to other unit rectangular areas;
and determining physical coordinates of each chip in the multi-item wafer in a sorting coordinate system according to the area positioning information of each unit rectangular area in the primary sorting map and the secondary sorting map of each unit rectangular area, and picking and sorting the chips in the multi-item wafer according to the physical coordinates of each chip in the sorting coordinate system.
2. The automated multi-project wafer sorting method based on the multi-stage sorting map according to claim 1, wherein the constructing the two-stage sorting map to obtain one unit rectangular area comprises:
dividing each unit rectangular area into cells according to a row-column format, wherein the length of each unit rectangular area is M, the width of each unit rectangular area is N, the length of each unit cell is M, the width of each unit cell is N, each unit rectangular area comprises k1 columns of unit cells along the length direction, each unit rectangular area comprises k2 columns of unit cells along the width direction, M=m×k1, N=m×k2, and k1 and k2 are integer parameters;
According to the chip arrangement information in the single wafer partition and the chip specification of each chip, determining all cells occupied by each chip in a unit rectangular area, storing row and column information of the cells occupied by each chip in the unit rectangular area, and constructing and obtaining a two-stage classification map of the unit rectangular area.
3. The automated multi-project wafer sorting method based on the multi-level sort map according to claim 2, wherein the determining all cells occupied by each chip in one unit rectangular area comprises:
and determining the arrangement positions of the chips in the unit rectangular area according to the chip arrangement information in the single wafer partition, determining the number of the unit cells respectively occupied along the row-column direction at the corresponding arrangement positions according to the chip specification of each chip, and determining to obtain all the unit cells occupied by each chip in the unit rectangular area.
4. The automated multi-project wafer sorting method based on the multi-stage sorting map according to claim 3, wherein the determining physical coordinates of each chip in the multi-project wafer in the sorting coordinate system comprises:
determining a unit cell where the center of gravity of each chip is located as a center of gravity unit cell of the chip according to the unit cell occupied by each chip in the unit rectangular area;
Determining coordinates of the barycenter unit cells of each chip in a local coordinate system of the unit rectangular area according to row and column information of the barycenter unit cells of each chip in the unit rectangular area;
and according to the coordinates of the center of gravity unit grid of each chip in the local coordinate system of the unit rectangular area, combining the area positioning information of the unit rectangular area, and converting the coordinate system of the local coordinate system and the coordinate system of the sorting coordinate system to obtain the coordinates of the center of gravity unit grid of the chip in the sorting coordinate system as the physical coordinates of the corresponding chip in the sorting coordinate system.
5. The multi-project wafer automatic sorting method based on the multi-stage sorting map according to claim 1, further comprising:
detecting whether a sorting map corresponding to the product specification of a plurality of wafers to be sorted exists or not, wherein the sorting map comprises a first-stage sorting map and a second-stage sorting map of each unit rectangular area, and the plurality of wafers with the same product specification are completely the same;
when a sorting map corresponding to the product specification of the multi-project wafer to be sorted does not exist, constructing a sorting map of the multi-project wafer to be sorted, sorting the multi-project wafer to be sorted based on the constructed sorting map, and storing the constructed sorting map corresponding to the product specification of the multi-project wafer to be sorted;
And when a sorting map corresponding to the product specification of the multi-project wafer to be sorted exists, directly calling the sorting map corresponding to the product specification of the multi-project wafer to be sorted, and sorting the multi-project wafer to be sorted.
6. The automated multi-project wafer sorting method based on the multi-stage sorting map according to claim 1, wherein the picking and sorting the chips in the multi-project wafer comprises:
for small-size chips with the chip specifications not reaching the size threshold, controlling a pickup mechanism to sequentially move to physical coordinates of each small-size chip in the same unit rectangular region in a sorting coordinate system, and sequentially picking and sorting each small-size chip in a wafer partition corresponding to the unit rectangular region; after picking and sorting are completed on all small-size chips in the wafer partition corresponding to one unit rectangular area, picking and sorting are sequentially carried out on the small-size chips in the wafer partition corresponding to the next unit rectangular area;
after picking and sorting small-size chips in all wafer partitions in the multi-project wafer, controlling a picking mechanism to sequentially move to physical coordinates of each large-size chip in the multi-project wafer in a sorting coordinate system for the large-size chips with the chip specification reaching the size threshold value, and sequentially picking and sorting the large-size chips in each wafer partition in the multi-project wafer.
7. The automated multi-project wafer sorting method based on the multi-stage sorting map according to claim 6, wherein picking and sorting small-sized chips in the wafer partitions corresponding to each unit rectangular area further comprises:
controlling a pickup mechanism to move to the area positioning information of the unit rectangular area and repositioning the area vertex of the unit rectangular area to obtain corrected area positioning information of the unit rectangular area; and determining physical coordinates of each small-size chip in the unit rectangular region according to the corrected region positioning information of the unit rectangular region and the second-level classification map of the unit rectangular region, and controlling a pickup mechanism to sequentially move to the physical coordinates of each small-size chip in the unit rectangular region for pickup and classification.
8. The automated multi-project wafer sorting method based on the multi-stage sorting map of claim 6, wherein controlling the movement of the pick mechanism to pick and sort the chips at physical coordinates in the sorting coordinate system for each chip comprises:
the picking mechanism is controlled to move to a physical coordinate position of the chip in a sorting coordinate system, the chip to be picked is jacked up by a thimble unit with the thimble type matched with the chip specification of the chip to be picked, and the chip to be picked is sucked by a suction nozzle with the aperture matched with the chip specification of the chip to be picked, so that the picking and sorting of the chip to be picked are completed; the quantity and arrangement form of the ejector pins arranged at the end parts of the ejector pin units of different ejector pin types are at least different.
9. The automated multi-project wafer sorting method based on the multi-stage sorting map according to claim 8, wherein the picking and sorting of the chips further comprises:
when the thimble type of the current thimble unit is not matched with the chip specification of the chip to be picked up, controlling the thimble lifting platform to drive the current thimble unit to descend, wherein the current thimble unit is clamped into clamping grooves on the side wall of a thimble library base through buckles on the side wall in the descending process, and a plurality of clamping grooves are formed in the circumference of the thimble library base and each clamping groove is clamped with a thimble unit with a different thimble type; the thimble lifting platform continues to descend to the lower limit preset position and is separated from the current thimble unit; the thimble library base is controlled to circumferentially rotate until a thimble type target thimble unit matched with the chip specification of a chip to be picked rotates to the position above the thimble lifting platform, the thimble lifting platform is controlled to ascend and contact with the target thimble unit to drive the target thimble unit to ascend, a buckle of the target thimble unit is separated from a clamping groove on the side wall of the thimble library base in the ascending process, and the thimble lifting platform continues to ascend to an upper limit preset position to finish switching from the current thimble unit to the target thimble unit.
10. The multi-project wafer automatic sorting method based on the multi-stage sorting map according to claim 1, further comprising:
in the process of picking and sorting chips in the multi-project wafer, displaying a real-time picking state based on a first-stage sorting map and a second-stage sorting map, wherein the first-stage sorting map displays a unit rectangular area corresponding to a wafer partition in which all chips are sorted as a first state, and displays a unit rectangular area corresponding to a wafer partition in which the chips are not sorted as a second state; the method comprises the steps of displaying a secondary sorting map of a unit rectangular area corresponding to a wafer partition where a chip which is currently being picked up is located, displaying an arrangement area of the chip which is already picked up in the secondary sorting map which is currently displayed as a first color, and displaying arrangement areas of other chips which are not yet picked up as different other colors according to different chip types.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114999933A (en) * | 2022-06-30 | 2022-09-02 | 深圳市丰泰工业科技有限公司 | Matrix die bonding process |
| CN116013816A (en) * | 2023-01-18 | 2023-04-25 | 江西兆驰半导体有限公司 | Sorting method and system for LED chips and computer equipment |
| CN116921260A (en) * | 2023-06-13 | 2023-10-24 | 苏州精濑光电有限公司 | Light-emitting chip sorting method and device |
| CN117038554A (en) * | 2023-10-10 | 2023-11-10 | 迈为技术(珠海)有限公司 | Chip positioning method and chip transferring method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114999933A (en) * | 2022-06-30 | 2022-09-02 | 深圳市丰泰工业科技有限公司 | Matrix die bonding process |
| CN116013816A (en) * | 2023-01-18 | 2023-04-25 | 江西兆驰半导体有限公司 | Sorting method and system for LED chips and computer equipment |
| CN116921260A (en) * | 2023-06-13 | 2023-10-24 | 苏州精濑光电有限公司 | Light-emitting chip sorting method and device |
| CN117038554A (en) * | 2023-10-10 | 2023-11-10 | 迈为技术(珠海)有限公司 | Chip positioning method and chip transferring method |
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