CN117374176A - High-voltage LED chip manufacturing method and high-voltage LED chip - Google Patents
High-voltage LED chip manufacturing method and high-voltage LED chip Download PDFInfo
- Publication number
- CN117374176A CN117374176A CN202311404685.1A CN202311404685A CN117374176A CN 117374176 A CN117374176 A CN 117374176A CN 202311404685 A CN202311404685 A CN 202311404685A CN 117374176 A CN117374176 A CN 117374176A
- Authority
- CN
- China
- Prior art keywords
- layer
- led chip
- voltage led
- etching
- type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 238000002955 isolation Methods 0.000 claims abstract description 62
- 238000005530 etching Methods 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 30
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 239000013078 crystal Substances 0.000 claims abstract description 10
- 239000010410 layer Substances 0.000 claims description 221
- 229910052751 metal Inorganic materials 0.000 claims description 47
- 239000002184 metal Substances 0.000 claims description 47
- 239000011241 protective layer Substances 0.000 claims description 27
- 238000000137 annealing Methods 0.000 claims description 6
- 238000001039 wet etching Methods 0.000 claims description 6
- 238000000034 method Methods 0.000 abstract description 29
- 241001391944 Commicarpus scandens Species 0.000 abstract description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 25
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 230000008569 process Effects 0.000 description 11
- 238000002161 passivation Methods 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 7
- 238000000576 coating method Methods 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- 238000001704 evaporation Methods 0.000 description 5
- 238000009413 insulation Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000008020 evaporation Effects 0.000 description 4
- 239000007788 liquid Substances 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 3
- 230000000052 comparative effect Effects 0.000 description 3
- 238000000313 electron-beam-induced deposition Methods 0.000 description 3
- 239000007769 metal material Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000000243 solution Substances 0.000 description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- 238000011109 contamination Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000003929 acidic solution Substances 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000009194 climbing Effects 0.000 description 1
- 239000008367 deionised water Substances 0.000 description 1
- 229910021641 deionized water Inorganic materials 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000000428 dust Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000002834 transmittance Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission
- H01L27/153—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/0004—Devices characterised by their operation
- H01L33/0008—Devices characterised by their operation having p-n or hi-lo junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/36—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
- H01L33/40—Materials therefor
- H01L33/42—Transparent materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
Abstract
The invention provides a high-voltage LED chip manufacturing method and a high-voltage LED chip, wherein the method comprises the following steps: providing a substrate; epitaxially growing an epitaxial layer on a substrate, wherein the epitaxial layer at least comprises an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are deposited in sequence; etching the P-type semiconductor layer to the substrate direction until the N-type semiconductor layer is exposed, so as to form an N-type mesa and a P-type mesa; etching the N-type table top to form a first isolation channel for dividing a plurality of crystal grains and a second isolation channel for dividing a plurality of high-voltage LED chips on the N-type table top; growing a first insulating protection layer, and etching the first insulating protection layer according to a preset pattern to expose the N-type table top and the P-type table top; manufacturing electrodes on the exposed N-type table top and the exposed P-type table top; the corresponding number of dies is set as a group and the electrodes of different polarities of adjacent dies in the group are bridged. The invention can ensure that the chip has larger luminous area and improve the condition that the electrode connecting bridge is easy to break.
Description
Technical Field
The invention relates to the technical field of LED chips, in particular to a high-voltage LED chip manufacturing method and a high-voltage LED chip.
Background
The high-voltage LED chip is a light-emitting diode chip formed by dividing an epitaxial layer of a large-size chip into a plurality of single-particle grains in a mode of etching isolation grooves in the manufacturing process of the chip and connecting corresponding electrodes of adjacent grains in series.
The structure of a single die of a high voltage LED chip of existing parallel structure generally comprises: in order to form a plurality of single-grain grains and electrically connect the grains in series, the substrate, the N-type semiconductor layer, the active layer, the P-type semiconductor layer and the electrode are required to etch an isolation groove between adjacent grains to the surface of the substrate, then deposit a PV passivation layer on the isolation groove, and finally vapor plating an electrode connecting bridge on the PV passivation layer to connect the electrodes with different polarities of the adjacent grains in series.
However, in order to prevent the electrode connection bridge from being broken, the side wall of the isolation trench is often designed to be relatively gentle, and the opening above the isolation trench is large at this time, resulting in a small light emitting area of a single die. In addition, when the patterned substrate is adopted by some chips, the patterned substrate is etched irregularly, so that the PV passivation layer is deposited irregularly, and at the moment, the electrode connecting bridge evaporated on the PV passivation layer is easily disconnected, so that the functional integrity of the chips is affected.
Disclosure of Invention
Based on the above, the invention aims to provide a high-voltage LED chip manufacturing method and a high-voltage LED chip, so that the situation that an electrode connecting bridge is easy to break is improved when the manufactured high-voltage LED chip ensures a large light emitting area.
In one aspect, the invention provides a method for manufacturing a high-voltage LED chip, which comprises the following steps of S100-S700:
s100, providing a substrate;
s200, epitaxially growing an epitaxial layer on a substrate, wherein the epitaxial layer at least comprises an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are deposited in sequence;
s300, etching the P-type semiconductor layer to the substrate direction until the N-type semiconductor layer is exposed, so as to form an N-type mesa and a P-type mesa;
s400, etching the N-type table top to form a first isolation channel for dividing a plurality of crystal grains and a second isolation channel for dividing a plurality of high-voltage LED chips on the N-type table top;
s500, integrally growing a first insulating protection layer, and etching the first insulating protection layer according to a preset pattern to expose the N-type table top and the P-type table top;
s600, manufacturing electrodes on the exposed N-type table top and the exposed P-type table top;
s700, setting a corresponding number of crystal grains into a group, and bridging electrodes with different polarities of adjacent crystal grains in the group.
In addition, the method for manufacturing the high-voltage LED chip can also have the following additional technical characteristics:
further, before etching the first insulating protection layer according to the preset pattern, the method further comprises: and carrying out CMP treatment on the first insulating protection layer, wherein the thickness of the treated first insulating protection layer is 2000-6000A and is more than 70% of the width of the first isolation channel.
Further, etching the first insulating protection layer according to a preset pattern specifically includes: and carrying out wet etching on the first insulating protective layer according to the CBL mask pattern to form a third isolation channel exposing the N-type mesa and a fourth isolation channel exposing the P-type mesa.
Further, step S600 specifically includes steps S610 to S640:
s610, growing a transparent conductive layer to cover the surface of the fourth isolation channel and part of the surface of the first insulating protection layer;
s620, epitaxially growing a first metal layer on a part of the region of the transparent conductive layer and the bottom of the third isolation channel;
s630, integrally growing a second insulating protection layer to cover the first insulating protection layer and the first metal layer;
s640, etching the second insulating protection layer to expose part of the first metal layer.
Further, before step S640, the method further includes: and annealing the transparent conductive layer, wherein the annealing temperature is 450-650 ℃.
Further, step S700 specifically includes steps S710 to S730:
s710, epitaxially growing a second metal layer covering the etching area of the second insulating protective layer on the second insulating protective layer so as to electrically connect the first metal layers with different polarities on the adjacent crystal grains in series;
s720, epitaxially growing a third insulating protection layer to cover the second metal layer;
and S730, etching the third insulating protection layer to expose the second metal layer part of the head and tail grains in the same group.
Further, after step S730, the method further includes: and epitaxially growing a third metal layer covering the etching area of the third insulating protective layer on the third insulating protective layer to form an N-type electrode and a P-type electrode of the high-voltage LED chip.
Further, the second insulating protection layer is a reflective layer having a DBR structure.
Further, the first isolation channel has a width of 1 micron to 4 microns and the second isolation channel has a width of greater than 6 microns.
Based on the same inventive concept, the invention also provides a high-voltage LED chip, which is prepared by the method for manufacturing the high-voltage LED chip.
According to the high-voltage LED chip manufacturing method and the high-voltage LED chip, the first insulating protective layer is directly epitaxially grown on the substrate, meanwhile, the first insulating protective layer is filled in the first isolation channel, and then the first insulating protective layer is windowed to facilitate the subsequent electrode extraction, so that the first isolation channel can be etched to be better in perpendicularity when the chip is manufactured, namely, the side wall of the first isolation channel is relatively steep, an opening above the first isolation channel is not quite large, and the problem that the loss of the area of an active layer is increased due to the oversized opening, so that the luminous efficiency of the chip is reduced is avoided. Meanwhile, the electrode connecting bridge is arranged at the isolation channel, the thickness of the electrode connecting bridge deposited on the side wall, the bottom wall and the electrode table top of the isolation channel is not consistent when the electrode connecting bridge is in vertical evaporation, the thickness of the deposited side wall inclined to the isolation channel is thinner generally, disconnection is easy to occur, in the application, the first isolation channel is completely filled by the first insulating protective layer, the effect of electrically isolating adjacent grains is achieved, the electrode connecting bridge is not required to be arranged at the isolation channel, a metal layer can be directly grown on the first insulating protective layer to interconnect P, N poles of adjacent grains like the conventional high-voltage LED chip, the process is simple compared with the electrode connecting bridge, the growth thickness is uniform, the disconnection is difficult, and the problem that the electrode connecting bridge is easy to break in the conventional high-voltage LED chip is effectively solved.
Drawings
FIG. 1 is a flow chart of a method for fabricating a high voltage LED chip in an embodiment of the invention;
FIG. 2 is a schematic diagram of the structure of an etched epitaxial layer according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a structure after epitaxially growing a first insulating layer according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of the structure of the first insulating layer in the embodiment of FIG. 3 after etching;
FIG. 5 is a schematic diagram of the structure after epitaxially growing the transparent conductive layer and the first metal layer according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a structure after the second insulating protection layer is epitaxially grown in an embodiment of the present invention;
FIG. 7 is a schematic diagram of a structure after epitaxially growing a second metal layer according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a structure of a third insulation protection layer and a third metal layer after epitaxial growth in an embodiment of the present invention;
description of main reference numerals:
| substrate and method for manufacturing the same | 101 | Epitaxial layer | 102 |
| First insulating protective layer | 103 | Transparent conductive layer | 104 |
| A first metal layer | 105 | Second insulating protective layer | 106 |
| Second metal layer | 107 | Third insulating protective layer | 108 |
| Third metal layer | 109 | N-type table top | 201 |
| P-type table top | 202 | First isolation trench | 203 |
| Second isolation trench | 204 | Third isolation trench | 205 |
| Fourth isolation channel | 206 |
The invention will be further described in the following detailed description in conjunction with the above-described figures.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Several embodiments of the invention are presented in the figures. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
It will be understood that when an element is referred to as being "mounted" on another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
In the process of etching the isolation groove, if the verticality of the high-voltage LED chip is better, namely the side wall of the groove is designed into a relatively steep form, the phenomenon of incomplete coverage of the side wall easily occurs when the PV passivation layer is deposited on the side wall of the groove later, and in the process of evaporating an electrode connecting bridge, the phenomenon of bridge cutoff easily occurs on the side wall of the groove because the evaporation process of an evaporator is basically vertical evaporation. Therefore, the side wall of the groove is designed to be relatively gentle, so that no matter the PV passivation layer is deposited or the electrode connecting bridge is evaporated, the phenomenon of climbing is generated, and instability caused by the excessively vertical side wall can be effectively avoided.
However, the sidewall of the isolation trench is designed to be relatively gentle, and the opening above the trench isolation trench is larger, and the loss of the active area is increased, so that the optical power of the high-voltage LED chip is reduced. In addition, in order to improve the luminous efficiency, some types of LED chips adopt a patterned substrate technology, but the patterned substrate is etched irregularly, so that the PV passivation layer is deposited irregularly, and the electrode connection bridge evaporated on the PV passivation layer is easily broken, which affects the functional integrity of the chip. Therefore, the high-voltage LED chip manufacturing method and the high-voltage LED chip are provided, so that the manufactured high-voltage LED chip can ensure a larger light emitting area and improve the condition that an electrode connecting bridge is easy to break.
Referring to fig. 1, the method for manufacturing a high voltage LED chip of the present invention specifically includes steps S100-S700:
s100, providing a substrate 101;
specifically, as shown in fig. 2, the material of the substrate 101 may be one of sapphire, siC, si and ZnO, and the substrate 101 may be one of a patterned substrate and a flat substrate.
S200, epitaxially growing an epitaxial layer 102 on a substrate 101, wherein the epitaxial layer 102 at least comprises an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are deposited in sequence;
as an exemplary illustration, the basic structure of a single die of a GaN-based high-voltage LED chip may be: the sapphire patterned substrate, an N-type GaN layer, a multi-layer quantum well layer and a P-type GaN layer.
S300, etching the P-type semiconductor layer to the direction of the substrate 101 until the N-type semiconductor layer is exposed, so as to form an N-type mesa 201 and a P-type mesa 202;
specifically, as shown in fig. 2, using the MESA layer as a mask, photoresist coating, exposure and development are sequentially performed on the epitaxial layer 102, and then ICP etching is performed on the epitaxial layer 102 to expose the N-type MESA 201 and the P-type MESA 202, wherein the etched region of the epitaxial layer 102 forms the N-type MESA 201, and the non-etched region of the epitaxial layer 102 forms the P-type MESA 202 after the photoresist is cleaned.
S400, etching the N-type table 201 to form a first isolation channel 203 for dividing a plurality of crystal grains and a second isolation channel 204 for dividing a plurality of high-voltage LED chips on the N-type table 201;
specifically, as shown in fig. 2, using the ISO layer as a mask, photoresist coating, exposure, and development are sequentially performed on the epitaxial layer 102, and then the epitaxial layer 102 is subjected to ICP etching, to finally form a first isolation channel 203 dividing a plurality of grains and a second isolation channel 204 dividing a plurality of high-voltage LED chips.
In this step, by etching the first isolation channel 203 and the second isolation channel 204 formed by the epitaxial layer 102, good electrical isolation can be formed between adjacent high-voltage LED chips and between adjacent dies, so as to prevent leakage.
S500, as shown in FIG. 3, integrally growing the first insulation protection layer 103, and etching the first insulation protection layer 103 according to a preset pattern to expose the N-type mesa 201 and the P-type mesa 202;
since the N-type semiconductor layer, the active layer, and the P-type semiconductor layer are exposed to the working environment at this time, moisture and dust are easily absorbed to fail, and thus it is necessary to deposit the first insulating protection layer 103 on the epitaxial layer 102. Alternatively, the first insulating protective layer 103 may be one or more of silicon dioxide, aluminum oxide, silicon nitride, and the like. For example, when the first insulating protection layer 103 made of silicon dioxide or silicon nitride is manufactured, a high temperature is often required, and in this case, in order to prevent the active region in the epitaxial layer 102 from being damaged, a PECVD process may be used to deposit a silicon dioxide or silicon nitride polycrystalline or amorphous film.
In order to planarize the deposited first insulating protection layer 103 for the subsequent growth of the layered structure, in some alternative embodiments, a CMP (chemical mechanical polishing) process of the first insulating protection layer 103 is required before etching the first insulating protection layer 103. Preferably, the thickness of the first insulating protective layer 103 after the treatment is 2000 to 6000 a. Meanwhile, in order to ensure that the first insulating protection layer 103 filled in the first isolation channel 203 is sufficiently closed at this time, the thickness of the first insulating protection layer 103 needs to be greater than 70% of the width of the first isolation channel 203. The thickness of the first insulating protection layer 103 is a height relative to the upper surface of the epitaxial layer 102.
When the first insulating protection layer 103 is etched, a CBL layer is used as a mask, photoresist coating, exposure and development are sequentially performed on the first insulating protection layer 103, and then wet etching is performed. For example, when the first insulating protective layer 103 is made of silicon dioxide, wet etching in a BOE solution, preferably for 200-800s, is selected, wherein the BOE solution is a weakly acidic solution, and the main component is HF: HN 4 F=4:1, which reacts with the silicon dioxide as a mask, effectively etching the portion of the mask that is not protected by the photoresist. After the etching is completed, as shown in fig. 4, the first insulating protection layer 103 forms a CBL layer, and at this time, a third isolation channel 205 exposing a portion of the N-type mesa 201 and a fourth isolation channel 206 exposing a portion of the P-type mesa 202 are formed.
In this step, the wet etching is performed by immersing the chip in the solution, so that the etching is isotropic, and although the etching precision is low, the isotropy of the wet etching is also the result, so that the transition between the etched third isolation trench 205 and the etched fourth isolation trench 206 is gentle, and the method has the advantages of simple process, low damage, low cost and the like.
S600, in order to connect the high-voltage LED chip with an external circuit and electrically connect adjacent grains in series, electrodes are required to be manufactured on the exposed N-type table-board 201 and the exposed P-type table-board 202;
s700, setting a corresponding number of crystal grains into a group, and bridging electrodes with different polarities of adjacent crystal grains in the group. As shown in fig. 2 to 8, one high voltage LED chip is composed of three dies. It will be appreciated that the drawings are illustrative only and that other numbers of dies may be used to form a high voltage LED chip.
In some alternative embodiments, step S600 specifically includes steps S610-S640:
s610, as shown in fig. 5, epitaxially growing the transparent conductive layer 104 to cover the surface of the fourth isolation channel 206 and a part of the surface of the first insulating protection layer 103;
alternatively, the transparent conductive layer 104 may be made of one or more inorganic materials such as GIO, ZITO, ITO, or organic materials such as nano silver wire, so long as the transparency > 80% is satisfied and the resistivity is lower than that of the P-type semiconductor layer. The specific deposition process depends on the material used for the transparent conductive layer 104, for example, when ITO (indium tin oxide) is used for the transparent conductive layer 104, a magnetron sputtering method is preferably used to form a highly dense ITO transparent conductive layer.
In order to remove unnecessary areas of the transparent conductive layer 104, in implementation:
firstly, sequentially performing photoresist coating, exposure and development on a transparent conductive layer 104, so as to form a corresponding pattern layer on the photoresist layer, taking the pattern layer formed by the photoresist as a barrier layer, soaking the pattern layer in etching liquid of the transparent conductive layer 104 for 3-15 minutes, and etching the transparent conductive layer in an area which is not protected by the photoresist, wherein the etching liquid adopted specifically depends on the material adopted by the transparent conductive layer 104, for example, when the transparent conductive layer 104 adopts ITO (indium tin oxide), preferably, the ITO etching liquid is adopted, and the main component of the etching liquid is ferric chloride;
then, the residual photoresist in the previous step is removed and rinsed clean with deionized water.
In the step, by arranging the transparent conductive layer 104, current can be transmitted from the electrode to the P-type semiconductor layer, meanwhile, due to the existence of the first insulating protective layer 103, on one hand, the current can be prevented from diffusing to the lower part of the electrode, and the current density flowing to an active area below the electrode metal is reduced, so that the light loss caused by light absorption and light blocking of the electrode metal is reduced; on the other hand, the current can be led to a region far away from the electrode, so that current crowding nearby the electrode is reduced, and the light-emitting power can be improved.
S620, as shown in FIG. 5, growing a first metal layer 105 on a part of the area of the transparent conductive layer 104 and the bottom of the third isolation channel 205;
specifically, firstly, a layer of negative photoresist is coated on the upper surface of the epitaxial layer 102, and exposure and development are sequentially performed; next, the first metal layer 105 is deposited on the surface of the area not protected by the photoresist by using an electron beam deposition technique; finally, lift-off processes are used to remove unwanted areas of photoresist and metal layers on the surface of epitaxial layer 102. Alternatively, the first metal layer 105 may be composed of one or more of metal materials such as Ni, al, ti, au, pt.
S630, in order to protect the first metal layer 105, prevent it from leaking, breaking and from contamination, as shown in fig. 6, a second insulating protection layer 106 needs to be grown entirely on the epitaxial layer 102 to cover the first insulating protection layer 103 and the first metal layer 105. In order to improve the light extraction efficiency of the chip, the second insulating protection layer 106 is preferably a reflective layer having a DBR (distributed bragg reflector) structure. In specific implementation, a reflective layer is deposited on the upper surface of the epitaxial layer 102 by an evaporation process, where the reflective layer is formed by alternately stacking a low refractive index silicon dioxide layer and a high refractive index titanium dioxide layer.
S640, as shown in fig. 6, the second insulating protection layer 106 is etched to expose a portion of the first metal layer 105.
Specifically, first, photoresist coating, exposure and development are performed on the upper surface of the second insulating protection layer 106, so that a corresponding layer is formed on the photoresist layer, and the layer formed by the photoresist is used as a barrier layer; then, a part of the area of the second insulating protection layer 106 is etched away by dry etching, so that a part of the first metal layer 105 is exposed, and subsequent circuit interconnection is facilitated.
In some alternative embodiments, prior to step S640, further comprising: the chip is placed in an annealing furnace to anneal the transparent conductive layer 104, preferably at a temperature of 450-650 ℃.
This step can improve the transmittance of the transparent conductive layer 104 and reduce the resistivity of the transparent conductive layer 104 by annealing the transparent conductive layer 104.
In some alternative embodiments, step S700 specifically includes steps S710-S730:
s710, as shown in FIG. 7, epitaxially growing a second metal layer 107 covering the etched region of the second insulation protection layer 106 on the second insulation protection layer 106 to electrically connect the first metal layers 105 with different polarities on the adjacent grains in series;
specifically, firstly, a layer of negative photoresist is coated on the upper surface of the epitaxial layer 102, and exposure and development are sequentially performed; next, a second metal layer 107 is deposited on the surface of the region not protected by the photoresist using an electron beam deposition technique; finally, lift-off processes are used to remove unwanted areas of photoresist and metal layers on the surface of epitaxial layer 102. Alternatively, the second metal layer 107 may be composed of one or more of metal materials such as Ni, al, ti, au, pt.
S720, in order to protect the second metal layer 107, prevent it from leakage, break and contamination, as shown in FIG. 8, a third insulating protection layer 108 needs to be epitaxially grown on the epitaxial layer 102 to cover the second metal layer 107;
s730, as shown in fig. 8, etching the third insulating protection layer 108 to expose the second metal layer 107 of the first and the last grains in the same group;
specifically, first, photoresist coating, exposing and developing are performed on the upper surface of the third insulating protection layer 108, so that a corresponding layer is formed on the photoresist layer, and the layer formed by the photoresist is used as a barrier layer; then, a part of the area of the third insulating protection layer 108 is etched away by dry etching, so that a part of the second metal layer 107 is exposed, and subsequent circuit interconnection is facilitated.
In some alternative embodiments, as shown in fig. 8, after step S730, the method further includes: a third metal layer 109 covering the etched region of the third insulating protective layer 108 is epitaxially grown on the third insulating protective layer 108 to form N-type and P-type electrodes of the high voltage LED chip.
The specific implementation method comprises the following steps: firstly, coating a layer of negative photoresist on the upper surface of an epitaxial layer 102, and sequentially exposing and developing; next, a third metal layer 109 is deposited on the surface of the region not protected by the photoresist using an electron beam deposition technique; finally, lift-off processes are used to remove unwanted areas of photoresist and metal layers on the surface of epitaxial layer 102. Alternatively, the third metal layer 109 may be composed of one or more of the metal materials Ni, al, ti, au, pt and the like.
The invention is further illustrated by the following examples:
comparative example one:
the embodiment provides a high-voltage LED chip, which comprises a substrate 101 and an epitaxial wafer 102, wherein the width of a first isolation channel 203 is 5 micrometers.
Embodiment one:
the embodiment provides a high-voltage LED chip, which includes a substrate 101 and an epitaxial wafer 102, wherein the width of a first isolation channel 203 is 1 micron, and the thickness of a first insulating protection layer 103 is 1 micron.
Embodiment two:
the embodiment provides a high-voltage LED chip, which comprises a substrate 101 and an epitaxial wafer 102, wherein the width of a first isolation channel 203 is 1.5 micrometers, and the thickness of a first insulating protection layer 103 is 1 micrometer.
Embodiment III:
the embodiment provides a high-voltage LED chip, which comprises a substrate 101 and an epitaxial wafer 102, wherein the width of a first isolation channel 203 is 2 micrometers, and the thickness of a first insulating protection layer 103 is 1.5 micrometers.
Embodiment four:
the embodiment provides a high-voltage LED chip, which comprises a substrate 101 and an epitaxial wafer 102, wherein the width of a first isolation channel 203 is 3 micrometers, and the thickness of a first insulating protection layer 103 is 2.5 micrometers.
The high voltage LED chips provided in comparative example one and examples one to four were tested under the same conditions (test current of 15 mA), and the relevant results were shown in table 1:
TABLE 1
As can be seen from table 1, in the high-voltage LED chip obtained by the method in the embodiment of the present invention, under the same test conditions, compared with the high-voltage LED chip in the first comparative example, when the thickness of the first insulating protection layer 103 is within a reasonable range, the light-emitting brightness and the light efficiency are effectively improved, and meanwhile, the width of the first isolation channel 203 between adjacent grains in the same high-voltage LED chip can be etched to be smaller, so that the loss of the active layer area due to the excessive opening is avoided from being increased, and the light-emitting efficiency of the chip is reduced.
In addition, the invention also provides a high-voltage LED chip, which is prepared by the manufacturing method of the high-voltage LED chip.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The foregoing examples illustrate only a few embodiments of the invention and are described in detail herein without thereby limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. The manufacturing method of the high-voltage LED chip is characterized by comprising the following steps of:
providing a substrate;
epitaxially growing an epitaxial layer on the substrate, wherein the epitaxial layer at least comprises an N-type semiconductor layer, an active layer and a P-type semiconductor layer which are deposited in sequence;
etching the P-type semiconductor layer to the substrate direction until the N-type semiconductor layer is exposed, so as to form an N-type mesa and a P-type mesa;
etching the N-type table top to form a first isolation channel for dividing a plurality of crystal grains and a second isolation channel for dividing a plurality of high-voltage LED chips on the N-type table top;
integrally growing a first insulating protection layer, and etching the first insulating protection layer according to a preset pattern to expose the N-type table top and the P-type table top;
manufacturing electrodes on the exposed N-type table top and the exposed P-type table top;
the corresponding number of dies is set as a group and the electrodes of different polarities of adjacent dies in the group are bridged.
2. The method of manufacturing a high voltage LED chip of claim 1, further comprising the step of, before said etching said first insulating protective layer in a predetermined pattern:
and carrying out CMP treatment on the first insulating protection layer, wherein the thickness of the first insulating protection layer after treatment is 2000-6000 microns and is more than 70% of the width of the first isolation channel.
3. The method of manufacturing a high voltage LED chip of claim 1, wherein said etching said first insulating protective layer in a predetermined pattern comprises the steps of:
and carrying out wet etching on the first insulating protective layer according to the CBL mask pattern to form a third isolation channel exposing the N-type table top and a fourth isolation channel exposing the P-type table top.
4. The method of manufacturing a high voltage LED chip of claim 3, wherein said manufacturing electrodes on exposed N-type mesas and P-type mesas comprises the steps of:
growing a transparent conductive layer to cover the fourth isolation channel surface and a part of the first insulating protection layer surface;
epitaxially growing a first metal layer on a part of the transparent conductive layer and the bottom of the third isolation channel;
integrally growing a second insulating protection layer to cover the first insulating protection layer and the first metal layer;
and etching the second insulating protection layer to expose part of the first metal layer.
5. The method of manufacturing a high voltage LED chip of claim 4, further comprising the steps of:
and carrying out annealing treatment on the transparent conductive layer, wherein the annealing temperature is 450-650 ℃.
6. The method of manufacturing a high voltage LED chip of claim 4 or 5, wherein said grouping the corresponding number of dies into a group and bridging the different polarity electrodes of adjacent dies in the group comprises the steps of:
epitaxially growing a second metal layer covering the etching area of the second insulating protective layer on the second insulating protective layer so as to electrically connect the first metal layers with different polarities on the adjacent crystal grains in series;
epitaxially growing a third insulating protection layer to cover the second metal layer;
and etching the third insulating protection layer to expose the second metal layer part of the head and tail grains in the same group.
7. The method of manufacturing a high voltage LED chip of claim 6, further comprising the step of, after said etching said third insulating protective layer to expose portions of said second metal layers of said first and second die in the same group:
and epitaxially growing a third metal layer covering the etching area of the third insulating protective layer on the third insulating protective layer to form an N-type electrode and a P-type electrode of the high-voltage LED chip.
8. The method of manufacturing a high voltage LED chip as claimed in claim 4 or 5, wherein the second insulating protection layer is a reflective layer having a DBR structure.
9. The method of manufacturing a high voltage LED chip of claim 1, wherein said first isolation channel has a width of 1 micron to 4 microns and said second isolation channel has a width of greater than 6 microns.
10. A high voltage LED chip, characterized in that the high voltage LED chip is manufactured by the high voltage LED chip manufacturing method according to any one of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311404685.1A CN117374176A (en) | 2023-10-26 | 2023-10-26 | High-voltage LED chip manufacturing method and high-voltage LED chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311404685.1A CN117374176A (en) | 2023-10-26 | 2023-10-26 | High-voltage LED chip manufacturing method and high-voltage LED chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117374176A true CN117374176A (en) | 2024-01-09 |
Family
ID=89394391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311404685.1A Pending CN117374176A (en) | 2023-10-26 | 2023-10-26 | High-voltage LED chip manufacturing method and high-voltage LED chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117374176A (en) |
-
2023
- 2023-10-26 CN CN202311404685.1A patent/CN117374176A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8735185B2 (en) | Light emitting device and fabrication method thereof | |
| US8698181B2 (en) | Light emitting device | |
| US9087971B2 (en) | Light-emitting device having dielectric reflector and method of manufacturing the same | |
| US8124985B2 (en) | Semiconductor light emitting device and method for manufacturing the same | |
| CN101656260B (en) | Antistatic GaN-based luminescent device and preparation method thereof | |
| US20050179042A1 (en) | Monolithic integration and enhanced light extraction in gallium nitride-based light-emitting devices | |
| EP2860753A1 (en) | Method of fabricating vertical structure LEDs | |
| CN110729322B (en) | Vertical LED chip structure and manufacturing method thereof | |
| TW202127686A (en) | Light-emitting device | |
| CN102790045A (en) | Light emitting diode array and manufacturing method thereof | |
| US20130119427A1 (en) | Led substrate, led chip and method for manufacturing the same | |
| JP5632034B2 (en) | Light emitting diode chip and manufacturing method thereof | |
| US20070065959A1 (en) | Method for manufacturing light-emitting diode | |
| CN103682021B (en) | Metal electrode has light emitting diode and the manufacture method thereof of array type micro structure | |
| CN117374176A (en) | High-voltage LED chip manufacturing method and high-voltage LED chip | |
| KR20120081042A (en) | Gan compound semiconductor light emitting element | |
| KR20150043748A (en) | Method of forming patterns for semiconductor device | |
| CN107546307B (en) | Light emitting diode and preparation method thereof | |
| EP2830105A1 (en) | Light emitting diode and manufacturing method thereof | |
| CN112002789A (en) | High-power light-emitting chip and manufacturing method thereof | |
| CN217588966U (en) | Light-emitting diode | |
| CN217387195U (en) | Flip-chip type MICROLED chip structure | |
| CN113594084A (en) | Preparation method of isolation structure, high-voltage light-emitting device and manufacturing method thereof | |
| CN112242406A (en) | Array substrate, manufacturing method thereof and display device | |
| CN117080341A (en) | LED chip and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |