CN113594084A - Preparation method of isolation structure, high-voltage light-emitting device and manufacturing method thereof - Google Patents
Preparation method of isolation structure, high-voltage light-emitting device and manufacturing method thereof Download PDFInfo
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- H01L27/156—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components with at least one potential-jump barrier or surface barrier specially adapted for light emission in a repetitive configuration, e.g. LED bars two-dimensional arrays
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Abstract
The application relates to the technical field of semiconductors, in particular to a preparation method of an isolation structure for a high-voltage light-emitting device, the high-voltage light-emitting device and a manufacturing method thereof, wherein the preparation method of the isolation structure for the high-voltage light-emitting device comprises the following steps: forming a line type insulating layer on a substrate; and etching the substrate by taking the line type insulating layer as a mask to form n line type isolation walls and n-1 grooves to obtain an isolation structure, wherein two adjacent grooves are separated by the line type isolation walls. Through the mode, the linear isolation walls on the substrate are used for isolating the light-emitting epitaxial layers, so that the active layer area loss caused by etching of the active layer is avoided, and the utilization rate of the active layer is improved.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing an isolation structure for a high voltage light emitting device, and a method for manufacturing the high voltage light emitting device.
Background
In recent years, due to the progress of technology and efficiency, the application of the LED is more and more extensive. With the upgrading of LED applications, the market demand for LEDs is moving towards higher power and higher brightness, i.e. high power LEDs. For realizing high power LEDs, the design of high voltage light emitting diodes is one of the solutions at present.
In the long research and development process of the present application, the inventor finds that the current high voltage light emitting diode is implemented by connecting a plurality of LED units in series or in series and parallel, the LED units are discrete devices, or the LED units are separated from each other and fabricated on the same substrate by a single chip integration method. For the monolithic integration scheme, in order to realize the isolation between the GaN-based LED units, a trench needs to be deeply etched in the GaN layer to separate the epitaxial structures of the LED units, and the metal connection lines connected in series with the LED units need to pass through the trench, so as to ensure that the metal connection lines are not broken during series connection, the etching angle is generally controlled below 50 °, which results in an excessively large etching area of the active layer of each LED unit and a low utilization rate, and meanwhile, the etched surface has a large number of non-radiative recombination centers which seriously restrict the improvement of the optical performance.
Disclosure of Invention
The application provides a preparation method of an isolation structure for a high-voltage light-emitting device, the high-voltage light-emitting device and a manufacturing method thereof, and aims to solve the technical problems in the prior art.
In order to solve the technical problem, the application adopts a technical scheme that: provided is a method for preparing an isolation structure for a high voltage light emitting device, including: forming a line type insulating layer on a substrate; and etching the substrate by taking the line type insulating layer as a mask to form n line type isolation walls and n-1 grooves to obtain an isolation structure, wherein two adjacent grooves are separated by the line type isolation walls.
In order to solve the above technical problem, another technical solution adopted by the present application is: provided is a method of manufacturing a high voltage light emitting device, including: providing an isolation structure, wherein the isolation structure is prepared by the method; respectively growing n-1 light-emitting epitaxial layers on the n-1 grooves, wherein the light-emitting epitaxial layers comprise a first semiconductor layer, an active layer and a second semiconductor layer which are arranged in a stacked mode, a mesa structure is formed on one side, facing the second semiconductor layer, of the first semiconductor layer, and the upper surface of the part, close to one side of the line type isolation wall, of the first semiconductor layer is exposed; forming n-1 insulating medium layers, wherein the 1 st insulating medium layer covers a local area of one side, away from the substrate, of the 1 st second semiconductor, and the ith insulating medium layer covers a local area of one side, away from the substrate, of the ith second semiconductor, an ith line type isolation wall between two adjacent light-emitting epitaxial layers and a local upper surface of the i-1 st first semiconductor layer close to one side of the ith line type isolation wall; forming n-1 current diffusion layers, wherein the 1 st current diffusion layer covers one side of the 1 st insulating medium layer, which is far away from the second semiconductor, and the ith current diffusion layer covers one side of the ith insulating medium layer, which is far away from the second semiconductor, and a local area of one side of the ith second semiconductor, which is far away from the substrate; forming n-2 interconnection metal layers, wherein the (i-1) th interconnection electrode layer covers the local upper surface of the (i-1) th first semiconductor layer, the (i) th insulating medium layer and one side of the (i) th current diffusion layer, which is deviated from the insulating medium layer, so that two adjacent light-emitting epitaxial layers separated by the line-type isolation wall are electrically connected in series; forming a first conductive type electrode on one side of the 1 st current diffusion layer, which is far away from the insulating medium layer, and forming a second conductive type electrode on the local upper surface of the nth first semiconductor layer to obtain a high-voltage light-emitting device; wherein i is more than or equal to 2 and less than or equal to n-1, and i and n are integers.
In order to solve the above technical problem, another technical solution adopted by the present application is: there is provided a high voltage light emitting device comprising: the device comprises a substrate, wherein n line-type isolation walls and n-1 grooves are arranged on one side of the substrate, and two adjacent grooves are isolated by the line-type isolation walls; the light-emitting epitaxial layer comprises a first semiconductor layer, an active layer and a second semiconductor layer which are sequentially stacked in the groove, wherein a mesa structure is formed on one side, facing the second semiconductor layer, of the first semiconductor layer, and the upper surface of the part, close to one side of the line-type isolation wall, of the first semiconductor layer is exposed; n-1 insulating medium layers, wherein the 1 st insulating medium layer covers a local area of one side, away from the substrate, of the 1 st second semiconductor, and the ith insulating medium layer covers a local area of one side, away from the substrate, of the ith second semiconductor, an ith line type isolation wall between two adjacent light-emitting epitaxial layers and a local upper surface of the i-1 st first semiconductor layer close to one side of the ith line type isolation wall; n-1 current diffusion layers, wherein the 1 st current diffusion layer covers one side of the 1 st insulating medium layer, which is far away from the second semiconductor, and the ith current diffusion layer covers one side of the ith insulating medium layer, which is far away from the second semiconductor, and a local area of one side of the ith second semiconductor, which is far away from the substrate; the n-2 interconnection metal layers, wherein the (i-1) th interconnection electrode layer covers the local upper surface of the (i-1) th first semiconductor layer, the (i) th insulating medium layer and one side of the (i) th current diffusion layer, which is far away from the insulating medium layer, so that two adjacent light-emitting epitaxial layers separated by the line-type isolation wall are electrically connected in series; a first conductive type electrode formed on a partial upper surface of the nth first semiconductor layer; the second conductive type electrode is formed on one side, away from the insulating medium layer, of the 1 st current diffusion layer; wherein i is more than or equal to 2 and less than or equal to n-1, and i and n are integers.
Different from the prior art, the application has the following beneficial effects:
(1) deep etching of the GaN layer is cancelled, non-radiative recombination centers on the etched surface are reduced, and luminous efficiency is improved;
(2) the light-emitting epitaxial layers are isolated through the linear isolation walls on the substrate, so that the area loss of the active layer caused by etching the active layer is avoided, and the utilization rate of the active layer is improved;
(3) the depth of the groove of the isolation structure is equal to the thickness of the light-emitting epitaxial layers, so that the metal connecting wire which is connected with each light-emitting epitaxial layer in series is prevented from breaking due to the fact that the metal connecting wire needs to penetrate through the groove, and meanwhile the length of the interconnection metal layer can be reduced;
(4) the width of the linear isolation wall is 3-8 mu m, the distance between two adjacent light-emitting epitaxial layers is greatly reduced, and the area of the active layer can be increased by 5-10%;
(5) the size of the groove is adjustable, the width of the light-emitting epitaxial layer can be adjusted in the direction parallel to the line type isolation wall so as to meet the requirements of different brightness under the specified voltage, and meanwhile, the light-emitting epitaxial layers with different numbers can be connected in series in the direction perpendicular to the line type isolation wall so as to meet the requirements of different voltages.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts. Wherein:
FIG. 1 is a schematic structural diagram of an embodiment of an isolation structure for a high voltage light emitting device according to the present invention;
FIG. 2 is a schematic structural diagram of another embodiment of an isolation structure for a high voltage light emitting device according to the present application;
FIG. 3 is a schematic structural diagram of an embodiment of a high voltage light emitting device according to the present application;
FIG. 4 is a schematic top view of an embodiment of a high voltage light emitting device according to the present application;
FIG. 5 is a schematic flow chart illustrating an embodiment of a method for manufacturing a high voltage light emitting device according to the present application;
FIG. 6 is a schematic structural diagram of another embodiment of a high voltage light emitting device according to the present application;
fig. 7 is a schematic flow chart of another embodiment of a method for manufacturing a high voltage light emitting device according to the present application.
Detailed Description
Several embodiments of the present application will be described in further detail below with reference to the accompanying drawings. The following description and illustrations of the embodiments do not limit the scope of the present application in any way.
It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used in this application, specify the presence of stated features, integers, steps, components, and/or groups thereof, but do not preclude the presence or addition or deletion of one or more other features, integers, steps, components, groups thereof, and/or groups thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Example 1
The present embodiment provides an isolation structure 11 for a high voltage light emitting device 10 and a method for manufacturing the same, where the isolation structure 11 is as shown in fig. 1, and specifically includes: the semiconductor device includes a substrate 100 and a line type insulating layer 200 located on one side of the substrate 100, wherein one side of the substrate 100 is provided with n line type isolation walls 101 and n-1 trenches 102, and two adjacent trenches 102 are separated by the line type isolation wall 101.
The substrate 100 may be a sapphire substrate, a silicon carbide substrate, a diamond substrate, an aluminum nitride substrate, or a gallium nitride-like substrate, and is preferably a sapphire substrate.
The material of the line type insulating layer 200 may be silicon dioxide or silicon nitride, the thickness of the line type insulating layer 200 may be 0.5 to 2 μm, and the width of the line type insulating layer 200 may be 3 to 8 μm.
The method for preparing the isolation structure 11 for the high voltage light emitting device 10 comprises the following steps:
s101: a substrate 100 is provided.
S102: a line type insulating layer 200 is formed on the substrate 100.
Specifically, the line type insulating layer 200 is formed on the substrate 100 by an electron beam evaporation or plasma enhanced chemical vapor deposition process. The line type insulating layer 200 may be made of silicon dioxide or silicon nitride, the thickness H1 of the line type insulating layer 200 may be 0.5 to 2 μm, and the width D1 of the line type insulating layer 200 may be 3 to 8 μm.
S103: the substrate 100 is etched using the line-type insulating layer 200 as a mask to form n line-type isolation walls 101 and n-1 trenches 102, thereby obtaining the isolation structure 11, wherein two adjacent trenches 102 are separated by the line-type isolation wall 101.
Specifically, the substrate 100 is subjected to inductively coupled plasma etching using the line-type insulating layer 200 as a mask to form n line-type isolation walls 101 and n-1 trenches 102, and the stacked line-type insulating layer 200 and a portion of the substrate 100 form the line-type isolation wall 101. Wherein the depth H2 of the formed trench 102 is 3-5 μm, and the width D2 of the formed line-type isolation wall 101 is 3-8 μm.
Example 2
The present embodiment provides an isolation structure 11 for a high voltage light emitting device 10 and a method for manufacturing the same, where the structure of the isolation structure 11 is shown in fig. 2, and specifically includes: the semiconductor device includes a substrate 100 and a line type insulating layer 200 located on one side of the substrate 100, wherein one side of the substrate 100 is provided with n line type isolation walls 101 and n-1 trenches 102, and two adjacent trenches 102 are separated by the line type isolation wall 101.
The substrate 100 may be a sapphire substrate, a silicon carbide substrate, a diamond substrate, an aluminum nitride substrate, or a gallium nitride homogeneous substrate.
The material of the line type insulating layer 200 may be silicon dioxide or silicon nitride, the thickness of the line type insulating layer 200 may be 0.5 to 2 μm, and the width of the line type insulating layer 200 may be 3 to 8 μm.
The method for preparing the isolation structure 11 for the high voltage light emitting device 10 comprises the following steps:
s201: a substrate 100 is provided.
S202: a line type insulating layer 200 is formed on the substrate 100.
Specifically, the line type insulating layer 200 is formed on the substrate 100 by an electron beam evaporation or plasma enhanced chemical vapor deposition process. The material of the line-type insulating layer 200 may be silicon dioxide or silicon nitride, the thickness of the line-type insulating layer 200 may be 0.5 to 2 μm, and the width of the line-type insulating layer 200 may be 3 to 8 μm.
S203: the substrate 100 is etched using the line-type insulating layer 200 as a mask to form n line-type isolation walls 101 and n-1 trenches 102, thereby obtaining the isolation structure 11, wherein two adjacent trenches 102 are separated by the line-type isolation wall 101.
Specifically, the substrate 100 is etched by inductively coupled plasma using the line-type insulating layer 200 as a mask to form n line-type isolation walls 101 and n-1 trenches 102, wherein the depth of the formed trench 102 is 3 to 5 μm, and the width of the formed line-type isolation wall 101 is 3 to 8 μm.
S204: the line type insulating layer 200 is removed to expose the upper surface of the substrate 100 at the line type isolation wall 101.
Example 3
The present embodiment provides a high voltage light emitting device 10 and a method for manufacturing the same, where the structure of the high voltage light emitting device 10 is shown in fig. 3 to 4, and specifically includes: the light emitting diode comprises a substrate 100, a line type insulating layer 200, a light emitting epitaxial layer 300, n-1 insulating medium layers 400, n-1 current diffusion layers 500, n-2 interconnection metal layers 600, a first conductive type electrode 700 and a second conductive type electrode 800.
One side of the substrate 100 is provided with n line-type isolation walls 101 and n-1 trenches 102, two adjacent trenches 102 are separated by the line-type isolation wall 101, and the line-type isolation wall 101 is formed by the stacked line-type insulating layers 200 and a part of the substrate 100.
The light emitting epitaxial layer 300 includes a first semiconductor layer 301, an active layer 302, and a second semiconductor layer 303 sequentially stacked in the trench 102, wherein the light emitting epitaxial layer 300 has a mesa structure formed on the first semiconductor layer 301 facing the second semiconductor layer 303, and a portion of the upper surface of the first semiconductor layer 301 close to the line type isolation wall 101 is exposed. Wherein the thickness of the light emitting epitaxial layer 300 may be equal to the depth of the trench 102.
The first semiconductor layer 301 is an N-type semiconductor layer (e.g., N-type GaN), and the corresponding first conductive type electrode 700 is also referred to as an N-type electrode. The second semiconductor layer 303 is a P-type semiconductor layer (e.g., P-type GaN), and the corresponding second electrode is also referred to as a P-type electrode. In other embodiments, the first semiconductor layer 301 and the second semiconductor layer 303 may be single-layer or multi-layer structures of any other suitable material having different conductivity types.
The 1 st insulating medium layer 400 covers a local area of one side of the 1 st second semiconductor, which is far away from the substrate 100, and the ith insulating medium layer 400 covers a local area of one side of the ith second semiconductor, which is far away from the substrate 100, an ith line type isolation wall 101 between two adjacent light emitting epitaxial layers 300, and a local upper surface of the (i-1) th first semiconductor layer 301, which is close to one side of the ith line type isolation wall 101.
The insulating medium layer 400 may be made of silicon dioxide or silicon nitride, the thickness of the insulating medium layer 400 is 80-400 nm, and the insulating medium layer 400 has high compactness and insulativity and can prevent electric leakage between the first conductive type electrode 700 and the second conductive type electrode 800.
The 1 st current diffusion layer 500 covers a side of the 1 st insulating dielectric layer 400 away from the second semiconductor, and the ith current diffusion layer 500 covers a side of the ith insulating dielectric layer 400 away from the second semiconductor and a local area of a side of the ith second semiconductor away from the substrate 100.
The material of the current spreading layer 500 may be a transparent conductive oxide such as Indium Tin Oxide (ITO) or zinc oxide (ZnO).
The ith-1 interconnection electrode layer covers a partial upper surface of the ith-1 first semiconductor layer 301, the ith insulating medium layer 400 and one side of the ith current diffusion layer 500 away from the insulating medium layer 400, so that two adjacent light-emitting epitaxial layers 300 separated by the line-shaped isolation wall 101 are electrically connected in series.
A first conductive type electrode 700 is formed on a partial upper surface of the nth first semiconductor layer 301, and the first conductive type electrode 700 is electrically connected to the first semiconductor layer 301 through direct contact. The second conductive type electrode 800 is formed at a side of the 1 st current diffusion layer 500 facing away from the insulating medium layer 400, and the second conductive type electrode 800 is electrically connected to the current diffusion layer 500 and electrically connected to the second semiconductor layer 303 through the current diffusion layer 500. The shapes of the first conductive type electrode 700 and the second conductive type electrode 800 are not limited and may be selected according to actual needs. The first conductive type electrode 700 and the second conductive type electrode are both made of conductive materials, the materials are aluminum, copper, tungsten, molybdenum, chromium, gold, titanium, silver, nickel, palladium or any combination thereof, and the first conductive type electrode 700 and the second conductive type electrode are at least of one layer structure.
As shown in fig. 5, the manufacturing method for the high voltage light emitting device 10 includes the steps of:
s301: a substrate 100 is provided.
S302: a line type insulating layer 200 is formed on the substrate 100.
Specifically, the line type insulating layer 200 is formed on the substrate 100 by an electron beam evaporation or plasma enhanced chemical vapor deposition process. The material of the line-type insulating layer 200 may be silicon dioxide or silicon nitride, the thickness of the line-type insulating layer 200 may be 0.5 to 2 μm, and the width of the line-type insulating layer 200 may be 3 to 8 μm.
S303: the substrate 100 is etched using the line-type insulating layer 200 as a mask to form n line-type isolation walls 101 and n-1 trenches 102, thereby obtaining the isolation structure 11, wherein two adjacent trenches 102 are separated by the line-type isolation wall 101.
S304: n-1 light emitting epitaxial layers 300 are grown on n-1 trenches 102, respectively.
Specifically, a first semiconductor layer 301, an active layer 302 and a second semiconductor layer 303 are sequentially grown at a trench 102 of a substrate 100 according to a conventional Metal Organic Chemical Vapor Deposition (MOCVD) process to form a light emitting epitaxial layer 300, and two adjacent light emitting epitaxial layers 300 are separated by a line type partition wall 101.
S305: a mesa structure is formed on the first semiconductor layer 301 on the side facing the second semiconductor layer 303, and the upper surface of the portion of the first semiconductor layer 301 on the side close to the line type partition wall 101 is exposed.
Specifically, after the light-emitting epitaxial layer 300 is cleaned, photoresist coating, exposure and development are adopted, a part of the light-emitting epitaxial layer 300 area close to one side of the linear isolation wall 101 is exposed, and the second semiconductor layer 303 and the active layer 302 in the part of the light-emitting epitaxial layer 300 area are etched away, so that a part of the upper surface of the first semiconductor layer 301 is exposed; meanwhile, the upper surface of the line type partition wall 101 between two adjacent light emitting epitaxial layers 300 is etched to remove the deposition that may be deposited during the epitaxial growth in step S304.
S306: n-1 insulating dielectric layers 400 are formed.
Specifically, the photoresist on the surface of the light-emitting epitaxial layer 300 is removed, and the light-emitting epitaxial layer 300 is cleaned to obtain the substrate. And depositing an insulating medium layer 400 on the main surface of the substrate, which is far away from the substrate 100, by using a plasma enhanced chemical vapor deposition process, wherein the insulating medium layer 400 can be made of silicon dioxide or silicon nitride, and the thickness of the insulating medium layer 400 is 80-400 nm.
The insulating dielectric layer 400 has high compactness and insulation, and can prevent electric leakage between the first conductive type electrode 700 and the second conductive type electrode 800 which are prepared subsequently.
And exposing a part of the insulating dielectric layer 400 to be etched by coating photoresist, exposing and developing, and etching off the part of the insulating dielectric layer 400 to obtain n-1 insulating dielectric layers 400. The 1 st insulating medium layer 400 covers a local area of one side of the 1 st second semiconductor, which is far away from the substrate 100, and the ith insulating medium layer 400 covers a local area of one side of the ith second semiconductor, which is far away from the substrate 100, an ith line type isolation wall 101 between two adjacent light emitting epitaxial layers 300, and a local upper surface of the (i-1) th first semiconductor layer 301, which is close to one side of the ith line type isolation wall 101.
The insulating medium layer 400 covering the local area of the second semiconductor on the side away from the substrate 100 can be used as a current blocking layer; the insulating dielectric layer 400 covering the line-shaped isolation wall 101 between two adjacent light-emitting epitaxial layers 300 and the partial upper surface of the first semiconductor layer 301 close to one side of the line-shaped isolation wall 101 is used for insulating the subsequent interconnection electrode layer and the second semiconductor layer 303, so as to prevent short circuit.
S307: n-1 current diffusion layers 500 are formed.
Specifically, a current diffusion layer 500 is formed on the main surface of the substrate facing away from the substrate 100 by electron beam evaporation or sputtering. The material of the current spreading layer 500 may be a transparent conductive oxide such as Indium Tin Oxide (ITO) or zinc oxide (ZnO).
By applying photoresist, exposing, and developing, a part of the current diffusion layer 500 to be etched is exposed, and a part of the current diffusion layer 500 is etched, so that n-1 current diffusion layers 500 are obtained. The 1 st current diffusion layer 500 covers a side of the 1 st insulating dielectric layer 400 away from the second semiconductor, and the ith current diffusion layer 500 covers a side of the ith insulating dielectric layer 400 away from the second semiconductor and a local area of a side of the ith second semiconductor away from the substrate 100.
Further, after the photoresist of the current diffusion layer 500 is removed, the current diffusion layer 500 is placed in a nitrogen environment for high-temperature annealing treatment, so that the contact resistance between the current diffusion layer 500 and the second semiconductor layer 303 is reduced.
S308: n-2 interconnect metal layers 600 are formed.
An electron beam evaporation apparatus is used to deposit the interconnect metal layer 600. The ith-1 interconnection electrode layer covers the partial upper surface of the ith-1 first semiconductor layer 301, the ith insulating medium layer 400 and one side of the ith current diffusion layer 500 away from the insulating medium layer 400, so that two adjacent light-emitting epitaxial layers 300 separated by the line-shaped isolation wall 101 are electrically connected in series;
s309: and forming a second conductive type electrode 800 on the side of the 1 st current diffusion layer 500 away from the insulating medium layer 400, and forming a first conductive type electrode 700 on the partial upper surface of the nth first semiconductor layer 301 to obtain the high-voltage light-emitting device 10.
The first conductive type electrode 700 and the second conductive type electrode 800 are deposited using an electron beam evaporation apparatus.
S310: a passivation layer 900 is formed on the side of the high voltage light emitting device 10 facing away from the substrate 100.
Specifically, a passivation layer 900 is formed by a plasma enhanced chemical vapor deposition process on the side of the high voltage light emitting device 10 facing away from the substrate 100. The passivation layer 900 may be silicon dioxide, and the thickness of the passivation layer 900 is 80nm to 200 nm.
S311: the passivation layer 900 is etched such that a partial region of the first conductive type electrode 700 on a side facing away from the substrate 100, a partial region of the second conductive type electrode 800 on a side facing away from the substrate 100, and a side of the nth line type partition wall 101 facing away from the substrate 100 are exposed.
Example 4
The present embodiment provides a high voltage light emitting device 10 and a method for manufacturing the same, where the structure of the high voltage light emitting device 10 is shown in fig. 6, and specifically includes: the light emitting diode comprises a substrate 100, a light emitting epitaxial layer 300, n-1 insulating medium layers 400, n-1 current diffusion layers 500, n-2 interconnection metal layers 600, a first conductive type electrode 700 and a second conductive type electrode 800.
One side of the substrate 100 is provided with n line-type isolation walls 101 and n-1 trenches 102, and two adjacent trenches 102 are separated by the line-type isolation wall 101.
The light emitting epitaxial layer 300 includes a first semiconductor layer 301, an active layer 302, and a second semiconductor layer 303 sequentially stacked in the trench 102, wherein the light emitting epitaxial layer 300 has a mesa structure formed on the first semiconductor layer 301 facing the second semiconductor layer 303, and a portion of the upper surface of the first semiconductor layer 301 close to the line type isolation wall 101 is exposed. Wherein the thickness of the light emitting epitaxial layer 300 may be equal to the depth of the trench 102.
The first semiconductor layer 301 is an N-type semiconductor layer (e.g., N-type GaN), and the corresponding first conductive type electrode 700 is also referred to as an N-type electrode. The second semiconductor layer 303 is a P-type semiconductor layer (e.g., P-type GaN), and the corresponding second electrode is also referred to as a P-type electrode. In other embodiments, the first semiconductor layer 301 and the second semiconductor layer 303 may be single-layer or multi-layer structures of any other suitable material having different conductivity types.
The 1 st insulating medium layer 400 covers a local area of one side of the 1 st second semiconductor, which is far away from the substrate 100, and the ith insulating medium layer 400 covers a local area of one side of the ith second semiconductor, which is far away from the substrate 100, an ith line type isolation wall 101 between two adjacent light emitting epitaxial layers 300, and a local upper surface of the (i-1) th first semiconductor layer 301, which is close to one side of the ith line type isolation wall 101.
The insulating medium layer 400 may be made of silicon dioxide or silicon nitride, the thickness of the insulating medium layer 400 is 80-400 nm, and the insulating medium layer 400 has high compactness and insulativity and can prevent electric leakage between the first conductive type electrode 700 and the second conductive type electrode 800.
The 1 st current diffusion layer 500 covers a side of the 1 st insulating dielectric layer 400 away from the second semiconductor, and the ith current diffusion layer 500 covers a side of the ith insulating dielectric layer 400 away from the second semiconductor and a local area of a side of the ith second semiconductor away from the substrate 100.
The material of the current spreading layer 500 may be a transparent conductive oxide such as Indium Tin Oxide (ITO) or zinc oxide (ZnO).
The ith-1 interconnection electrode layer covers a partial upper surface of the ith-1 first semiconductor layer 301, the ith insulating medium layer 400 and one side of the ith current diffusion layer 500 away from the insulating medium layer 400, so that two adjacent light-emitting epitaxial layers 300 separated by the line-shaped isolation wall 101 are electrically connected in series.
A first conductive type electrode 700 is formed on a partial upper surface of the nth first semiconductor layer 301, and the first conductive type electrode 700 is electrically connected to the first semiconductor layer 301 through direct contact. The second conductive type electrode 800 is formed at a side of the 1 st current diffusion layer 500 facing away from the insulating medium layer 400, and the second conductive type electrode 800 is electrically connected to the current diffusion layer 500 and electrically connected to the second semiconductor layer 303 through the current diffusion layer 500. The shapes of the first conductive type electrode 700 and the second conductive type electrode 800 are not limited and may be selected according to actual needs. The first conductive type electrode 700 and the second conductive type electrode are both made of conductive materials, the materials are aluminum, copper, tungsten, molybdenum, chromium, gold, titanium, silver, nickel, palladium or any combination thereof, and the first conductive type electrode 700 and the second conductive type electrode are at least of one layer structure.
As shown in fig. 7, the manufacturing method for the high voltage light emitting device 10 includes the steps of:
s401: a substrate 100 is provided.
S402: a line type insulating layer 200 is formed on the substrate 100.
Specifically, the line type insulating layer 200 is formed on the substrate 100 by an electron beam evaporation or plasma enhanced chemical vapor deposition process. The material of the line-type insulating layer 200 may be silicon dioxide or silicon nitride, the thickness of the line-type insulating layer 200 may be 0.5 to 2 μm, and the width of the line-type insulating layer 200 may be 3 to 8 μm.
S403: the substrate 100 is etched using the line-type insulating layer 200 as a mask to form n line-type isolation walls 101 and n-1 trenches 102, wherein two adjacent trenches 102 are separated by the line-type isolation wall 101.
S404: n-1 light emitting epitaxial layers 300 are grown on n-1 trenches 102, respectively.
Specifically, a first semiconductor layer 301, an active layer 302 and a second semiconductor layer 303 are sequentially grown at a trench 102 of a substrate 100 according to a conventional Metal Organic Chemical Vapor Deposition (MOCVD) process to form a light emitting epitaxial layer 300, and two adjacent light emitting epitaxial layers 300 are separated by a line type partition wall 101.
S405: the line type insulating layer 200 is removed to obtain the isolation structure 11.
This step can effectively prevent the short circuit between the adjacent led units due to the nitride remaining on the line-type insulating layer 200.
S406: a mesa structure is formed on the first semiconductor layer 301 on the side facing the second semiconductor layer 303, and the upper surface of the portion of the first semiconductor layer 301 on the side close to the line type partition wall 101 is exposed.
Specifically, after the light-emitting epitaxial layer 300 is cleaned, photoresist coating, exposure and development are adopted, a part of the light-emitting epitaxial layer 300 area close to one side of the linear isolation wall 101 is exposed, and the second semiconductor layer 303 and the active layer 302 in the part of the light-emitting epitaxial layer 300 area are etched away, so that a part of the upper surface of the first semiconductor layer 301 is exposed; meanwhile, the upper surface of the line type partition wall 101 between two adjacent light emitting epitaxial layers 300 is etched to remove the deposition that may be deposited during the epitaxial growth in step S404.
S407: n-1 insulating dielectric layers 400 are formed.
Specifically, the photoresist on the surface of the light-emitting epitaxial layer 300 is removed, and the light-emitting epitaxial layer 300 is cleaned to obtain the substrate. And depositing an insulating medium layer 400 on the main surface of the substrate, which is far away from the substrate 100, by using a plasma enhanced chemical vapor deposition process, wherein the insulating medium layer 400 can be made of silicon dioxide or silicon nitride, and the thickness of the insulating medium layer 400 is 80-400 nm.
The insulating dielectric layer 400 has high compactness and insulation, and can prevent electric leakage between the first conductive type electrode 700 and the second conductive type electrode 800 which are prepared subsequently.
And exposing a part of the insulating dielectric layer 400 to be etched by coating photoresist, exposing and developing, and etching off the part of the insulating dielectric layer 400 to obtain n-1 insulating dielectric layers 400. The 1 st insulating medium layer 400 covers a local area of one side of the 1 st second semiconductor, which is far away from the substrate 100, and the ith insulating medium layer 400 covers a local area of one side of the ith second semiconductor, which is far away from the substrate 100, an ith line type isolation wall 101 between two adjacent light emitting epitaxial layers 300, and a local upper surface of the (i-1) th first semiconductor layer 301, which is close to one side of the ith line type isolation wall 101.
The insulating medium layer 400 covering the local area of the second semiconductor on the side away from the substrate 100 can be used as a current blocking layer; the insulating dielectric layer 400 covering the line-shaped isolation wall 101 between two adjacent light-emitting epitaxial layers 300 and the partial upper surface of the first semiconductor layer 301 close to one side of the line-shaped isolation wall 101 is used for insulating the subsequent interconnection electrode layer and the second semiconductor layer 303, so as to prevent short circuit.
S408: n-1 current diffusion layers 500 are formed.
Specifically, a current diffusion layer 500 is formed on the main surface of the substrate facing away from the substrate 100 by electron beam evaporation or sputtering. The material of the current spreading layer 500 may be a transparent conductive oxide such as Indium Tin Oxide (ITO) or zinc oxide (ZnO).
By applying photoresist, exposing, and developing, a part of the current diffusion layer 500 to be etched is exposed, and a part of the current diffusion layer 500 is etched, so that n-1 current diffusion layers 500 are obtained. The 1 st current diffusion layer 500 covers a side of the 1 st insulating dielectric layer 400 away from the second semiconductor, and the ith current diffusion layer 500 covers a side of the ith insulating dielectric layer 400 away from the second semiconductor and a local area of a side of the ith second semiconductor away from the substrate 100.
Further, after the photoresist of the current diffusion layer 500 is removed, the current diffusion layer 500 is placed in a nitrogen environment for high-temperature annealing treatment, so that the contact resistance between the current diffusion layer 500 and the second semiconductor layer 303 is reduced.
S409: n-2 interconnect metal layers 600 are formed.
An electron beam evaporation apparatus is used to deposit the interconnect metal layer 600. The ith-1 interconnection electrode layer covers the partial upper surface of the ith-1 first semiconductor layer 301, the ith insulating medium layer 400 and one side of the ith current diffusion layer 500 away from the insulating medium layer 400, so that two adjacent light-emitting epitaxial layers 300 separated by the line-shaped isolation wall 101 are electrically connected in series;
s410: and forming a second conductive type electrode 800 on the side of the 1 st current diffusion layer 500 away from the insulating medium layer 400, and forming a first conductive type electrode 700 on the partial upper surface of the nth first semiconductor layer 301 to obtain the high-voltage light-emitting device 10.
The first conductive type electrode 700 and the second conductive type electrode 800 are deposited using an electron beam evaporation apparatus.
S411: a passivation layer 900 is formed on the side of the high voltage light emitting device 10 facing away from the substrate 100.
Specifically, a passivation layer 900 is formed by a plasma enhanced chemical vapor deposition process on the side of the high voltage light emitting device 10 facing away from the substrate 100. The passivation layer 900 may be silicon dioxide, and the thickness of the passivation layer 900 is 80nm to 200 nm.
S412: the passivation layer 900 is etched such that a partial region of the first conductive type electrode 700 on a side facing away from the substrate 100, a partial region of the second conductive type electrode 800 on a side facing away from the substrate 100, and a side of the nth line type partition wall 101 facing away from the substrate 100 are exposed.
In the above embodiments, the etching process may be performed by a dry etching process or a wet etching process.
In the embodiment, i is more than or equal to 2 and less than or equal to n-1, and i and n are integers.
In the above embodiment, the line type partition walls 101 may have the same width and be arranged at equal intervals.
In the above embodiment, the depth of the trench 102 is equal to the thickness of the light emitting epitaxial layer 300.
In the above embodiment, the width of the light-emitting epitaxial layers 300 can be adjusted in the direction parallel to the line-shaped isolation walls 101 to satisfy different brightness requirements under a specified voltage, and meanwhile, different numbers of light-emitting epitaxial layers 300 can be connected in series in the direction perpendicular to the line-shaped isolation walls 101 to satisfy different voltage requirements.
Different from the prior art, the application has the following beneficial effects:
(1) deep etching of the GaN layer is cancelled, non-radiative recombination centers on the etched surface are reduced, and luminous efficiency is improved;
(2) the light-emitting epitaxial layers 300 are isolated by the linear isolation walls 101 on the substrate 100, so that the area loss of the active layer 302 caused by etching the active layer 302 is avoided, and the utilization rate of the active layer 302 is improved;
(3) the depth of the groove 102 of the isolation structure 11 is equal to the thickness of the light-emitting epitaxial layers 300, so that the metal connecting line for connecting the light-emitting epitaxial layers 300 in series is prevented from breaking due to the fact that the metal connecting line needs to penetrate through the groove 102, and meanwhile, the length of the interconnection metal layer 600 can be reduced;
(4) the width of the linear isolation wall 101 is 3-8 mu m, the distance between two adjacent light-emitting epitaxial layers 300 is greatly reduced, and the area of the active layer 302 can be increased by 5-10%;
(5) the size of the trench 102 is adjustable, so that the width of the light-emitting epitaxial layer 300 can be adjusted in a direction parallel to the line-shaped isolation wall 101 to meet the requirements of different brightness under a specified voltage, and meanwhile, different numbers of light-emitting epitaxial layers 300 can be connected in series in a direction perpendicular to the line-shaped isolation wall 101 to meet different voltage requirements.
The above description is only for the purpose of illustrating embodiments of the present application and is not intended to limit the scope of the present application, and all modifications of equivalent structures and equivalent processes, which are made by the contents of the specification and the drawings of the present application or are directly or indirectly applied to other related technical fields, are also included in the scope of the present application.
Claims (12)
1. A method for preparing an isolation structure for a high voltage light emitting device, comprising:
forming a line type insulating layer on a substrate;
and etching the substrate by taking the line type insulating layer as a mask to form n line type isolation walls and n-1 grooves to obtain the isolation structure, wherein two adjacent grooves are separated by the line type isolation walls.
2. The method of manufacturing according to claim 1, further comprising:
and removing the line-type insulating layer to expose the upper surface of the substrate at the line-type isolation wall.
3. The method of manufacturing according to claim 1, wherein the step of forming a linear type insulating layer on the substrate comprises:
forming the line-type insulating layer on the substrate by an electron beam evaporation or plasma enhanced chemical vapor deposition process;
the material of the linear insulating layer is silicon dioxide or silicon nitride, and the thickness of the linear insulating layer is 0.5-2 mu m.
4. The method according to claim 1, wherein the step of etching the substrate using the line-type insulating layer as a mask to form n line-type isolation walls and n-1 trenches comprises:
performing inductively coupled plasma etching on the substrate by taking the line-type insulating layer as a mask to form n line-type isolation walls and n-1 grooves;
the depth of the formed groove is 3-5 mu m, and the width of the formed linear isolation wall is 3-8 mu m.
5. A method of manufacturing a high voltage light emitting device, comprising:
providing an isolation structure prepared by the method of any one of claims 1 to 4;
respectively growing n-1 light-emitting epitaxial layers on the n-1 grooves, wherein the light-emitting epitaxial layers comprise a first semiconductor layer, an active layer and a second semiconductor layer which are arranged in a stacked mode, a mesa structure is formed on one side, facing the second semiconductor layer, of the first semiconductor layer, of each light-emitting epitaxial layer, and the upper surface of the part, close to one side of the line type isolation wall, of the first semiconductor layer is exposed;
forming n-1 insulating medium layers, wherein the 1 st insulating medium layer covers a local area of the 1 st second semiconductor layer at the side away from the substrate, and the ith insulating medium layer covers a local area of the ith second semiconductor layer at the side away from the substrate, an ith line-type isolation wall between every two adjacent light-emitting epitaxial layers and a local upper surface of the i-1 st first semiconductor layer at the side close to the ith line-type isolation wall;
forming n-1 current diffusion layers, wherein the 1 st current diffusion layer covers one side of the 1 st insulating medium layer, which is far away from the second semiconductor, the ith current diffusion layer covers one side of the ith insulating medium layer, which is far away from the second semiconductor, and a local area of one side of the ith second semiconductor, which is far away from the substrate;
forming n-2 interconnection metal layers, wherein the i-1 st interconnection electrode layer covers the local upper surface of the i-1 st first semiconductor layer, the i-th insulating medium layer and the i-th current diffusion layer on the side away from the insulating medium layer, so that two adjacent light-emitting epitaxial layers separated by the line-type partition wall are electrically connected in series;
forming a first conductive type electrode on one side of the 1 st current diffusion layer, which is far away from the insulating medium layer, and forming a second conductive type electrode on the local upper surface of the nth first semiconductor layer to obtain the high-voltage light-emitting device;
wherein i is more than or equal to 2 and less than or equal to n-1, and i and n are integers.
6. The method of manufacturing of claim 5, further comprising:
forming a passivation layer on one side of the high-voltage light-emitting device, which is far away from the substrate;
and etching the passivation layer to expose a local area of one side of the first conductive type electrode, which is far away from the substrate, a local area of one side of the second conductive type electrode, which is far away from the substrate, and one side of the nth linear isolation wall, which is far away from the substrate.
7. A high voltage light emitting device, comprising:
the device comprises a substrate, wherein n line-type isolation walls and n-1 grooves are arranged on one side of the substrate, and every two adjacent grooves are separated by the line-type isolation walls;
the light-emitting epitaxial layer comprises a first semiconductor layer, an active layer and a second semiconductor layer which are sequentially stacked in the groove, wherein a mesa structure is formed on one side, facing the second semiconductor layer, of the first semiconductor layer, and the upper surface of the part, close to one side of the line-type isolation wall, of the first semiconductor layer is exposed;
n-1 insulating medium layers, wherein the 1 st insulating medium layer covers a local area of the 1 st second semiconductor layer at the side away from the substrate, and the ith insulating medium layer covers a local area of the ith second semiconductor layer at the side away from the substrate, an ith line-type isolation wall between two adjacent light-emitting epitaxial layers and a local upper surface of the i-1 st first semiconductor layer at the side close to the ith line-type isolation wall;
n-1 current diffusion layers, wherein the 1 st current diffusion layer covers one side of the 1 st insulating medium layer, which is far away from the second semiconductor, the ith current diffusion layer covers one side of the ith insulating medium layer, which is far away from the second semiconductor, and a local area of one side of the ith second semiconductor, which is far away from the substrate;
n-2 interconnection metal layers, wherein the i-1 st interconnection electrode layer covers the local upper surface of the i-1 st first semiconductor layer, the i-th insulating medium layer and the i-th current diffusion layer on the side away from the insulating medium layer, so that two adjacent light-emitting epitaxial layers separated by the line-type partition wall are electrically connected in series;
a first conductive type electrode formed on a partial upper surface of the nth first semiconductor layer;
the second conductive type electrode is formed on one side, away from the insulating medium layer, of the 1 st current diffusion layer;
wherein i is more than or equal to 2 and less than or equal to n-1, and i and n are integers.
8. The high voltage light emitting device of claim 7, further comprising:
and the line-type insulating layer is arranged on the substrate, and the line-type insulating layer and part of the substrate which are arranged in a stacked mode form the line-type isolation wall.
9. The high voltage light emitting device according to claim 7 or 8, further comprising:
and the passivation layer covers one side of the high-voltage light-emitting device, which is far away from the substrate, and exposes a local area of one side of the first conductive type electrode, a local area of one side of the second conductive type electrode, which is far away from the substrate, and one side of the nth linear isolation wall, which is far away from the substrate.
10. The high voltage light emitting device of claim 9,
the depth of the groove is 3-5 mu m;
the width of the linear isolation wall is 3-8 mu m;
the thickness of the passivation layer is 80 nm-200 nm.
11. The high voltage light emitting device of claim 7,
the linear isolation walls are equal in width and are arranged at equal intervals.
12. The high voltage light emitting device of claim 7,
the depth of the groove is equal to the thickness of the light-emitting epitaxial layer.
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