CN117374103A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

Info

Publication number
CN117374103A
CN117374103A CN202311667322.7A CN202311667322A CN117374103A CN 117374103 A CN117374103 A CN 117374103A CN 202311667322 A CN202311667322 A CN 202311667322A CN 117374103 A CN117374103 A CN 117374103A
Authority
CN
China
Prior art keywords
semiconductor layer
gate electrode
nitride semiconductor
layer
nitride
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN202311667322.7A
Other languages
Chinese (zh)
Other versions
CN117374103B (en
Inventor
何清源
郝荣辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Innoscience Suzhou Semiconductor Co Ltd
Original Assignee
Innoscience Suzhou Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Innoscience Suzhou Semiconductor Co Ltd filed Critical Innoscience Suzhou Semiconductor Co Ltd
Priority to CN202311667322.7A priority Critical patent/CN117374103B/en
Publication of CN117374103A publication Critical patent/CN117374103A/en
Application granted granted Critical
Publication of CN117374103B publication Critical patent/CN117374103B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H01L29/475—Schottky barrier electrodes on AIII-BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes
    • H01L29/452—Ohmic electrodes on AIII-BV compounds
    • H01L29/454—Ohmic electrodes on AIII-BV compounds on thin film AIII-BV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
    • H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

The present disclosure provides a semiconductor device and a method of manufacturing the same. The semiconductor device includes: a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer; a third nitride semiconductor layer doped with impurities and provided on the second nitride semiconductor layer; a gate electrode disposed on the third nitride semiconductor layer; a first semiconductor layer disposed on the third nitride semiconductor layer; and a via electrically connected to the gate electrode, wherein the gate electrode and the third nitride semiconductor layer define a schottky contact, and the first semiconductor layer and the via define an ohmic contact.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method of manufacturing the same.
Background
Components comprising direct bandgap semiconductors, such as semiconductor components comprising group III-V materials or group III-V compounds (class: group III-V compounds), may operate or work under a variety of conditions or in a variety of environments (e.g., at different voltages and frequencies).
The semiconductor components may include heterojunction bipolar transistors (HBTs, heterojunction bipolar transistor), heterojunction field effect transistors (HFETs, heterojunction field effect transistor), high-electron-mobility transistor, modulation-doped field effect transistors (MODFETs), and the like.
Taking a high electron mobility transistor as an example, it can be divided into: current injection PGAN HEMTs (power gallium nitride high electron mobility transistors) and voltage driven PGAN HEMTs (power gallium nitride high electron mobility transistors).
In the current injection PGAN HEMT, a current is injected into a Gate (Gate) region of a transistor, and by changing the magnitude of the injected current, the open/close state of a conductive path between the Gate and the source can be controlled. When the injected current reaches a certain threshold, the transistor is in an on state, allowing current to flow. Conversely, when the injected current is below the threshold, the transistor is in an off state, allowing no current to pass.
The voltage-driven PGAN HEMT is a transistor structure that realizes a switching function by controlling the voltage between the gate and the source. In this structure, the voltage between the gate and the source is adjusted, thereby controlling the open and closed states of the conductive path. When the applied voltage reaches a certain threshold value, the transistor is turned on; when the voltage is below the threshold, the transistor is turned off.
But it has the following disadvantages: the current injection type PGAN HEMT adopts a grid design of ohmic contact, so that the grid leakage is relatively large while the larger saturation current is realized, the efficiency of a power transistor is reduced due to the existence of the grid leakage, and the problems of heat effect or unstable current and the like can be caused.
Voltage driven PGAN HEMTs typically employ a gate design with schottky contacts, which are metal-semiconductor contacts with small gate leakage characteristics. However, since PGAN (GaN material) is in a floating state, a problem of trapping effect at an interface may be caused, affecting the overall performance of the transistor.
Disclosure of Invention
An object of the present disclosure is to provide a semiconductor device and a method of manufacturing the same for solving a technical problem that current injection type PGAN HEMT and voltage driving type PGAN HEMT affect performance of a transistor due to respective gate leakage and trap effects, etc.
In order to achieve the above object, the present disclosure provides the following technical solutions:
in a first aspect, embodiments of the present disclosure provide a semiconductor device including:
a substrate;
a first nitride semiconductor layer disposed on the substrate;
a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer;
a third nitride semiconductor layer doped with impurities and provided on the second nitride semiconductor layer;
a gate electrode disposed on the third nitride semiconductor layer;
a first semiconductor layer disposed on the third nitride semiconductor layer; a kind of electronic device with high-pressure air-conditioning system
A via electrically connected to the gate electrode;
wherein the gate electrode and the third nitride semiconductor layer define a schottky contact and the first semiconductor layer and the via define an ohmic contact.
Optionally, the method further comprises:
and a second semiconductor layer which is provided between the first semiconductor layer and the third nitride semiconductor layer and has a band gap larger than that of the first semiconductor layer.
Optionally, the second semiconductor layer is doped with impurities.
Optionally, the gate electrode is adjacent to the first semiconductor layer and the second semiconductor layer.
Optionally, the first semiconductor layer is doped with impurities.
Optionally, the gate electrode has a first portion and a second portion, the first portion being spaced apart from the second portion along a first direction.
Optionally, the first semiconductor layer is located between the first portion and the second portion of the gate electrode.
Optionally, the method further comprises:
a second semiconductor layer having a band gap greater than a band gap of the first semiconductor layer, wherein the second semiconductor layer is located between the first portion and the second portion of the gate electrode.
Optionally, the gate electrode has a third portion, the first portion being spaced apart from the third portion along a second direction different from the first direction.
Optionally, the first semiconductor layer is located between the first portion and the third portion of the gate electrode.
Optionally, the method further comprises:
a second semiconductor layer having a band gap greater than a band gap of the first semiconductor layer, wherein the second semiconductor layer is located between the first portion and the third portion of the gate electrode.
Optionally, an upper surface of the first semiconductor layer is coplanar with an upper surface of the gate electrode.
Optionally, an upper surface of the first semiconductor layer is not coplanar with an upper surface of the gate electrode.
Optionally, the via hole penetrates a portion of the gate electrode.
Alternatively, the first semiconductor layer has a plurality of portions spaced apart from each other, the gate electrode has a plurality of portions spaced apart from each other, and the plurality of portions of the first semiconductor layer and the plurality of portions of the gate electrode are staggered with each other.
In a second aspect, embodiments of the present disclosure provide a method of manufacturing a semiconductor device, including:
providing a substrate;
forming a first nitride semiconductor layer on the substrate;
forming a second nitride semiconductor layer on the first nitride semiconductor layer, wherein the band gap of the second nitride semiconductor layer is larger than that of the first nitride semiconductor layer;
forming a third nitride semiconductor layer on the second nitride semiconductor layer, the third nitride semiconductor layer being doped with impurities;
forming a gate electrode on the third nitride semiconductor layer;
forming a first semiconductor layer on the third nitride semiconductor layer; a kind of electronic device with high-pressure air-conditioning system
Forming a via electrically connected to the gate electrode;
wherein the gate electrode and the third nitride semiconductor layer define a schottky contact and the first semiconductor layer and the via define an ohmic contact.
Optionally, the method further comprises:
forming a second semiconductor layer on the third nitride semiconductor layer, wherein the first semiconductor layer is formed on the second semiconductor layer, and the band gap of the second semiconductor layer is larger than that of the first semiconductor layer.
Optionally, the second semiconductor layer is doped with impurities.
Optionally, the first semiconductor layer is doped with impurities.
Optionally, forming the gate electrode includes:
forming an electrode material layer on the third nitride semiconductor layer; a kind of electronic device with high-pressure air-conditioning system
A portion of the electrode material layer is removed to form the gate electrode having a first portion and a second portion spaced apart from the first portion.
In a third aspect, embodiments of the present disclosure provide a semiconductor device including:
a substrate;
a first nitride semiconductor layer disposed on the substrate;
a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer;
a third nitride semiconductor layer doped with impurities and provided on the second nitride semiconductor layer;
a gate electrode disposed on the third nitride semiconductor layer;
a carrier-providing layer adjoining the gate electrode, wherein the carrier-providing layer is configured to generate a first carrier to neutralize a second carrier located within a trap of the gate electrode.
Optionally, the method further comprises:
a barrier layer disposed between the third nitride semiconductor layer and the carrier providing layer, wherein a band gap of the barrier layer is larger than a band gap of the carrier providing layer.
Optionally, the barrier layer is doped with impurities.
Optionally, the carrier-providing layer is doped with impurities.
Optionally, the gate electrode has a first portion and a second portion, the first portion being separated from the second portion by the carrier-providing layer.
Therefore, the gate electrode and the third nitride semiconductor layer form Schottky contact, current leakage between the gate and other areas can be reduced, performance and efficiency of the device are improved, the first semiconductor layer and the through hole form ohmic contact, low-impedance connection can be achieved, smooth flow of high current is ensured, and performance, efficiency and reliability of the device can be improved by combining the gate electrode with the third nitride semiconductor layer.
In addition, when a positive voltage is applied to the gate electrode, holes in the first semiconductor layer are injected downward, but due to the existence of the second semiconductor layer barrier, holes are accumulated at the interface of the first semiconductor layer and the second semiconductor layer, and the accumulated holes are neutralized with trap electrons at the schottky interface, thereby playing a role in improving interface states.
Drawings
The aspects of the disclosure may be readily understood from the following detailed description when read in conjunction with the accompanying drawings. It is contemplated that various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.
Fig. 1 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;
fig. 2 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;
fig. 3 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;
fig. 4 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;
fig. 5 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure;
FIG. 6 is a schematic diagram of interface states according to some embodiments of the present disclosure;
fig. 7 is a schematic diagram of a method for fabricating a semiconductor device according to some embodiments of the present disclosure;
fig. 8 is a schematic diagram of a method for fabricating a semiconductor device according to some embodiments of the present disclosure;
common reference numerals are used throughout the drawings and the detailed description to refer to the same or like components; the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. In this disclosure, references to forming or disposing a first feature on or over a second feature may include embodiments in which the first and second features are formed or disposed in direct contact, and may also include embodiments in which additional features may be formed or disposed between the first and second features such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself limit the relationship between the various embodiments and/or configurations discussed.
Embodiments of the present disclosure are discussed in detail below. However, it is to be understood that this disclosure provides many applicable concepts that can be embodied in a wide variety of specific contexts. The particular embodiments discussed are illustrative only and are not limiting of the scope of the present disclosure.
Fig. 1 is a cross-sectional view of a semiconductor device according to some embodiments of the present disclosure, and the lower left corner is a coordinate system schematic, as shown in fig. 1: the semiconductor device 1a may include a substrate 12, a first nitride semiconductor layer 14, a second nitride semiconductor layer 16, a third nitride semiconductor layer 18, a gate electrode 20, a first semiconductor layer 40, and a via hole 50.
Wherein the substrate 12 may comprise, but is not limited to, silicon (Si), doped Si, silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs), or other semiconductor material. Substrate 12 may include, but is not limited to, sapphire, silicon-on-insulator (SOI, silicon on insulator), or other suitable materials.
The first nitride semiconductor layer 14 may be disposed on the substrate 12. The first nitride semiconductor layer 14 may include a group III-V layer. The first nitride semiconductor layer 14 may include, but is not limited to, group III nitrides, such as the compound InaAlbGa1-a-bN, where a+b+.ltoreq.1. The group III nitride further includes, but is not limited to, for example, the compound AlaGa (1-a) N, where a+.1. The first nitride semiconductor layer 14 may include a gallium nitride (GaN) layer. The energy gap of GaN is about 3.4. 3.4 eV.
The second nitride semiconductor layer 16 may be disposed on the first nitride semiconductor layer 14 and has a band gap greater than that of the first nitride semiconductor layer 14. The second nitride semiconductor layer 16 may include a group III-V layer. The second nitride semiconductor layer 16 may include, but is not limited to, group III nitrides, such as the compound InaAlbGa1-a-bN, where a+b+.ltoreq.1. The group III nitride may further include, but is not limited to, for example, the compound AlaGa (1-a) N, where a+.1. The energy gap of the second nitride semiconductor layer 16 may be larger than that of the first nitride semiconductor layer 14. The second nitride semiconductor layer 16 may include an aluminum gallium nitride (AlGaN) layer. The energy gap of AlGaN is about 4.0. 4.0 eV.
A heterojunction may be formed between the second nitride semiconductor layer 16 and the first nitride semiconductor layer 14, and polarization of the heterojunction forms a two-dimensional electron gas (two-dimensional electron gas,2 DEG) region in the first nitride semiconductor layer 14.
The third nitride semiconductor layer 18 may be disposed on the second nitride semiconductor layer 16. The third nitride semiconductor layer 18 may be in direct contact with the second nitride semiconductor layer 16. The third nitride semiconductor layer 18 may be disposed between the gate electrode 20 and the second nitride semiconductor layer 16. The upper surface of the third nitride semiconductor layer may be denoted as upper surface 18s1, and third nitride semiconductor layer 18 is doped with impurities. The third nitride semiconductor layer 18 may contain p-type impurities. The third nitride semiconductor layer 18 may include a p-type doped GaN layer, a p-type doped AlGaN layer, a p-type doped AlN layer, or other suitable III-V layer. The p-type impurities may include magnesium (Mg), beryllium (Be), zinc (Zn), and cadmium (Cd). The third nitride semiconductor layer 18 may be configured to control the concentration of 2DEG in the first nitride semiconductor layer 14. The third nitride semiconductor layer 18 may be used to deplete the 2DEG directly under the third nitride semiconductor layer 18.
The gate electrode 20 may be disposed on the third nitride semiconductor layer 18. The gate electrode 20 may include a metal. The gate electrode 20 may comprise titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), lead (Pb), molybdenum (Mo) and compounds thereof (such as, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), other conductive nitrides or conductive oxides), metal alloys (such as aluminum copper alloy (Al-Cu)), or other suitable materials. In a specific implementation, the gate electrode 20 defines a schottky contact with the third nitride semiconductor layer 18, wherein the gate electrode 20 may be a schottky gate.
The Schottky contact (Schottky contact) refers to a contact between a metal and a semiconductor. In schottky contacts, a barrier is formed between a metal and a semiconductor, which can control the flow of electrons, thereby achieving rectification and modulation of current. Schottky contacts are formed by the energy band difference between metals and semiconductors. When the metal contacts the semiconductor, a potential barrier is formed at the interface, and the current can only conduct unidirectionally (rectify) due to the potential barrier formed by the Schottky contact, so that the switching speed is high and the reverse leakage current is low.
The first semiconductor layer 40 is disposed on the third nitride semiconductor layer 18, the first semiconductor layer 40 is adjacent to the gate electrode 20, and the first semiconductor layer 40 is doped with impurities, which are commonly used to modify the conductivity of the semiconductor. The first semiconductor layer 40 may be PGAN.
In the semiconductor device, the gate electrode 20 is generally used to control the flow of current in the semiconductor material. The gate electrode 20 changes the charge distribution in the semiconductor material by an applied voltage signal, thereby regulating the transmission of current. The first semiconductor layer 40 is a layer of semiconductor material in direct contact with the gate electrode 20. In the specific semiconductor device 1a, the gate electrode 20 is located above the third nitride semiconductor layer 18 and forms a schottky contact with the third nitride semiconductor layer 18. And the gate electrode 20 can control or regulate the charge distribution and current transmission in the first semiconductor layer 40 by contact with the first semiconductor layer 40, realizing a current control function for the entire semiconductor device 1 a.
The semiconductor device 1a further includes: the through hole 50, the through hole 50 is a hole structure penetrating the gate electrode 20, and is an electrically connected channel. The via 50 passes through a region of the gate electrode 20 for establishing electrical connection with the gate electrode 20.
Thereby, ohmic contact is formed between the first semiconductor layer 40 and the via hole 50. Ohmic contact refers to a low-resistance contact mode existing between two materials, and can effectively transfer current. The ohmic contact establishes a good electrical connection between the first semiconductor layer 40 and the via 50 so that current can flow freely between them for low resistance, efficient energy transfer and signal conduction. And the gate electrode 20 and the third nitride semiconductor layer 18 define schottky contacts, so that current can be conducted (rectified) only in one direction due to a potential barrier formed by the schottky contacts, with a high switching speed and a low reverse leakage current.
In one possible implementation, as shown in fig. 1, the upper surface 40s1 of the first semiconductor layer 40 is coplanar with the upper surface 20s1 of the gate electrode 20.
In one possible implementation, as shown in fig. 2, the upper surface 40s1 of the first semiconductor layer 40 is not coplanar with the upper surface 20s1 of the gate electrode 20.
In one possible implementation, as shown in fig. 2, via 50 is electrically connected to gate electrode 20, with via 50 extending through a portion of gate electrode 20.
In one possible implementation, as shown in fig. 1, 2, and 3, the gate electrode 20 has a first portion 201 and a second portion 202, the first portion 201 being spaced apart from the second portion 202 along a first direction (X-axis). The first semiconductor layer 40 is adjacent to the gate electrode 20 and may be characterized in that the first semiconductor layer 40 is located between the first portion 201 and the second portion 202 of the gate electrode 20.
Note that the gate electrode 20 has a first portion 201 and a second portion 202, and is spaced apart in the X-axis direction, which means that the gate electrode 20 is divided into two different regions, which may be referred to as the first portion 201 and the second portion 202, respectively. An alternative implementation of the first semiconductor layer 40 in spatial contact abutment with the gate electrode 20 is: the first semiconductor layer 40 is located between the first portion 201 and the second portion 202 of the gate electrode 20.
It will be appreciated that by dividing the gate electrode 20 into different regions, more precise control of the current flow may be achieved. For example: the first portion 201 is responsible for controlling the switching state or regulating the threshold of current flow, while the second portion 202 is used to provide higher current handling capability. The magnitude and direction of the current can be flexibly adjusted through the two portions of the gate electrode 20 to meet the requirements of a particular device.
In one possible implementation, as shown in fig. 1, 2, and 3, the semiconductor device 1a further includes a second semiconductor layer 30 disposed between the first semiconductor layer 40 and the third nitride semiconductor layer 18, and having a band gap greater than that of the first semiconductor layer 40. The second semiconductor layer 30 adjoins the gate electrode 20. And, optionally, the second semiconductor layer 30 is doped with an impurity (e.g., P-type or N-type impurity), and the second semiconductor layer 30 may be P-AlGaN.
The second semiconductor layer 30 is provided between the first semiconductor layer 40 and the third nitride semiconductor layer 18, that is, the second semiconductor layer 30 and the first semiconductor layer 40 are stacked in this order in a direction away from the third nitride semiconductor layer 18.
And further in combination with the possible implementation of the foregoing, that is, in an implementation in which the gate electrode 20 has the first portion 201 and the second portion 202, and the first portion 201 is spaced from the second portion 202 along the first direction (X-axis), the abutment of the second semiconductor layer 30 with the gate electrode 20 may be expressed as: the second semiconductor layer 30 is located between the first portion 201 and the second portion 202 of the gate electrode 20. And in the space formed by the first portion 201 and the second portion 202 of the gate electrode 20, the first semiconductor layer 40 is located above, i.e., in a direction away from the third nitride semiconductor layer 18, and the second semiconductor layer 30 is located below, i.e., in a direction close to the third nitride semiconductor layer 18.
In one possible implementation, as shown in fig. 4, the gate electrode 20 further includes: third portion 203, first portion 201 is spaced from third portion 203 along a second direction (Y-axis) different from the first direction. And the first semiconductor layer 40 is located between the first portion 201 and the third portion 203 of the gate electrode 20. The second semiconductor layer 30 is located between the first portion 201 and the third portion 203 of the gate electrode 20.
In this design, the gate electrode 20 is subdivided into three sections: a first portion 201, a second portion 202, and a third portion 203. The first portion 201 and the third portion 203 are spaced apart in the Y-axis direction, and the first portion 201 and the second portion 202 are spaced apart or opposite to each other in the X-axis direction, and the second portion 202 and the third portion 203 are also spaced apart in the Y-axis direction, and the first semiconductor layer 40 is also located between the first portion 201 and the third portion 203 of the gate electrode 20 and between the third portion 203 and the second portion 202 on the basis of the structure. Thus, the area of ohmic contact (the first semiconductor layer 40 and the gate electrode 20, and the second semiconductor layer 30 and the gate electrode 20) can be increased by changing the vertically continuous gate electrode 20 to be vertically split, so as to further reduce the interface state.
In one possible implementation, as shown in fig. 5, the first semiconductor layer 40 has a plurality of portions 411 spaced apart from each other, the gate electrode 20 has a plurality of portions 211 spaced apart from each other, and the plurality of portions of the first semiconductor layer 40 and the plurality of portions of the gate electrode 20 are staggered with each other. Thus, the gate electrode 20 which is laterally continuous can be changed to be laterally split, the gate length can be effectively reduced, the high frequency characteristic of the device can be improved, the gate resistance can be reduced, and the forward saturation current can be improved.
In one possible implementation, the semiconductor device 1a further includes: the first electrode 61, the second electrode 62, and the gate electrode 20 may be disposed between the first electrode 61 and the second electrode 62.
In one possible implementation, as shown in fig. 1, the semiconductor device 1a further includes: the packaging layer 70, the packaging layer 70 refers to an external protection layer for packaging other film layers, and the packaging layer 70 has the main functions of providing mechanical protection, electrical connection, heat dissipation and the like.
In summary, the structure of the semiconductor device 1a described in the present application can be summarized as follows: a substrate 12 providing the basic support for the entire device, a first nitride semiconductor layer 14, a second nitride semiconductor layer 16, a third nitride semiconductor layer 18), each stacked on top of the previous layer. Wherein the band gap of the second nitride semiconductor layer 16 is larger than that of the first nitride semiconductor layer 14. And the third nitride semiconductor layer 18 is doped with impurities, the electrical properties of which are adjusted. The gate electrode 20 is located on the third nitride semiconductor layer 18 and forms a schottky contact with the third nitride semiconductor layer 18. The gate electrode 20 has a complex geometry including spaced apart first 201, second 202 and third 203 portions (as shown in fig. 4) that are spaced apart in different directions.
The first semiconductor layer 40 is located on the third nitride semiconductor layer 18 and defines an ohmic contact with a via 50, the via 50 extending through a portion of the gate electrode 20.
In addition, in an alternative design, the first semiconductor layer 40 may be divided into a plurality of portions, which are staggered with portions of the gate electrode 20.
In an alternative embodiment, the second semiconductor layer 30 is arranged between the first semiconductor layer 40 and the third nitride semiconductor layer 18, and has a band gap that is greater than the band gap of the first semiconductor layer 40. This layer may also be doped with impurities and in some versions be located between certain portions of the gate electrode 20.
While with respect to the surfaces of the first semiconductor layer 40 and the gate electrode 20, both may be coplanar, or the upper surfaces of both may not be coplanar.
In summary, when a positive voltage is applied to the gate electrode 20, holes in the first semiconductor layer 40 are injected downward, but due to the existence of the barrier of the second semiconductor layer 30, holes are accumulated at the interface between the first semiconductor layer 40 and the second semiconductor layer 30, and these accumulated holes are neutralized with trap electrons at the schottky interface, thereby improving the interface state.
The disclosed embodiment also provides a semiconductor device 1a including:
a substrate 12;
a first nitride semiconductor layer 14 provided on the substrate 12;
a second nitride semiconductor layer 16 provided on the first nitride semiconductor layer 14 and having a band gap larger than that of the first nitride semiconductor layer 14;
a third nitride semiconductor layer 18 doped with impurities and provided on the second nitride semiconductor layer 16;
a gate electrode 20 disposed on the third nitride semiconductor layer 18;
a carrier providing layer adjacent to the gate electrode 20, wherein the carrier providing layer is configured to generate a first carrier to neutralize a second carrier located within the traps of the gate electrode 20.
In one possible implementation, the method further includes:
a barrier layer provided between the third nitride semiconductor layer 18 and the carrier providing layer, wherein the band gap of the barrier layer is larger than that of the carrier providing layer. The barrier layer includes the second semiconductor layer 30, and the carrier providing layer includes the first semiconductor layer 40.
In one possible implementation, the barrier layer is doped with impurities.
In one possible implementation, the carrier-providing layer is doped with impurities.
In one possible implementation, the gate electrode 20 has a first portion 201 and a second portion 202, the first portion 201 being separated from the second portion 202 by a carrier providing layer. It should be noted that the carrier providing layer is adjacent to the gate electrode 20, and the carrier providing layer is configured to generate a first carrier to neutralize a second carrier located in the trap of the gate electrode 20.
It should be noted that the first semiconductor layer 40 is disposed between two portions of the gate electrode 20, so that better current control and performance optimization can be achieved. When a positive voltage V1 is applied to the gate electrode 20, holes in the first semiconductor layer 40 are injected downward, and since the band gap of the second semiconductor layer 30 is larger than that of the first semiconductor layer 40, a potential barrier is generated, and the existence of the potential barrier plays a key role in the movement of holes. Holes accumulate at the interface of the first semiconductor layer 40 and the second semiconductor layer 30, and these accumulated holes are neutralized with the trapped electrons at the schottky interface, thereby functioning to improve the interface state (as shown in fig. 6).
Specifically, when a positive voltage is applied to the gate electrode 20, an electric field over the third nitride semiconductor layer 18 causes holes in the first semiconductor layer 40 to be injected downward into the third nitride semiconductor layer 18. However, since the band gap of the second semiconductor layer 30 is larger than that of the first semiconductor layer 40, it creates a potential barrier, which means that holes are blocked at the second semiconductor layer 30 when attempting to migrate toward the third nitride semiconductor layer 18 deeper. And holes accumulate at the interface of the first semiconductor layer 40 and the second semiconductor layer 30 due to the existence of this potential barrier, forming a region with a higher hole concentration. When there is a schottky contact between the semiconductor and the metal (e.g., gate electrode 20), the contact interface typically has some electron states, known as trap states. These trap states are due to the different band structures that exist between the semiconductor and the metal, resulting in unfilled electron states at the interface between them. Due to the accumulation of holes between the first semiconductor layer 40 and the second semiconductor layer 30, the holes may recombine with trapped electrons of the schottky interface, thereby neutralizing the interface state, which may help reduce the interface state density between the semiconductor and the metal, thereby improving device performance, such as reducing leakage current, improving switching speed, and the like.
The embodiment of the disclosure further provides a method for manufacturing a transistor structure, which is used for manufacturing the transistor structure provided in the above embodiment, as shown in fig. 7 and 8, and the manufacturing method includes:
step S1: providing a substrate 12;
step S2: forming a first nitride semiconductor layer 14 on the substrate 12;
step S3: forming a second nitride semiconductor layer 16 on the first nitride semiconductor layer 14, and having a band gap larger than that of the first nitride semiconductor layer 14;
step S4: forming a third nitride semiconductor layer 18 on the second nitride semiconductor layer 16, the third nitride semiconductor layer 18 being doped with impurities;
step S5: forming a gate electrode 20 on the third nitride semiconductor layer 18;
step S6: forming a first semiconductor layer 40 on the third nitride semiconductor layer 18;
step S7: forming a via 50 electrically connected to the gate electrode 20;
wherein the gate electrode 20 defines a schottky contact with the third nitride semiconductor layer 18 and the first semiconductor layer 40 defines an ohmic contact with the via 50.
In a possible implementation manner, as shown in fig. 8, the method for manufacturing the transistor structure further includes: the second semiconductor layer 30 is formed on the third nitride semiconductor layer 18, wherein the first semiconductor layer 40 is formed on the second semiconductor layer 30, and the band gap of the second semiconductor layer 30 is larger than that of the first semiconductor layer 40.
In one possible implementation, the second semiconductor layer 30 is doped with impurities. Wherein the first semiconductor layer 40 is doped with impurities.
In one possible implementation, the step of fabricating the gate electrode 20 specifically includes: forming an electrode material layer on the third nitride semiconductor layer 18; and removing a portion of the electrode material layer to form the gate electrode 20 having a first portion 201 and a second portion 202 spaced apart from the first portion 201.
Note that the first nitride semiconductor layer 14, the second nitride semiconductor layer 16, the third nitride semiconductor layer 18, and the gate electrode 20 may be formed by chemical vapor deposition (chemical vapor deposition, CVD), physical vapor deposition (physical vapor deposition, PVD), atomic layer deposition (atomic layer deposition, ALD), or other suitable techniques. The patterns (patterns) of the first nitride semiconductor layer 14, the second nitride semiconductor layer 16, the third nitride semiconductor layer 18, and the gate electrode 20 may be formed through a photolithography (photo lithography) process, an etching process, and other suitable processes.
Thus, when a positive voltage is applied to the gate electrode 20, an electric field over the third nitride semiconductor layer 18 causes holes in the first semiconductor layer 40 to be injected downward into the third nitride semiconductor layer 18. However, since the band gap of the second semiconductor layer 30 is larger than that of the first semiconductor layer 40, it creates a potential barrier, which means that holes are blocked at the second semiconductor layer 30 when attempting to migrate toward the third nitride semiconductor layer 18 deeper. And holes accumulate at the interface of the first semiconductor layer 40 and the second semiconductor layer 30 due to the existence of this potential barrier, forming a region with a higher hole concentration. When there is a schottky contact between the semiconductor and the metal (e.g., gate electrode 20), the contact interface typically has some electron states, known as trap states. These trap states are due to the different band structures that exist between the semiconductor and the metal, resulting in unfilled electron states at the interface between them. Due to the accumulation of holes between the first semiconductor layer 40 and the second semiconductor layer 30, the holes may recombine with trapped electrons of the schottky interface, thereby neutralizing the interface state, which may help reduce the interface state density between the semiconductor and the metal, thereby improving device performance, such as reducing leakage current, improving switching speed, and the like.
Unless otherwise specified, spatial descriptions as "on …", "under …", "upward", "left", "right", "downward", "top", "bottom", "vertical", "horizontal", "side", "above", "below", "upper", "above …", "below …" are indicated relative to the orientation shown in the drawings. It should be understood that the spatial descriptions used herein are for illustration purposes only, and that the actual implementation of the structures described herein may be spatially arranged in any orientation or manner, provided that the advantages of the embodiments of the present disclosure do not deviate from such an arrangement.
As used herein, the term "vertical" is used to refer to both upward and downward directions, while the term "horizontal" refers to a direction transverse to the vertical direction.
As used herein, the terms "about," "substantially," "generally," and "about" are used to describe and explain minor variations. When used in connection with an event or circumstance, the term can refer to instances where the event or circumstance occurs precisely and instances where it occurs to the close approximation. For example, when used in connection with a numerical value, the term can refer to a range of variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, a first value may be considered "substantially" the same as or equal to a second value if the first value is within less than or equal to ±10% of the second value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. For example, "substantially" perpendicular may refer to a range of angular variation of less than or equal to ±10° relative to 90 °, such as less than or equal to ±5°, less than or equal to ±4°, less than or equal to ±3°, less than or equal to ±2°, less than or equal to ±1°, less than or equal to ±0.5°, less than or equal to ±0.1° or less than or equal to ±0.05°.
Two surfaces may be considered to be coplanar or substantially coplanar if the displacement between the two surfaces is no more than 5 μm, no more than 2 μm, no more than 1 μm, or no more than 0.5 μm. A surface may be considered substantially flat if the displacement between the highest point and the lowest point of the surface is not more than 5 μm, not more than 2 μm, not more than 1 μm or not more than 0.5 μm.
As used herein, the singular terms "a" and "an" may include plural referents unless the context clearly dictates otherwise.
As used herein, the terms "conductive", "conductive (electrically conductive)" and "conductivity" refer to the ability to carry electrical current. Conductive materials generally indicate those materials that exhibit little or no opposition to the flow of current. One measure of conductivity is Siemens per meter (S/m). Typically, the conductive material is one having a conductivity greater than about 104S/m (e.g., at least 105S/m or at least 106S/m). The conductivity of a material can sometimes vary with temperature. Unless specified otherwise, the conductivity of the material is measured at room temperature.
Further, amounts, ratios, and other numerical values are sometimes presented herein in a range format. It is to be understood that such range format is used for convenience and brevity and should be interpreted flexibly to include not only the numerical values explicitly recited as the limits of the range, but also to include all the individual numerical values or sub-ranges encompassed within that range as if each numerical value and sub-range is explicitly recited.
While the present disclosure has been depicted and described with reference to particular embodiments thereof, such depicted and described are not meant to be limiting. It will be understood by those skilled in the art that various changes may be made and equivalents substituted without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a distinction between process reproduction and actual equipment in the present disclosure due to manufacturing processes and tolerances. Other embodiments of the present disclosure are possible that are not specifically described. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations being performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of operations is not a limitation of the present disclosure.

Claims (25)

1. A semiconductor device, comprising:
a substrate;
a first nitride semiconductor layer disposed on the substrate;
a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer;
a third nitride semiconductor layer doped with impurities and provided on the second nitride semiconductor layer;
a gate electrode disposed on the third nitride semiconductor layer;
a first semiconductor layer disposed on the third nitride semiconductor layer; a kind of electronic device with high-pressure air-conditioning system
A via electrically connected to the gate electrode;
wherein the gate electrode and the third nitride semiconductor layer define a schottky contact and the first semiconductor layer and the via define an ohmic contact.
2. The semiconductor device according to claim 1, further comprising:
and a second semiconductor layer which is provided between the first semiconductor layer and the third nitride semiconductor layer and has a band gap larger than that of the first semiconductor layer.
3. The semiconductor device according to claim 2, wherein the second semiconductor layer is doped with an impurity.
4. The semiconductor device according to claim 2, wherein the gate electrode is adjacent to the first semiconductor layer and the second semiconductor layer.
5. The semiconductor device according to claim 1, wherein the first semiconductor layer is doped with an impurity.
6. The semiconductor device according to claim 1, wherein the gate electrode has a first portion and a second portion, the first portion being spaced apart from the second portion along a first direction.
7. The semiconductor device according to claim 6, wherein the first semiconductor layer is located between the first portion and the second portion of the gate electrode.
8. The semiconductor device according to claim 6, further comprising:
a second semiconductor layer having a band gap greater than a band gap of the first semiconductor layer, wherein the second semiconductor layer is located between the first portion and the second portion of the gate electrode.
9. The semiconductor device according to claim 6, wherein the gate electrode has a third portion, the first portion being spaced apart from the third portion along a second direction different from the first direction.
10. The semiconductor device according to claim 9, wherein the first semiconductor layer is located between the first portion and the third portion of the gate electrode.
11. The semiconductor device according to claim 9, further comprising:
a second semiconductor layer having a band gap greater than a band gap of the first semiconductor layer, wherein the second semiconductor layer is located between the first portion and the third portion of the gate electrode.
12. The semiconductor device according to claim 1, wherein an upper surface of the first semiconductor layer is coplanar with an upper surface of the gate electrode.
13. The semiconductor device according to claim 1, wherein an upper surface of the first semiconductor layer is not coplanar with an upper surface of the gate electrode.
14. The semiconductor device according to claim 1, wherein the via penetrates a portion of the gate electrode.
15. The semiconductor device according to claim 1, wherein the first semiconductor layer has a plurality of portions separated from each other, wherein the gate electrode has a plurality of portions separated from each other, and wherein the plurality of portions of the first semiconductor layer and the plurality of portions of the gate electrode are staggered with each other.
16. A method of manufacturing a semiconductor device, comprising:
providing a substrate;
forming a first nitride semiconductor layer on the substrate;
forming a second nitride semiconductor layer on the first nitride semiconductor layer, wherein the band gap of the second nitride semiconductor layer is larger than that of the first nitride semiconductor layer;
forming a third nitride semiconductor layer on the second nitride semiconductor layer, the third nitride semiconductor layer being doped with impurities;
forming a gate electrode on the third nitride semiconductor layer;
forming a first semiconductor layer on the third nitride semiconductor layer; a kind of electronic device with high-pressure air-conditioning system
Forming a via electrically connected to the gate electrode;
wherein the gate electrode and the third nitride semiconductor layer define a schottky contact and the first semiconductor layer and the via define an ohmic contact.
17. The method as recited in claim 16, further comprising:
forming a second semiconductor layer on the third nitride semiconductor layer, wherein the first semiconductor layer is formed on the second semiconductor layer, and the band gap of the second semiconductor layer is larger than that of the first semiconductor layer.
18. The method of claim 17, wherein the second semiconductor layer is doped with impurities.
19. The method of claim 16, wherein the first semiconductor layer is doped with impurities.
20. The method of claim 16, wherein forming the gate electrode comprises:
forming an electrode material layer on the third nitride semiconductor layer; a kind of electronic device with high-pressure air-conditioning system
A portion of the electrode material layer is removed to form the gate electrode having a first portion and a second portion spaced apart from the first portion.
21. A semiconductor device, comprising:
a substrate;
a first nitride semiconductor layer disposed on the substrate;
a second nitride semiconductor layer provided on the first nitride semiconductor layer and having a band gap larger than that of the first nitride semiconductor layer;
a third nitride semiconductor layer doped with impurities and provided on the second nitride semiconductor layer;
a gate electrode disposed on the third nitride semiconductor layer;
a carrier-providing layer adjoining the gate electrode, wherein the carrier-providing layer is configured to generate a first carrier to neutralize a second carrier located within a trap of the gate electrode.
22. The semiconductor device according to claim 21, further comprising:
a barrier layer disposed between the third nitride semiconductor layer and the carrier providing layer, wherein a band gap of the barrier layer is larger than a band gap of the carrier providing layer.
23. The semiconductor device according to claim 22, wherein the barrier layer is doped with an impurity.
24. The semiconductor device according to claim 21, wherein the carrier-providing layer is doped with an impurity.
25. The semiconductor device according to claim 21, wherein the gate electrode has a first portion and a second portion, the first portion being separated from the second portion by the carrier-providing layer.
CN202311667322.7A 2023-12-07 2023-12-07 Semiconductor device and method for manufacturing the same Active CN117374103B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311667322.7A CN117374103B (en) 2023-12-07 2023-12-07 Semiconductor device and method for manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311667322.7A CN117374103B (en) 2023-12-07 2023-12-07 Semiconductor device and method for manufacturing the same

Publications (2)

Publication Number Publication Date
CN117374103A true CN117374103A (en) 2024-01-09
CN117374103B CN117374103B (en) 2024-03-08

Family

ID=89394899

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311667322.7A Active CN117374103B (en) 2023-12-07 2023-12-07 Semiconductor device and method for manufacturing the same

Country Status (1)

Country Link
CN (1) CN117374103B (en)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110021661A (en) * 2019-04-26 2019-07-16 江苏能华微电子科技发展有限公司 Semiconductor devices and preparation method thereof
CN110299407A (en) * 2019-06-29 2019-10-01 厦门市三安集成电路有限公司 Power device and preparation method thereof
CN112331720A (en) * 2020-11-07 2021-02-05 东南大学 High-threshold-value stable gallium nitride power semiconductor device
CN113497137A (en) * 2020-04-07 2021-10-12 苏州捷芯威半导体有限公司 Semiconductor device and preparation method thereof
CN114038910A (en) * 2021-09-30 2022-02-11 江苏能华微电子科技发展有限公司 Combined contact structure and novel GaN HEMT device
CN114078957A (en) * 2020-08-10 2022-02-22 华为技术有限公司 Mixed gate field effect transistor, preparation method and switching circuit
US20220199795A1 (en) * 2020-04-20 2022-06-23 Huawei Technologies Co., Ltd. Gallium nitride component and drive circuit thereof

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110021661A (en) * 2019-04-26 2019-07-16 江苏能华微电子科技发展有限公司 Semiconductor devices and preparation method thereof
CN110299407A (en) * 2019-06-29 2019-10-01 厦门市三安集成电路有限公司 Power device and preparation method thereof
CN113497137A (en) * 2020-04-07 2021-10-12 苏州捷芯威半导体有限公司 Semiconductor device and preparation method thereof
US20220199795A1 (en) * 2020-04-20 2022-06-23 Huawei Technologies Co., Ltd. Gallium nitride component and drive circuit thereof
CN114078957A (en) * 2020-08-10 2022-02-22 华为技术有限公司 Mixed gate field effect transistor, preparation method and switching circuit
CN112331720A (en) * 2020-11-07 2021-02-05 东南大学 High-threshold-value stable gallium nitride power semiconductor device
CN114038910A (en) * 2021-09-30 2022-02-11 江苏能华微电子科技发展有限公司 Combined contact structure and novel GaN HEMT device

Also Published As

Publication number Publication date
CN117374103B (en) 2024-03-08

Similar Documents

Publication Publication Date Title
US10629681B2 (en) III-nitride devices including a graded depleting layer
US8390029B2 (en) Semiconductor device for reducing and/or preventing current collapse
KR20150092708A (en) Semiconductor device
KR101771022B1 (en) Gallium nitride power semiconductor device having a vertical structure
JP4955292B2 (en) Semiconductor device
WO2021189182A1 (en) Semiconductor device and manufacturing method therefor
CN114270532A (en) Semiconductor device and method for manufacturing the same
US20240105812A1 (en) Nitride-based semiconductor device and method for manufacturing the same
CN112840464B (en) Semiconductor device and method for manufacturing the same
CN117374103B (en) Semiconductor device and method for manufacturing the same
US20240055509A1 (en) Nitride-based semiconductor device and method for manufacturing the same
WO2023141749A1 (en) GaN-BASED SEMICONDUCTOR DEVICE WITH REDUCED LEAKAGE CURRENT AND METHOD FOR MANUFACTURING THE SAME
EP3405979B1 (en) Semiconductor device, electronic part, electronic apparatus, and method for fabricating semiconductor device
WO2023082058A1 (en) Nitride-based semiconductor device and method for manufacturing thereof
US11637177B2 (en) III-nitride semiconductor device with non-active regions to shape 2DEG layer
CN115939204B (en) Nitride semiconductor device and method for manufacturing the same
US20220376101A1 (en) Semiconductor device and fabrication method thereof
CN115458597B (en) Nitride-based semiconductor device and method of manufacturing the same
WO2023212856A1 (en) Semiconductor device and method for manufacturing thereof
WO2024011610A1 (en) Semiconductor device and method for manufacturing thereof
CN115832041A (en) Semiconductor device and method for manufacturing the same
CN116325173A (en) Nitride-based semiconductor device and method of manufacturing the same
CN115621310A (en) Semiconductor device and method for manufacturing the same
CN115663025A (en) Nitride-based semiconductor device and method for manufacturing the same
CN116190428A (en) Nitride-based semiconductor device and method of manufacturing the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant