CN117370094A - Test equipment, fault injection circuit and fault injection test method - Google Patents

Test equipment, fault injection circuit and fault injection test method Download PDF

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Publication number
CN117370094A
CN117370094A CN202311660434.XA CN202311660434A CN117370094A CN 117370094 A CN117370094 A CN 117370094A CN 202311660434 A CN202311660434 A CN 202311660434A CN 117370094 A CN117370094 A CN 117370094A
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China
Prior art keywords
controller
test
circuit
fault injection
module
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CN202311660434.XA
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CN117370094B (en
Inventor
王超
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Suzhou Metabrain Intelligent Technology Co Ltd
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Suzhou Metabrain Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2284—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by power-on test, e.g. power-on self test [POST]

Abstract

The invention discloses test equipment, a fault injection circuit and a fault injection test method, which are applied to the technical field of fault test and are used for solving the problems of low test efficiency and inaccurate test in the traditional scheme. Comprising the following steps: the power module is used for receiving the power supply of the upper computer and supplying power to the tested circuit after the voltage level conversion; the controller is used for sequentially receiving K items of test information sent by the upper computer, when the ith item of test information is received, the state control of each of the N driving modules is carried out based on the ith item of test information so as to carry out the ith item of fault injection test aiming at the tested circuit, and any 1 driving module is used for: under the control of the controller, the high-impedance state is output, or the high-level state is output, or the low-level state is output. By applying the scheme of the invention, the continuous K-term fault injection test of the tested circuit can be automatically realized, the connection relation does not need to be adjusted in the test process, and the test efficiency and the test result accuracy are effectively ensured.

Description

Test equipment, fault injection circuit and fault injection test method
Technical Field
The present invention relates to the field of fault testing technologies, and in particular, to a testing device, a fault injection circuit, and a fault injection testing method.
Background
In the storage field of large data volume and high speed, as the number of cases in the whole equipment is increased, the test on the equipment is also frequent, especially in the research and development design stage of the equipment, signals related to a main board are numerous, according to different development requirements, fault injection test is required to be carried out on signals at different positions, and the test is carried out according to test cases, so that the test period is long, the test quality is low, and the problem is easy to occur. Particularly, when the chassis is tested, the fault injection operation of signals is inconvenient, and the testing efficiency is affected. According to the current hardware fault injection mode, workers are required to manually lap the flying leads to test, and when test items are switched, the false test results are easily obtained due to human operation errors.
In summary, how to effectively implement the fault injection test, improve the test efficiency, and ensure the test accuracy is a technical problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide test equipment, a fault injection circuit and a fault injection test method, so as to effectively realize fault injection test, improve test efficiency and ensure test accuracy.
In order to solve the technical problems, the invention provides the following technical scheme:
a fault injection circuit comprising:
the power supply module is respectively connected with the upper computer and the tested circuit and is used for receiving the power supply of the upper computer and supplying power to the tested circuit after the voltage class conversion;
the controller is connected with the upper computer and is used for sequentially receiving K items of test information sent by the upper computer, and when the ith item of test information is received, the state control of each of the N driving modules is carried out based on the ith item of test information so as to carry out the ith fault injection test for the tested circuit;
the N driving modules are connected with the controller at the input ends, the N driving modules are connected with the tested circuit at the output ends, and any 1 driving module is used for the tested circuit; the control of the controller is in a high-resistance state, or the control of the controller is in a high-level state at the output end of the controller, or the control of the controller is in a low-level state at the output end of the controller;
n is a positive integer, K is a positive integer, and i is a positive integer and is equal to or more than 1 and equal to or less than K.
In a specific embodiment of the present invention, the circuit structures of the N driving modules are the same, and each driving module is provided with a power supply end for connecting with the power supply module, so that under the control of the controller, the output end of the driving module is in a high level state by using the received power supplied by the power supply module, and each driving module is provided with a grounding end for grounding, so that under the control of the controller, the output end of the driving module is in a low level state by grounding of the grounding end.
In a specific embodiment of the present invention, any 1 of the driving modules are driving modules based on switching tubes, resistors and gates, and are configured to control, under the control of the controller, on-off states of the switching tubes in the driving modules in combination with the gates, so that the driving modules are in a high-resistance state, or an output end is in a high-level state, or an output end is in a low-level state under the control of the controller.
In one embodiment of the present invention, any 1 of the driving modules includes: the switching circuit comprises a first switching tube, a second switching tube, a third switching tube, a first resistor, a second resistor and a NOR gate circuit;
The first end of the first switch tube is used as a power end of the driving module and is connected with the power module so as to receive power supply of the power module; the second end of the first switch tube is connected with the first end of the first resistor; the control end of the first switching tube is connected with the first input end of the NOR gate circuit, and the connection end is used as an enabling end of the driving module;
the second end of the first resistor is connected with the first end of the second switching tube, the second end of the second switching tube is connected with the first end of the second resistor, and the connecting end is used as the output end of the driving module;
the second end of the second resistor is connected with the first end of the third switching tube, the second end of the third switching tube is grounded, the control end of the third switching tube is respectively connected with the control end of the second switching tube and the output end of the NOR gate circuit, and the second input end of the NOR gate circuit is used as the input end of the driving module;
the enabling end of the driving module and the input end of the driving module are connected with the controller, and when the controller controls the enabling end of the driving module to be in a high-level state, the driving module is in a high-resistance state; when the controller controls the enabling end of the driving module to be in a low level, the driving module is in an enabling state, and in the enabling state, the level state of the output end of the driving module is consistent with the level state of the input end of the driving module.
In a specific embodiment of the present invention, for any 1 of the driving modules, the driving module further includes:
each first resistor branch comprises 1 resistor and a first controllable switch connected in series with the resistor, and the on-off states of the x first controllable switches are controlled by the controller so as to allow the controller to adjust the driving capability of the driving module when the output end is in a high level state; wherein x is a positive integer.
In a specific embodiment of the present invention, for any 1 of the driving modules, the driving module further includes:
y second resistor branches connected in parallel with the second resistor, wherein each second resistor branch comprises 1 resistor and a second controllable switch connected in series with the resistor, and the on-off states of the y second controllable switches are controlled by the controller so as to allow the controller to adjust the driving capability of the driving module when the output end is in a low level state; wherein y is a positive integer.
In one embodiment of the present invention, the power module is specifically configured to:
receiving power supply of the upper computer and providing power supply of z different voltage levels for the tested circuit after reducing the voltage to z different voltage levels; z is a positive integer not less than 2.
In a specific embodiment of the present invention, the power supply alarm signal pin and the z power supply enable signal pins of the power supply module are connected to the controller, and the controller is further configured to:
when the power supply alarm signal pins of the power supply module are detected to send an alarm, the power supply module is turned off through z power supply enabling signal pins, N driving modules are controlled to be in a high-resistance state, and the current fault injection test is ended.
In a specific embodiment of the present invention, each of the z power normal signal pins of the power module is connected to the controller, and the controller is further configured to:
when the j-th power normal signal pin of the power supply module is detected to be in a failure state, the j-th voltage class output of the power supply module is closed through the j-th power enable signal pin, and all driving modules receiving the j-th voltage class power supply of the power supply module are controlled to be in a high-resistance state; j is a positive integer and 1.ltoreq.j.ltoreq.z.
In one specific embodiment of the present invention, the controller is connected to the host computer through a universal serial bus connector and a protocol converter;
The universal serial bus connector is respectively connected with the upper computer and the protocol converter, and is used for: transmitting the test instruction sent by the upper computer to the protocol converter;
the protocol converter is connected with the controller, and is used for: receiving a test instruction sent by the universal serial bus connector and sending the test instruction to the controller after converting the test instruction into a first format;
wherein the first format is an instruction format supported by the controller.
In a specific embodiment of the present invention, for any 1 of the N driving modules, an output end of the driving module is connected to a specified position of the tested circuit through a crossover resistor, and a distance between the crossover resistor and the specified position is lower than a preset distance threshold.
In a specific embodiment of the present invention, the monitoring and recording circuit is further included for:
and when the controller performs the ith fault injection test for the tested circuit, monitoring and recording circuit indexes at preset positions of the tested circuit.
In a specific embodiment of the invention, a reserved interface is arranged on the controller, the controller is connected with a main board where the tested circuit is located through the reserved interface, and the controller and the N driving modules are arranged on the main board;
The controller is further configured to: and sequentially receiving K items of test information sent by the main board through the reserved interface, and carrying out respective state control of N driving modules based on the ith item of test information when the ith item of test information is received so as to carry out the ith item of fault injection test for the tested circuit.
The fault injection test method is applied to the controller in the fault injection circuit, and comprises the following steps:
sequentially receiving K items of test information sent by an upper computer;
when the ith test information is received, the state control of each of the N driving modules is carried out based on the ith test information so as to carry out the ith fault injection test for the tested circuit.
A test apparatus comprising a fault injection circuit as described above.
By applying the technical scheme provided by the embodiment of the invention, K fault injection tests of the tested circuit can be automatically realized through the fault injection circuit, and the fault injection circuit in the scheme of the application is not adopted in the traditional scheme. Specifically, the application considers that when the fault injection test of the tested circuit is performed, the tested circuit needs to be in a working state, and the main board of the tested circuit is subjected to self-power supply in the traditional scheme, which can influence the accuracy of the fault test to a certain extent.
The controller is connected with the upper computer, can receive K items of test information that the upper computer sent in proper order to, when receiving the ith item of test information, carry out the respective state control of N drive modules based on the ith item of test information, in order to carry out the ith item of fault injection test to the circuit under test, that is to say, in the scheme of this application, can carry out K items of fault injection test to the circuit under test in proper order through the fault injection circuit, improved test efficiency.
In addition, in consideration of the fact that the fault injection positions are different when different items of fault injection tests are carried out, in other words, when different items of fault injection tests are carried out, the specific used driving modules are different, the unused driving modules are still connected to the tested circuit, and in order to avoid affecting the accuracy of test results, the unused driving modules can be in a high-resistance state. That is, when each fault injection test of the tested circuit is performed, for any 1 driving module of the N driving modules, the driving module not only can make its own output end be in a high level state or in a low level state under the control of the controller, but also can be in a high resistance state under the control of the controller, so that the accuracy of the test result is not affected.
In summary, the scheme of the application can automatically realize continuous K-item fault injection test of the tested circuit by using the fault injection circuit, and the connection relation does not need to be adjusted in the test process, so that the test efficiency is effectively ensured, and the accuracy of the test result is effectively ensured.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a fault injection circuit according to the present invention;
FIG. 2 is a schematic diagram of a fault injection circuit according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a driving module according to an embodiment of the present invention;
FIG. 4 is a flow chart illustrating a fault injection testing method according to an embodiment of the present invention.
Detailed Description
The invention provides test equipment, a fault injection circuit and a fault injection test method, which can automatically realize continuous K fault injection tests of a tested circuit by using the fault injection circuit, and the connection relation does not need to be adjusted in the test process, so that the test efficiency is effectively ensured, and the accuracy of a test result is effectively ensured.
In order to better understand the aspects of the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a fault injection circuit according to the present invention, where the fault injection circuit may include:
the power module 10 is respectively connected with the upper computer and the tested circuit, and is used for receiving the power supply of the upper computer and supplying power to the tested circuit after the voltage class conversion;
the controller 20 is connected with the upper computer and is used for sequentially receiving K items of test information sent by the upper computer, and when the ith item of test information is received, the state control of each of the N driving modules 30 is carried out based on the ith item of test information so as to carry out the ith item of fault injection test for the tested circuit;
the N driving modules 30, the input ends of the N driving modules 30 are connected with the controller 20, the output ends of the N driving modules 30 are connected with a tested circuit, and any 1 driving module 30 is used for detecting the current of the tested circuit; under the control of the controller 20, the output end of the controller 20 is in a high-level state, or under the control of the controller 20, the output end of the controller 20 is in a low-level state;
N is a positive integer, representing the total number of drive modules 30, K is a positive integer, representing the total number of items for fault injection testing, typically at least 2, i is a positive integer and 1.ltoreq.i.ltoreq.K.
Specifically, the application considers that when performing fault injection test of the tested circuit, the tested circuit needs to be in a working state, and if the main board of the tested circuit is self-powered, the accuracy of the fault test can be affected to a certain extent. Therefore, the scheme of the application is provided with the power supply module 10 which is respectively connected with the upper computer and the tested circuit, the power supply module 10 can receive the power supply of the upper computer and supply power to the tested circuit after the conversion of the voltage level, that is, the power supply module 10 receives the power supply of the external power supply, and the external power supply is not directly power supply to the tested circuit, but isolation is realized through the power supply module 10, so that the obtained test result is free from the interference of the main board power supply or the external power supply when the fault injection test of the tested circuit is carried out later, and the accuracy of the test is ensured.
The specific circuit configuration of the power module 10 can be set and adjusted according to practical situations, and a step-down power module 10 with a better isolation effect can be generally adopted, that is, after the power module 10 receives power supplied by an upper computer, step-down is performed and output to a tested circuit.
Further, in practical applications, considering that the power supply voltage levels required by different devices of the tested circuit are different, for example, in an occasion, the tested circuit needs to use voltages of 3.3V,2.5V,1.8V and 1.0V, therefore, in one embodiment of the present invention, the power module 10 may be specifically used for:
and receiving the power supply of the upper computer, and providing the power supply of z different voltage levels for the tested circuit after the power supply is reduced to z different voltage levels.
In this embodiment, the power module 10 can provide power with z different voltage levels for the tested circuit, so as to effectively meet the power supply requirements of different voltage levels at different positions of the tested circuit. z is a positive integer not less than 2, for example, in the example of fig. 2, z=4, and in other embodiments, z may have other values, depending on the power requirements of the circuit under test. It will be appreciated that the voltage accuracy of the different voltage levels output by the power module 10 may be matched to or higher than the accuracy required by the device under test, and the parameters for measuring the voltage accuracy may be, for example, voltage amplitude range, ripple size, load capacity, etc.
The controller 20 is connected with the upper computer, and can sequentially receive the K items of test information sent by the upper computer, that is, in the scheme of the application, K items of fault injection test can be sequentially performed. When the controller 20 receives the ith test information, it performs respective state control of the N driving modules 30 based on the ith test information to perform the ith fault injection test for the tested circuit.
For example, in one case, when the controller 20 receives the 1 st test information, it determines that the 1 st driving module 30 of the N driving modules 30 needs to be controlled this time based on the information of 0X0001 carried in the 1 st test information. The input end of the 1 st driving module 30 is connected to the controller 20, and the output end is connected to the circuit to be tested, for example, the 1 st test information also carries 0X00, which means that the output end of the 1 st driving module 30 needs to be controlled to be in a low level state, the controller 20 writes 0X00 into a certain register corresponding to 0X0001, and since the register stores 0X00, the controller 20 controls the 1 st driving module 30 through a corresponding pin, so that the output end of the 1 st driving module 30 is in a low level state. If the 1 st test information is not 0x00 but 0x01, it indicates that the output end of the 1 st driving module 30 needs to be controlled to be in a high level state, and at this time, the controller 20 controls the 1 st driving module 30 through the corresponding pin, so that the output end of the 1 st driving module 30 is in a high level state.
In the solution of the present application, N driving modules 30 are provided, and in fig. 1, for convenience of viewing, a specific circuit structure of a single driving module 30 in a specific case is shown. In this application, the input ends of the N driving modules 30 are all connected with the controller 20, the output ends of the N driving modules 30 are all connected with the tested circuit, N is a positive integer, and represents the total number of the driving modules 30, in the embodiments of fig. 1 and fig. 2, only 2 driving modules 30 are shown for convenience in viewing, and in practical application, a larger number of driving modules 30 are generally required to be set.
The location at which the fault injection is performed is different when the fault injection test of different items is performed, in other words, the specific driving module 30 used is different when the fault injection test of different items is performed. Taking fig. 2 as an example, fig. 2 shows a part of a tested circuit, that is, 1 clock circuit and 1 CPLD (Complex Programmable Logic Device ) are connected with a BMC (Board Management Controller, baseboard management controller), for example, a plurality of driving modules 30 are not shown in fig. 2, and for example, when the 5 th fault injection test in the K fault injection test is performed, only the 2 driving modules 30 shown in fig. 2 need to be used, if the accuracy of the 5 th fault injection test is to be ensured, the connection with the tested circuit should be disconnected for the remaining driving modules 30, but if the connection between these driving modules 30 and the tested circuit is disconnected by manual operation by a staff member, the test efficiency is not improved, while in the scheme of the present application, any 1 driving module 30 can be in a high-impedance state under the control of the controller 20, which is equivalent to the disconnection with the tested circuit, so that the accuracy of the fault injection test is not affected.
In this regard, in the solution of the present application, for any 1 driving module 30 of the N driving modules 30, the driving module 30 may not only be in a high level state or a low level state under the control of the controller 20, but also be in a high resistance state under the control of the controller 20, so that the accuracy of the test result is not affected.
Of course, when the ith fault injection test is performed, for each of the N driving modules 30, what state each should be in, it may be determined by the ith test information.
In the scheme of the present application, N driving modules 30 need to be provided, and in a specific embodiment of the present invention, the circuit structures of the N driving modules 30 may be identical, which is favorable for reducing the production cost of the driving modules 30, and also is favorable for transporting and implementing device replacement of the fault driving module 30. Also, considering that the driving modules 30 are enabled to be in a high-impedance state, an output end high-level state, and an output end low-level state in the present application, in a specific embodiment of the present invention, a power end may be provided in each driving module 30 for connection with the power module 10, so that the output end of the driving module is in a high-level state by using the received power of the power module 10 under the control of the controller 20, and a ground end is provided in each driving module 30 for grounding, so that the output end of the driving module is in a low-level state by grounding of the ground end under the control of the controller 20.
The specific circuit configuration of the driving module 30 in the scheme of the present application can be set and adjusted according to actual needs, however, it is required to output a high level, and also to output a low level, and still it is required to be in a high-resistance state, for this application, considering that any 1 driving module 30 may be a driving module 30 based on a switching tube, a resistor and a gate circuit, and at least 1 switching tube is connected to the power module 10, at least 1 switching tube is grounded, and the gate circuit is used for: the on-off state of each switching tube in the driving module 30 is controlled by matching with the output signal of the controller 20, so that the driving module 30 is in a high-resistance state, or the output end is in a high-level state, or the output end is in a low-level state under the control of the controller 20.
It can be seen that in this embodiment, the gate circuit and the output signal of the controller 20 are used to control the on-off state of each switching tube in the driving module 30, which is convenient for implementing the control logic, and the channel control of the switching tubes can determine whether the driving module 30 is in the high-resistance state, the output end is in the high-level state or the output end is in the low-level state. It can be seen that in this embodiment, on the basis of guaranteeing the function of the driving module 30, passive devices are used, the number of device types is small, only 3 types of devices are used, and the reliability of the 3 types of devices is also high, so that the reliability of the driving module 30 can be effectively guaranteed.
For example, in one embodiment of the present invention, referring to fig. 2, any 1 of the driving modules 30 may include: the first switch tube Q1, the second switch tube Q2, the third switch tube Q3, the first resistor R1, the second resistor R2 and the NOR gate circuit 31. For convenience of viewing, only the specific structure of 1 driving module 30 is shown in fig. 2, and as described above, the specific structure of the remaining driving modules 30 may be the same.
The first end of the first switching tube Q1 is used as a power end of the driving module 30 and is connected with the power module 10 to receive power supply of the power module 10; the second end of the first switch tube Q1 is connected with the first end of the first resistor R1; the control end of the first switching tube Q1 is connected with the first input end of the NOR gate circuit 31, and the connection end is used as the enabling end of the driving module 30;
the second end of the first resistor R1 is connected with the first end of the second switching tube Q2, the second end of the second switching tube Q2 is connected with the first end of the second resistor R2, and the connecting end is used as the output end of the driving module 30;
the second end of the second resistor R2 is connected with the first end of the third switching tube Q3, the second end of the third switching tube Q3 is grounded, the control end of the third switching tube Q3 is respectively connected with the control end of the second switching tube Q2 and the output end of the NOR gate circuit 31, and the second input end of the NOR gate circuit 31 is used as the input end of the driving module 30;
The enabling end of the driving module 30 and the input end of the driving module 30 are connected with the controller 20, and when the controller 20 controls the enabling end of the driving module 30 to be in a high level, the driving module 30 is in a high resistance state; when the controller 20 controls the enable terminal of the driving module 30 to be at a low level, the driving module 30 is in an enable state, and in the enable state, the level state of the output terminal of the driving module 30 is consistent with the level state of the input terminal of the driving module 30.
Specifically, in this embodiment, the third switching tube Q3 needs to be a switching tube that is turned on when the control end is at a high level, the first switching tube Q1 and the second switching tube Q2 are both switching tubes that are turned on when the control end is at a low level, for example, in the embodiment of fig. 2, the first switching tube Q1 and the second switching tube Q2 are both PMOS tubes, and the third switching tube Q3 is an NMOS tube.
As can be seen from the specific structure of the driving module 30 in fig. 2, when the controller 20 outputs a high level to the enable terminal of the driving module 30, the control terminal of the first switching tube Q1 is in a high level state, and at this time, the first switching tube Q1 is not turned on and is in an off state. Since the control end of the first switching tube Q1 is connected to the first input end of the nor gate circuit 31 and the connection end is used as the enabling end of the driving module 30, when the controller 20 outputs a high level to the enabling end of the driving module 30, the first input end of the nor gate circuit 31 is also high level, and the output end of the nor gate circuit 31 is low level no matter whether the second input end of the nor gate circuit 31 is high level or low level. Since the output terminal of the nor gate circuit 31 is at a low level, the third switching transistor Q3 is in an off state. At this time, since the first switching tube Q1 is in the off state, there is no voltage difference between the first end of the second switching tube Q2 and the control end thereof, and thus the second switching tube Q2 is also in the off state.
In summary, when the controller 20 outputs a high level to the enable end of the driving module 30, the first switching tube Q1, the second switching tube Q2 and the third switching tube Q3 in the driving module 30 are all in an off state, so that the driving module 30 is in a high-resistance state at this time.
And if the controller 20 outputs a low level to the enable terminal of the driving module 30, the level state of the output terminal of the driving module 30 depends on the level state of the input terminal of the driving module 30. Specifically, if the controller 20 outputs a high level signal to the input terminal of the driving module 30, the output terminal of the nor gate 31 is low level, and at this time, the third switching transistor Q3 is in an off state. The first switching tube Q1 is in a conducting state because the enabling end of the driving module 30 is at a low level, and at this time, the second switching tube Q2 is also in a conducting state because the control end of the second switching tube Q2 is at a low level and a voltage difference exists between the first end of the second switching tube Q2 and the control end thereof.
In summary, when the controller 20 outputs a low level to the enable end of the driving module 30 and outputs a high level to the input end of the driving module 30, the first switching tube Q1 and the second switching tube Q2 in the driving module 30 are in an on state, and the third switching tube Q3 is in an off state, so that the output end of the driving module 30 is in a high level state, and the voltage at the corresponding position of the tested circuit can be forced to be pulled up, thereby realizing fault injection.
If the controller 20 outputs a low level signal to the enable end of the driving module 30 and the controller 20 outputs a low level signal to the input end of the driving module 30, the output end of the nor gate circuit 31 is at a high level, at this time, the third switching tube Q3 is in an on state, and the first switching tube Q1 and the second switching tube Q2 are in an off state, so that the output end of the driving module 30 is in a low level state, and the voltage at the corresponding position of the tested circuit can be forced to be pulled down, thereby realizing fault injection.
It can be seen that the driving module 30 in this embodiment effectively meets the functional requirements of the driving module 30 in this application, and has a simple structure and high reliability.
Referring to the following table one, which is a logic table of the driving module 30 in the embodiment of fig. 2, it can be seen that when the enable terminal is at a high level, the output terminal of the driving module 30 is in a high-resistance state, and when the enable terminal is at a low level, the level state of the output terminal of the driving module 30 is consistent with the level state of the input terminal thereof.
Table one:
in the above embodiment, the first end of the first switching tube Q1 is used as the power end of the driving module 30, and needs to be connected to the power module 10, and in the example of fig. 2, the specific connection is 3.3V dc output by the power module 10. It should be noted that the voltage level required at the power supply terminal of the driving module 30 may be different for different driving modules 30, and the voltage level at the power supply terminal of the driving module 30 may be determined based on the specific location of the circuit under test to which the driving module 30 is connected in practical application. For example, in the example of fig. 2, a voltage of 1.8V is required at the power supply terminal of the other driving module 30.
In a specific embodiment of the present invention, for any 1 driving module 30 of the N driving modules 30, the output end of the driving module 30 is connected to a designated position of the tested circuit through a crossover resistor, and the distance between the crossover resistor and the designated position is lower than a preset distance threshold.
The crossover resistor, i.e., the 0 ohm resistor, is a resistor with a small resistance value. In the example of fig. 2, the 2 driving modules 30 are all connected at designated positions of the tested circuit through crossover resistors, that is, the 2 driving modules 30 are respectively connected at corresponding fault injection positions of the tested circuit through 2 crossover resistors, and the 2 crossover resistors are respectively labeled as R01 and R02 in fig. 2. In this embodiment, the driving module 30 is required to be connected with the circuit to be tested in the scheme of the application, and the connection is realized through the crossover resistor, so that the reliability and stability of the connection can be ensured.
In this embodiment, the distance between the crossover resistor and the designated location is lower than the preset distance threshold, that is, the crossover resistor is located close to the circuit to be tested, which is advantageous for avoiding the signal integrity problem. That is, after the fault injection test is completed and the fault injection circuit is removed, the wire ends left at each designated position of the tested circuit are short, and the tested circuit is not affected.
In the example of fig. 2, the second input of nor gate 31 is also connected to controller 20 via 1 crossover resistor R03.
In one embodiment of the present invention, the power alarm signal pin and the z power enable signal pins of the power module 10 are connected to the controller 20, and the controller 20 may be further configured to:
when detecting that the power supply alarm signal pin of the power supply module 10 gives an alarm, the power supply module 10 is turned off through the z power supply enable signal pins, the N driving modules 30 are controlled to be in a high-resistance state, and the current fault injection test is ended.
In the example of fig. 2, the power alarm signal pin of the power module 10 is connected to the controller 20, and the line is labeled "alarm" in fig. 2, and the controller 20 can effectively learn the fault state of the power module 10 through the power alarm signal pin. For example, in one case, when the power module 10 detects an overtemperature, it controls the power alarm signal pin of the power module 10 to switch from a default high level state to a low level state, and when the controller 20 detects the condition, it can determine that an alarm sent by the power alarm signal pin of the power module 10 is detected, at this time, the controller 20 can turn off the power module 10 through z power enable signal pins, since z=4 in the example of fig. 2, the power module 10 has 4 power enable signal pins and all are connected to the controller 20, and of course, for convenience of viewing, only 1 power enable signal pin is shown in fig. 2 and the line is marked as "enabled". Meanwhile, to avoid damaging the circuit under test, the controller 20 controls the N driving modules 30 to be in the high-impedance state, and ends the current fault injection test.
In one embodiment of the present invention, the z power normal signal pins of the power module 10 are all connected to the controller 20, and the controller 20 is further configured to:
when the j-th power normal signal pin of the power module 10 is detected to be in a failure state, the j-th voltage class output of the power module 10 is turned off through the j-th power enable signal pin, and each driving module 30 receiving the j-th voltage class power supply of the power module 10 is controlled to be in a high-resistance state; j is a positive integer and 1.ltoreq.j.ltoreq.z.
Since z power normal signal pins of the power module 10, that is, z power signal pins of the power module 10, are z=4 in the example of fig. 2, the power module 10 has 4 power signal pins and is connected to the controller 20, of course, only 1 power signal pin is shown and labeled as "PG" in fig. 2 for convenience of viewing.
In this embodiment, when the j-th power normal signal pin of the power module 10 is detected to be in the failure state, it is indicated that an abnormality may occur in the output of the j-th voltage level of the power module 10, for which the controller 20 may turn off the output of the j-th voltage level of the power module 10 through the j-th power enable signal pin, and to ensure reliability, each driving module 30 receiving the power of the j-th voltage level of the power module 10 may be controlled to be in a high resistance state so as to avoid damaging the tested circuit.
In one embodiment of the present invention, referring to fig. 3, for any 1 driving module 30, the driving module 30 may further include:
x first resistor branches connected in parallel with the first resistor R1, each first resistor branch including 1 resistor and a first controllable switch connected in series with the resistor, wherein the on-off states of the x first controllable switches are controlled by the controller 20, so as to allow the controller 20 to adjust the driving capability of the driving module 30 when the output end is in a high level state; wherein x is a positive integer.
As described above, when the output end of the driving module 30 is in the high level state, the voltage at the corresponding position of the tested circuit needs to be forced to be pulled up, and the resistance value of the first resistor R1 can adjust the current flowing into the tested circuit, so in practical application, the circuit structures of the N driving modules 30 are generally the same, but the resistance values of the first resistors R1 in the N driving modules 30 are not necessarily completely identical due to the fact that the circuit structures are connected to different positions of the tested circuit, but are set according to the actual needs.
And this embodiment further considers that, for the same driving module 30, although the position where the driving module 30 accesses the tested circuit is determined, that is, the position where the driving module 30 accesses the tested circuit is not changed during all K fault injection tests, in some cases, the requirement for the resistance value of the first resistor R1 may be different during different fault injection tests. That is, for the same driving module 30, in some cases, the resistance value of the first resistor R1 is required to be adjustable, so as to adjust the current flowing into the circuit under test when the output terminal of the driving module 30 is in a high level state, thereby avoiding irreversible damage to the circuit under test.
In this embodiment, x first resistor branches are provided in parallel with the first resistor R1. Referring to fig. 3, each first resistor branch comprises 1 resistor and a first controllable switch in series with the resistor, 3 first resistor branches being shown in fig. 3 and labeled 32.
The on-off states of the x first controllable switches are all controlled by the controller 20, so that the controller 20 wants to adjust the resistance value of the first resistor R1 by controlling the on-off states of the x first controllable switches, and adjusts the driving capability of the driving module 30 when the output end is in a high level state, so as to avoid irreversible damage to the tested circuit.
In one embodiment of the present invention, for any 1 driving module 30, the driving modules 30 further include:
y second resistor branches connected in parallel with the second resistor R2, each second resistor branch including 1 resistor and a second controllable switch connected in series with the resistor, wherein the on-off states of the y second controllable switches are controlled by the controller 20, so as to allow the controller 20 to adjust the driving capability of the driving module 30 when the output end is in a low level state; wherein y is a positive integer.
As described above, when the output end of the driving module 30 is in the low level state, the voltage at the corresponding position of the tested circuit needs to be forced to be pulled down, and the resistance value of the second resistor R2 can adjust the current flowing through the third switching tube Q3, so in practical application, the circuit structures of the N driving modules 30 are generally the same, but the resistance values of the second resistors R2 in the N driving modules 30 are not necessarily completely identical due to the different positions of the tested circuit being connected, but need to be set according to practical needs.
And such an embodiment further contemplates that, for the same drive module 30, although the location where the drive module 30 is connected to the circuit under test is determined, in some cases, the requirements for the resistance value of the second resistor R2 may be different when performing different fault injection tests. That is, for the same driving module 30, in some cases, the resistance value of the second resistor R2 is required to be adjustable, so as to adjust the current flowing through the third switching tube Q3 when the output terminal of the driving module 30 is in the low level state, so as to avoid burning the third switching tube Q3.
In this embodiment, y second resistor branches are provided in parallel with the second resistor R2. Referring to fig. 3, each second resistor branch comprises 1 resistor and a second controllable switch in series with the resistor, 4 second resistor branches being shown in fig. 3 and labeled 33.
The on-off states of the y second controllable switches are all controlled by the controller 20, so that the controller 20 wants to adjust the resistance value of the second resistor R2 by controlling the on-off states of the y second controllable switches, and thus adjusts the driving capability of the driving module 30 when the output terminal is in the low level state, so as to avoid burning the third switching tube Q3.
In one embodiment of the present invention, the controller 20 is connected to the host computer through a universal serial bus connector and a protocol converter;
the universal serial bus connector is respectively connected with the upper computer and the protocol converter and is used for: transmitting a test instruction sent by the upper computer to the protocol converter;
the protocol converter is connected to the controller 20, and is configured to: receiving a test instruction sent by the universal serial bus connector and sending the test instruction to the controller 20 after being converted into the first format;
wherein the first format is an instruction format supported by the controller 20.
In this embodiment, the host computer usually has a USB (Universal Serial Bus ) interface, and the controller 20 usually adopts a CPLD device or other device, which cannot be directly connected to the host computer, so in this embodiment, the controller 20 can be connected to the host computer through a universal serial bus connector and a protocol converter, thereby ensuring the flexibility of connection.
In fig. 2, the universal serial bus connector is respectively connected with the upper computer and the protocol converter, so that the test instruction sent by the upper computer can be transferred to the protocol converter.
The protocol converter is connected to the controller 20, and can receive the test command sent by the universal serial bus connector, and send the test command to the controller 20 after converting the test command to the first format, for example, the first format specific UART (Universal Asynchronous Receiver/Transmitter ) format. A GPIO (General Purpose Input/Output) interface is used to connect to the driver module 30.
In a specific embodiment of the present invention, the monitoring and recording circuit is further included for:
when the controller 20 performs the i-th fault injection test for the tested circuit, the circuit index at the preset position of the tested circuit is monitored and recorded.
In the scheme of the application, through the fault injection circuit, K fault injection tests of the tested circuit are realized, and in order to facilitate the work of staff, in the embodiment, the monitoring and recording circuit is arranged, so that when the controller 20 performs the ith fault injection test of the tested circuit, circuit indexes at the preset position of the tested circuit can be automatically monitored and recorded.
In addition, it can be understood that the specific content of the circuit index to be monitored can be set and adjusted according to the actual situation. And when performing the analysis of a fault injection test, it is often analyzed whether the circuit under test has resistance to such fault injection conditions or whether the circuit under test has recovery capability for such fault injection conditions.
Taking the tested circuit including the BMC as an example in fig. 2, for example, before a certain fault injection test is performed, the output signal waveform of a certain output port of the BMC under a normal working condition can be determined by means of experimental record and/or theoretical analysis, for example, in this case, the tested circuit is required to have resistance to the fault injection condition, when the fault injection test is performed, the monitoring record circuit monitors and records the output signal waveform of the output port of the BMC, and a worker can determine whether the tested circuit has resistance to the fault injection condition by analyzing the waveform recorded by the monitoring record circuit and whether the waveform is consistent with the output signal waveform under the normal working condition.
In another example, in this case, the tested circuit is required to have the recovery capability for the fault injection condition, after the fault injection is finished, the monitoring and recording circuit monitors and records the waveform of the output signal of the output port of the BMC, and the staff can determine whether the tested circuit has the recovery capability for the fault injection condition by analyzing the waveform recorded by the monitoring and recording circuit and whether the waveform is consistent with the waveform of the output signal under the normal working condition.
In a specific embodiment of the present invention, a reserved interface is disposed on the controller 20, and the controller 20 is connected to a motherboard where a tested circuit is located through the reserved interface, and the controller 20 and the N driving modules 30 are all disposed on the motherboard;
the controller 20 is also configured to: k items of test information sent by the main board are sequentially received through the reserved interface, and when the ith item of test information is received, the state control of each of the N driving modules 30 is carried out based on the ith item of test information so as to carry out the ith item of fault injection test for the tested circuit.
In the scheme of the application, K fault injection tests aiming at the tested circuit can be efficiently and accurately carried out through the fault injection circuit, and the implementation mode further considers that the fault injection circuit is usually used as external equipment, namely when the fault injection test of certain tested equipment is needed, the fault injection circuit is connected with the tested equipment by staff. In particular situations, such as developing tests, where fault injection tests are performed very frequently on some devices under test, in order to avoid frequent connection of the fault injection circuit to the circuit under test, this embodiment contemplates that a reserved interface may be provided on the controller 20, and that the controller 20 is connected to the motherboard where the circuit under test is located through the reserved interface, while the controller 20 and the N driving modules 30 are directly disposed on the motherboard.
That is, in this embodiment, the controller 20 and the N driving modules 30 in the fault injection circuit may be integrated on the motherboard, and the controller 20 may sequentially receive the K test information sent by the motherboard through the reserved interface, so as to implement the fault injection test for each item of the tested device without requiring an upper computer.
According to the implementation mode, the main board where the tested circuit is located has the function of realizing fault injection test, so that the use flexibility of the scheme in practical application is improved, namely, in partial occasions, workers do not need to connect an upper computer and a fault injection circuit externally to realize fault injection test on the tested circuit.
Of course, when the implementation mode is adopted, the fault injection test of the tested equipment in the main board is directly realized by using the main board without connecting an upper computer, so that the power supply of the tested equipment is directly provided by the main board. In addition, in some cases, when the controller 20 is connected to the motherboard through a reserved interface, a device such as a BUFFER isolation circuit may be provided to improve signal quality.
By applying the technical scheme provided by the embodiment of the invention, K fault injection tests of the tested circuit can be automatically realized through the fault injection circuit. Specifically, the present application considers that when the fault injection test of the tested circuit is performed, the tested circuit needs to be in a working state, and in the traditional scheme, the main board of the tested circuit is self-powered, which can affect the accuracy of the fault test to a certain extent, in this application, the power module 10 connected with the upper computer and the tested circuit respectively is provided, the power module 10 can receive the power of the upper computer and supply power to the tested circuit after the conversion of the voltage level, that is, the power module 10 receives the power of the external power supply, and the external power supply is not directly used for supplying power to the tested circuit, but realizes isolation through the power module 10, so that the obtained test result is not interfered by the main board power supply or the external power supply when the fault injection test of the tested circuit is performed later, and the accuracy of the test is ensured.
The controller 20 is connected with the upper computer, and can sequentially receive K items of test information sent by the upper computer, and when the ith item of test information is received, the respective state control of the N driving modules 30 is performed based on the ith item of test information so as to perform the ith item of fault injection test for the tested circuit, that is, in the scheme of the application, the K items of fault injection test for the tested circuit can be sequentially performed through the fault injection circuit, so that the test efficiency is improved.
In addition, the present application considers that when different fault injection tests are performed, the positions of fault injection are different, in other words, when different fault injection tests are performed, the specific used driving modules 30 are different, while the unused driving modules 30 are still connected to the tested circuit, so that in order to avoid affecting the accuracy of the test result, the unused driving modules 30 may be in a high-impedance state. That is, when each fault injection test of the tested circuit is performed, for any 1 driving module 30 of the N driving modules 30, the driving module 30 not only can make its own output end be in a high level state or a low level state under the control of the controller 20, but also can be in a high resistance state under the control of the controller 20, so that the accuracy of the test result is not affected.
In summary, the scheme of the application can automatically realize continuous K-item fault injection test of the tested circuit by using the fault injection circuit, and the connection relation does not need to be adjusted in the test process, so that the test efficiency is effectively ensured, and the accuracy of the test result is effectively ensured.
Corresponding to the above embodiments of the fault injection circuit, embodiments of the present invention also provide a test apparatus, which may include the fault injection circuit in any of the above embodiments.
Referring to fig. 4, the embodiment of the present invention further provides a fault injection test method, which may be applied to the controller in the fault injection circuit in any of the above embodiments, including:
step S401: sequentially receiving K items of test information sent by an upper computer;
step S402: when the ith test information is received, the state control of each of the N driving modules is performed based on the ith test information so as to perform the ith fault injection test for the tested circuit.
It should also be noted that in this application relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of function in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
The principles and embodiments of the present invention are described in this application by applying specific examples, and the description of the above examples is only for helping to understand the technical solution of the present invention and its core ideas. It should be noted that it will be apparent to those skilled in the art that the present invention may be modified and practiced without departing from the spirit of the present invention.

Claims (15)

1. A fault injection circuit, comprising:
The power supply module is respectively connected with the upper computer and the tested circuit and is used for receiving the power supply of the upper computer and supplying power to the tested circuit after the voltage class conversion;
the controller is connected with the upper computer and is used for sequentially receiving K items of test information sent by the upper computer, and when the ith item of test information is received, the state control of each of the N driving modules is carried out based on the ith item of test information so as to carry out the ith fault injection test for the tested circuit;
the N driving modules are connected with the controller at the input ends, the N driving modules are connected with the tested circuit at the output ends, and any 1 driving module is used for the tested circuit; the control of the controller is in a high-resistance state, or the control of the controller is in a high-level state at the output end of the controller, or the control of the controller is in a low-level state at the output end of the controller;
n is a positive integer, K is a positive integer, and i is a positive integer and is equal to or more than 1 and equal to or less than K.
2. The fault injection circuit according to claim 1, wherein the circuit structures of the N driving modules are the same, and a power supply terminal is provided in each driving module for connection with the power supply module, so that under the control of the controller, the output terminal of the driving module is set to be in a high level state by the received power supply of the power supply module, and a ground terminal is provided in each driving module for grounding, so that under the control of the controller, the output terminal of the driving module is set to be in a low level state by the grounding of the ground terminal.
3. The fault injection circuit of claim 2, wherein any 1 of the drive modules is a switch tube, resistor and gate based drive module, and at least 1 switch tube is connected to the power module, at least 1 switch tube is grounded, and the gate is configured to: and the on-off state of each switching tube in the driving module is controlled by matching with the output signal of the controller, so that the driving module is in a high-resistance state, or the output end is in a high-level state, or the output end is in a low-level state under the control of the controller.
4. A fault injection circuit according to claim 3, wherein any 1 of the drive modules comprises: the switching circuit comprises a first switching tube, a second switching tube, a third switching tube, a first resistor, a second resistor and a NOR gate circuit;
the first end of the first switch tube is used as a power end of the driving module and is connected with the power module so as to receive power supply of the power module; the second end of the first switch tube is connected with the first end of the first resistor; the control end of the first switching tube is connected with the first input end of the NOR gate circuit, and the connection end is used as an enabling end of the driving module;
The second end of the first resistor is connected with the first end of the second switching tube, the second end of the second switching tube is connected with the first end of the second resistor, and the connecting end is used as the output end of the driving module;
the second end of the second resistor is connected with the first end of the third switching tube, the second end of the third switching tube is grounded, the control end of the third switching tube is respectively connected with the control end of the second switching tube and the output end of the NOR gate circuit, and the second input end of the NOR gate circuit is used as the input end of the driving module;
the enabling end of the driving module and the input end of the driving module are connected with the controller, and when the controller controls the enabling end of the driving module to be in a high-level state, the driving module is in a high-resistance state; when the controller controls the enabling end of the driving module to be in a low level, the driving module is in an enabling state, and in the enabling state, the level state of the output end of the driving module is consistent with the level state of the input end of the driving module.
5. The fault injection circuit of claim 4, wherein for any 1 of the drive modules, the drive modules further comprise:
Each first resistor branch comprises 1 resistor and a first controllable switch connected in series with the resistor, and the on-off states of the x first controllable switches are controlled by the controller so as to allow the controller to adjust the driving capability of the driving module when the output end is in a high level state; wherein x is a positive integer.
6. The fault injection circuit of claim 4, wherein for any 1 of the drive modules, the drive modules further comprise:
y second resistor branches connected in parallel with the second resistor, wherein each second resistor branch comprises 1 resistor and a second controllable switch connected in series with the resistor, and the on-off states of the y second controllable switches are controlled by the controller so as to allow the controller to adjust the driving capability of the driving module when the output end is in a low level state; wherein y is a positive integer.
7. The fault injection circuit of claim 1, wherein the power module is specifically configured to:
receiving power supply of the upper computer and providing power supply of z different voltage levels for the tested circuit after reducing the voltage to z different voltage levels; z is a positive integer not less than 2.
8. The fault injection circuit of claim 7, wherein the power supply module power supply alert signal pin and the z power supply enable signal pins are each connected to the controller, the controller further configured to:
when the power supply alarm signal pins of the power supply module are detected to send an alarm, the power supply module is turned off through z power supply enabling signal pins, N driving modules are controlled to be in a high-resistance state, and the current fault injection test is ended.
9. The fault injection circuit of claim 7, wherein z power normal signal pins of the power module are each connected to the controller, the controller further configured to:
when the j-th power normal signal pin of the power supply module is detected to be in a failure state, the j-th voltage class output of the power supply module is closed through the j-th power enable signal pin, and all driving modules receiving the j-th voltage class power supply of the power supply module are controlled to be in a high-resistance state; j is a positive integer and 1.ltoreq.j.ltoreq.z.
10. The fault injection circuit of claim 1, wherein the controller is coupled to the host computer via a universal serial bus connector and a protocol converter;
The universal serial bus connector is respectively connected with the upper computer and the protocol converter, and is used for: transmitting the test instruction sent by the upper computer to the protocol converter;
the protocol converter is connected with the controller, and is used for: receiving a test instruction sent by the universal serial bus connector and sending the test instruction to the controller after converting the test instruction into a first format;
wherein the first format is an instruction format supported by the controller.
11. The fault injection circuit of claim 1, wherein for any 1 of the N driver modules, the output of the driver module is connected to a designated location of the circuit under test through a crossover resistor, and the distance of the crossover resistor from the designated location is below a preset distance threshold.
12. The fault injection circuit of claim 1, further comprising a monitor and recording circuit for:
and when the controller performs the ith fault injection test for the tested circuit, monitoring and recording circuit indexes at preset positions of the tested circuit.
13. The fault injection circuit according to any one of claims 1 to 12, wherein a reserved interface is provided on the controller, the controller is connected to a motherboard where the circuit under test is located through the reserved interface, and the controller and the N driving modules are all provided on the motherboard;
the controller is further configured to: and sequentially receiving K items of test information sent by the main board through the reserved interface, and carrying out respective state control of N driving modules based on the ith item of test information when the ith item of test information is received so as to carry out the ith item of fault injection test for the tested circuit.
14. A fault injection test method, applied to the controller in the fault injection circuit according to any one of claims 1 to 13, comprising:
sequentially receiving K items of test information sent by an upper computer;
when the ith test information is received, the state control of each of the N driving modules is carried out based on the ith test information so as to carry out the ith fault injection test for the tested circuit.
15. A test apparatus comprising a fault injection circuit as claimed in any one of claims 1 to 13.
CN202311660434.XA 2023-12-06 2023-12-06 Test equipment, fault injection circuit and fault injection test method Active CN117370094B (en)

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Publication number Priority date Publication date Assignee Title
US20050050393A1 (en) * 2003-08-26 2005-03-03 Chakraborty Tapan J. Fault injection method and system
CN105353755A (en) * 2015-12-15 2016-02-24 中国航空工业集团公司北京长城航空测控技术研究所 Multifunctional fault injection device based on PXI bus
CN115407744A (en) * 2022-07-01 2022-11-29 哈尔滨工业大学（威海） Multi-protocol bus fault injection system and control method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050050393A1 (en) * 2003-08-26 2005-03-03 Chakraborty Tapan J. Fault injection method and system
CN105353755A (en) * 2015-12-15 2016-02-24 中国航空工业集团公司北京长城航空测控技术研究所 Multifunctional fault injection device based on PXI bus
CN115407744A (en) * 2022-07-01 2022-11-29 哈尔滨工业大学（威海） Multi-protocol bus fault injection system and control method thereof

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