CN117369306A - JTAG simulator of self-adaptive IO level - Google Patents
JTAG simulator of self-adaptive IO level Download PDFInfo
- Publication number
- CN117369306A CN117369306A CN202311479712.1A CN202311479712A CN117369306A CN 117369306 A CN117369306 A CN 117369306A CN 202311479712 A CN202311479712 A CN 202311479712A CN 117369306 A CN117369306 A CN 117369306A
- Authority
- CN
- China
- Prior art keywords
- level
- jtag
- circuit
- target board
- power supply
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004088 simulation Methods 0.000 claims abstract description 31
- 238000001514 detection method Methods 0.000 claims abstract description 12
- 230000003044 adaptive effect Effects 0.000 claims description 12
- 230000006978 adaptation Effects 0.000 abstract description 7
- 238000006243 chemical reaction Methods 0.000 abstract description 6
- 238000010586 diagram Methods 0.000 description 5
- 230000009471 action Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Landscapes
- Tests Of Electronic Circuits (AREA)
Abstract
The invention provides a JTAG simulator of self-adaptive IO level, which comprises: a JTAG simulation circuit which outputs a JTAG signal of a predetermined level through an output terminal; a JTAG connector for connection with a target board; the signal input end of the level switching circuit is connected with the output end of the JTAG simulation analog circuit, the signal output end of the level switching circuit is connected with the JTAG connector, and the level switching circuit comprises a plurality of level switching circuits; and the input end of the IO level detection circuit is connected with the Vref pin of the target board through the JTAG connector, and the output end of the IO level detection circuit is connected with the IO level input end of the JTAG simulation analog circuit and is used for detecting the IO level of the target board. Compared with the prior art, the invention automatically removes the adaptation level conversion circuit through the IO level of the target board, does not need to manually wire or manually find the adaptation board, and avoids the error risk.
Description
[ field of technology ]
The invention relates to the technical fields of chip design, EVB board (development board) debugging and product circuit board debugging, in particular to a JTAG (Joint Test Action Group, joint test action organization) simulator with self-adaptive IO level.
[ background Art ]
The chip design department and the board-level application product department often encounter IO level differences of the main chip due to different application situations, and common IO levels of the chips are 1.8V,2.5V,3.3V,5V and the like. Different chip IO levels and JTAG debugging need to be matched with different simulators or additional level conversion circuit boards. Misplug or misaccessing emulators of different levels can result in chip or emulator damage.
Fig. 1 is a schematic diagram of a JTAG emulator and a chip configuration with different IO levels in the prior art. In the technical scheme shown in fig. 1, an emulator is adapted for each IO level, which is very complex and costly, and it is also problematic whether most companies can find an appropriate adapting emulator or not by directly buying a finished emulator.
Fig. 2 is a schematic diagram of another JTAG emulator in the prior art and a chip configuration with different IO levels. Currently, the technical solution shown in fig. 2 is more applied to the market, only one simulator (such as 3.3V IO) is purchased, and the rest is transferred by the level transfer board. The level switching board is divided (namely, a board with 3.3V to 1.8V, a switching board with 3.3V to 2.5V, etc.), and also is integrally formed on a board (namely, all kinds of level switches are formed on a board, and then the switching mode is confirmed by a jumper wire mode). The proposal is economical, but does not solve the risk of wrong connection of the burning plates at all, and the jump connection is carried out between the conversion plates, so that the risk of poor contact is also present.
Therefore, a new solution is needed to solve the above problems.
[ invention ]
One of the purposes of the invention is to provide a JTAG simulator with self-adaptive IO level, which automatically removes the adaptation level conversion circuit through the IO level of the target board, does not need to manually wire or manually find the adaptation board, and avoids the error risk.
According to one aspect of the present invention, there is provided a JTAG emulator for adapting IO levels, comprising: the JTAG simulation circuit comprises an IO level input end, a first enabling signal output end and a JTAG signal output end, and is used for simulating the whole JTAG time sequence and outputting a JTAG signal with a preset level through the JTAG signal output end; a JTAG connector for connection with a target board; the level switching circuit comprises an enabling end, a signal input end and a signal output end, wherein the enabling end of the level switching circuit is connected with the first enabling signal output end of the JTAG simulation analog circuit, the signal input end of the level switching circuit is connected with the JTAG signal output end of the JTAG simulation analog circuit, the signal output end of the level switching circuit is connected with the JTAG connector, the level switching circuit comprises various level switching circuits, each level switching circuit is used for switching the level of a JTAG signal output by the JTAG simulation analog circuit from the preset level to another corresponding level, and when the level switching circuit works, only one level switching circuit is selected as the current level switching circuit; and the IO level detection circuit is used for detecting the IO level of the target board based on the Vref pin and outputting the detected IO level of the target board to the JTAG simulation analog circuit.
Compared with the prior art, the invention automatically removes the adaptation level conversion circuit through the IO level of the target board, does not need to manually wire or manually find the adaptation board, and avoids the error risk.
[ description of the drawings ]
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. Wherein:
FIG. 1 is a schematic diagram of a JTAG emulator and chip collocation with different IO levels in the prior art;
FIG. 2 is a schematic diagram of a functional circuit of another JTAG emulator and a chip arrangement with different IO levels according to the prior art;
FIG. 3 is a functional circuit schematic of the JTAG emulator of the adaptive IO level in one embodiment of the present invention.
[ detailed description ] of the invention
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention will be rendered by reference to the appended drawings and appended detailed description.
Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Unless specifically stated otherwise, the terms coupled, connected, or connected, as used herein, mean either direct or indirect connection, such as a and B, and include both direct electrical connection of a and B, and connection of a to B through electrical components or circuitry.
In the description of the present invention, it should be understood that the terms "upper", "lower", "front", "rear", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, are merely for convenience in describing the present invention and simplifying the description, and do not indicate or imply that the device or element in question must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present invention.
Referring to FIG. 3, a functional circuit diagram of a JTAG emulator with adaptive IO levels according to an embodiment of the present invention is shown. JTAG emulator 100, which is shown in FIG. 3, includes JTAG emulation analog circuitry 110, JTAG connector 120, level shifter circuitry 130, IO level detection circuitry 140, and VCC supply selection circuitry 150.
JTAG emulation simulation circuit 110 includes IO level input terminal 1, first enable signal output terminal 2, and JTAG signal output terminal 3, JTAG emulation simulation circuit 110 simulates the entire JTAG timing sequence, and outputs a predetermined level JTAG signal through JTAG signal output terminal 3 thereof. In the particular embodiment shown in FIG. 3, the predetermined level of JTAG signals output by JTAG emulation analog circuitry 110 is 3.3V; JTAG emulation analog circuitry 110 includes MCU (Microcontroller Unit, i.e., micro control unit) circuitry (not shown).
JTAG connector 120 is used for connection with a target board (not shown). The level shifter circuit 130 includes an enable terminal 5, a signal input terminal 6, and a signal output terminal 7, the enable terminal 5 of the level shifter circuit 130 is connected to the first enable signal output terminal 2 of the JTAG emulation analog circuit 110, the signal input terminal 6 thereof is connected to the JTAG signal output terminal 3 of the JTAG emulation analog circuit 110, the signal output terminal 7 thereof is connected to the JTAG connector 120, and the level shifter circuit 130 includes various level shifter circuits (not shown) each for shifting the level of the JTAG signal output from the JTAG emulation analog circuit 110 from a predetermined level to a corresponding other level. In operation, the level shifter circuit 130 selects only one level shifter circuit as the current level shifter circuit.
The input end 8 of the IO level detection circuit 140 is connected to the Vref pin of the target board through the JTAG connector 120, the output end 9 thereof is connected to the IO level input end 1 of the JTAG emulation analog circuit 110, and the IO level detection circuit 140 detects the IO level of the target board based on the Vref pin and outputs the detected IO level of the target board to the JTAG emulation analog circuit 110.
The JTAG emulation analog circuit 110 outputs a corresponding first enable signal EN1 to the level shifter circuit 130 based on the IO level of the target board detected by the IO level detection circuit 140; the level shifter circuit 130 selects a corresponding one of the plurality of level shifter circuits as a current level shifter circuit based on the first enable signal EN 1.
The enable terminal 10 of the VCC power supply selection circuit 150 is connected to the second enable signal output terminal 4 of the JTAG emulation analog circuit 110, and the output terminal 11 thereof is connected to the VCC pin of the target board via the JTAG connector 120. The VCC power supply selection circuit 150 includes power supply and current limiting circuits, and is not powered by default, and is powered externally only after being enabled.
The power supply voltage output by the VCC power supply selection circuit 150 is optional, and the JTAG emulation analog circuit 110 outputs a corresponding second enable signal EN2 to the VCC power supply selection circuit 150 based on the IO level of the target board detected by the IO level detection circuit 140; the VCC power supply selection circuit 150 selects and outputs a corresponding power supply voltage to the VCC pin of the target board based on the second enable signal EN2 to supply power to the target board.
In the embodiment shown in fig. 3, JTAG emulation analog circuit 110 is connected to PC (Personal Computer, i.e., host) 200. In the particular embodiment shown in FIG. 3, JTAG emulation simulation circuitry 110 is coupled to PC200 via a USB interface.
There are some target boards, and for reasons such as pin saving (i.e. pins) or physical interface mode, there is no Vref pin, where the IO level of the target board needs to be measured manually (or known in advance), and then command control is performed by the PC (i.e. host) 200, or manual control (e.g. dial switch) may be performed on the hardware board. Similarly, VCC power supply is also an option, can be automatically controlled, can be manually controlled and is relatively flexible.
In one embodiment of the present invention, the IO level of the target board is input to PC (i.e., host) 200; the PC (i.e. host) 200 outputs a corresponding control command to the JTAG emulation analog circuit 110 based on the input IO level of the target board; JTAG emulation simulation circuit 110 outputs corresponding first enable signal EN1 to level shifter circuit 130 based on the control instruction; the level shifter circuit 130 selects a corresponding one of the plurality of level shifter circuits as a current level shifter circuit based on the first enable signal EN 1. Accordingly, the JTAG emulation analog circuit 210 may output the corresponding second enable signal EN2 to the VCC power supply selection circuit 150 based on the control instruction output by the PC (i.e., host) 200; the VCC power supply selection circuit 150 selects and outputs a corresponding power supply voltage to the VCC pin of the target board based on the second enable signal EN2 to supply power to the target board.
In one embodiment of the present invention, the IO level of the target board is manually input to JTAG emulation simulation circuit 110 through a hardware board (not shown); JTAG simulation circuit 110 outputs a corresponding first enable signal EN1 to level shifter circuit 130 based on the IO level of the target board input manually; the level shifter circuit 130 selects a corresponding one of the plurality of level shifter circuits as a current level shifter circuit based on the first enable signal EN 1. Accordingly, the JTAG emulation analog circuit 210 may output the corresponding second enable signal EN2 to the VCC power supply selection circuit 150 based on the IO level of the target board input manually; the VCC power supply selection circuit 150 selects and outputs a corresponding power supply voltage to the VCC pin of the target board based on the second enable signal EN2 to supply power to the target board.
In one embodiment of the present invention, the VCC power supply selection circuit 150 outputs each power supply voltage selectable by the VCC power supply selection circuit to the VCC pin of the target board one by one from the minimum voltage to see whether the target board is normally started; if the target board is normally started, the VCC power supply selection circuit 150 continuously supplies power to the VCC pin of the target board with the currently output power supply voltage.
In some applications, the above-mentioned functions related to the power supply of the VCC power supply selection circuit 150 may be preserved if the emulator is not required to supply power to the target board.
In summary, the JTAG simulator with the self-adaptive IO level has the following advantages:
1. all JTAG share one simulator, so that the instrument cost is reduced, and the management cost is reduced.
2. Through the IO level of the target board, the level conversion circuit is automatically removed and adapted, manual wiring or manual matching board searching is not needed, and the board burning risk is reduced
3. Through the IO level of the target plate, the VCC is automatically unadapted to supply power to the outside;
4. IO level sensing (or detection) is optional, flexible in application and more refined in adaptation to different project requirements.
It should be noted that any modifications to the specific embodiments of the invention may be made by those skilled in the art without departing from the scope of the invention as defined in the appended claims. Accordingly, the scope of the claims of the present invention is not limited to the foregoing detailed description.
Claims (10)
1. A JTAG emulator for adaptive IO levels, comprising:
the JTAG simulation circuit comprises an IO level input end, a first enabling signal output end and a JTAG signal output end, and is used for simulating the whole JTAG time sequence and outputting a JTAG signal with a preset level through the JTAG signal output end;
a JTAG connector for connection with a target board;
the level switching circuit comprises an enabling end, a signal input end and a signal output end, wherein the enabling end of the level switching circuit is connected with the first enabling signal output end of the JTAG simulation analog circuit, the signal input end of the level switching circuit is connected with the JTAG signal output end of the JTAG simulation analog circuit, the signal output end of the level switching circuit is connected with the JTAG connector, the level switching circuit comprises various level switching circuits, each level switching circuit is used for switching the level of a JTAG signal output by the JTAG simulation analog circuit from the preset level to another corresponding level, and when the level switching circuit works, only one level switching circuit is selected as the current level switching circuit;
and the IO level detection circuit is used for detecting the IO level of the target board based on the Vref pin and outputting the detected IO level of the target board to the JTAG simulation analog circuit.
2. The adaptive IO level JTAG emulator of claim 1, wherein,
the JTAG simulation circuit outputs a corresponding first enabling signal EN1 to the level switching circuit based on the IO level of the target board detected by the IO level detection circuit;
the level shifter circuit selects a corresponding one of the plurality of level shifter circuits as the current level shifter circuit based on the first enable signal EN 1.
3. The adaptive IO level JTAG emulator of claim 2, further comprising a VCC power supply selection circuit,
the enabling end of the VCC power supply selection circuit is connected with the second enabling signal output end of the JTAG simulation circuit, and the output end of the VCC power supply selection circuit is connected with the VCC pin of the target board through the JTAG connector;
the power supply voltage output by the VCC power supply selection circuit is selectable.
4. The JTAG emulator with adaptive IO levels of claim 3,
the JTAG simulation circuit outputs a corresponding second enabling signal EN2 to the VCC power supply selection circuit based on the IO level of the target board detected by the IO level detection circuit;
the VCC power supply selection circuit selects and outputs a corresponding power supply voltage to a VCC pin of the target board based on the second enable signal EN 2.
5. The adaptive IO level JTAG emulator of claim 4, wherein,
the JTAG simulation circuit is connected with the host,
inputting the IO level of the target board into the host;
the host outputs a corresponding control instruction to the JTAG simulation analog circuit based on the input IO level of the target board;
the JTAG simulation circuit outputs a corresponding first enable signal EN1 to the level switching circuit based on the control instruction;
the level shifter circuit selects a corresponding one of the plurality of level shifter circuits as the current level shifter circuit based on the first enable signal EN 1.
6. The adaptive IO level JTAG emulator of claim 5, wherein,
the JTAG simulation circuit outputs a corresponding second enabling signal EN2 to the VCC power supply selection circuit based on the control instruction;
the VCC power supply selection circuit selects and outputs a corresponding power supply voltage to a VCC pin of the target board based on the second enable signal EN 2.
7. The JTAG emulator with adaptive IO levels of claim 4,
manually inputting the IO level of the target board to the JTAG simulation analog circuit through a hardware board;
the JTAG simulation circuit outputs a corresponding first enabling signal EN1 to the level switching circuit based on the IO level of the target board which is input manually;
the level shifter circuit selects a corresponding one of the plurality of level shifter circuits as the current level shifter circuit based on the first enable signal EN 1.
8. The adaptive IO level JTAG emulator of claim 7, wherein,
the JTAG simulation circuit outputs a corresponding second enabling signal EN2 to the VCC power supply selection circuit based on the IO level of the target board which is manually input;
the VCC power supply selection circuit selects and outputs a corresponding power supply voltage to a VCC pin of the target board based on the second enable signal EN 2.
9. An adaptive IO level JTAG emulator as claimed in claim 3, wherein,
the VCC power supply selection circuit outputs selectable power supply voltages to VCC pins of the target board one by one from the minimum voltage to see whether the target board is normally started,
and if the target board is normally started, the VCC power supply selection circuit continuously supplies power for the VCC pin of the target board by using the currently output power supply voltage.
10. The JTAG emulator with adaptive IO levels of claim 5,
the preset level of JTAG signals output by the JTAG simulation analog circuit is 3.3V;
and the JTAG simulation circuit is connected with the host computer through a USB interface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311479712.1A CN117369306A (en) | 2023-11-07 | 2023-11-07 | JTAG simulator of self-adaptive IO level |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311479712.1A CN117369306A (en) | 2023-11-07 | 2023-11-07 | JTAG simulator of self-adaptive IO level |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117369306A true CN117369306A (en) | 2024-01-09 |
Family
ID=89398306
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311479712.1A Pending CN117369306A (en) | 2023-11-07 | 2023-11-07 | JTAG simulator of self-adaptive IO level |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117369306A (en) |
-
2023
- 2023-11-07 CN CN202311479712.1A patent/CN117369306A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7312614B2 (en) | Commutator for power supply testing | |
| US8607081B2 (en) | Power control for PXI express controller | |
| US8745297B2 (en) | Load card for testing peripheral component interconnect slots | |
| US20200225296A1 (en) | Display module test platform | |
| US8441273B2 (en) | Testing card and testing system for USB port | |
| CN111881074A (en) | Electronic system, host device and control method | |
| CN111983427B (en) | 16-channel analog switch circuit testing system and testing method | |
| CN110618744A (en) | Novel GPU Carrier board card | |
| CN101184310A (en) | Test device for mobile phone | |
| CN117369306A (en) | JTAG simulator of self-adaptive IO level | |
| CN219225516U (en) | Time-sharing multiplexing circuit for multiplexing pins | |
| CN102479064B (en) | display, mouse and keyboard switching device | |
| CN102468582A (en) | Video graphics array (VGA) interface switching device | |
| CN100555180C (en) | The keyboard of tool multiple output function | |
| TWI396356B (en) | Adaptation circuit of power supply | |
| TW201704997A (en) | Debugging system and control method thereof | |
| CN220933447U (en) | Multifunctional expansion board based on COM-Express | |
| US11933842B2 (en) | Board adapter device, test method, system, apparatus, and device, and storage medium | |
| CN111179800B (en) | Display device driving system and electronic apparatus | |
| CN214586453U (en) | Circuit and device compatible with USB and I2C | |
| CN212433752U (en) | Communication voltage self-adaptive chip simulator circuit | |
| CN219225510U (en) | MCU hardware fault-based testing device | |
| KR100205608B1 (en) | Microcontroller developing system | |
| CN111782247B (en) | Upgrading system for power supply of burner | |
| US20230116296A1 (en) | Modular System Validation Platform for Computing Devices |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |