CN117353747B - Switched capacitor array applied to high-speed high-precision SAR ADC - Google Patents
Switched capacitor array applied to high-speed high-precision SAR ADC Download PDFInfo
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- CN117353747B CN117353747B CN202311452826.7A CN202311452826A CN117353747B CN 117353747 B CN117353747 B CN 117353747B CN 202311452826 A CN202311452826 A CN 202311452826A CN 117353747 B CN117353747 B CN 117353747B
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- 239000003990 capacitor Substances 0.000 title claims abstract description 113
- 238000005070 sampling Methods 0.000 claims abstract description 40
- 238000006243 chemical reaction Methods 0.000 claims abstract description 17
- 230000007704 transition Effects 0.000 claims description 7
- 230000003071 parasitic effect Effects 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 6
- 238000012986 modification Methods 0.000 description 4
- 230000004048 modification Effects 0.000 description 4
- 230000004075 alteration Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/34—Analogue value compared with reference values
- H03M1/38—Analogue value compared with reference values sequentially only, e.g. successive approximation type
- H03M1/46—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter
- H03M1/466—Analogue value compared with reference values sequentially only, e.g. successive approximation type with digital/analogue converter for supplying reference values to converter using switched capacitors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
Abstract
The invention discloses a switch capacitor array applied to a high-speed high-precision SAR ADC, which belongs to the technical field of capacitors of SAR ADCs, and adopts a bridging structure to reduce the total capacitance area, and comprises the following components: sampling capacitor C x[n‑1] ，C x[n‑2] ，C x[n‑3] ，C x[n‑4] Non-sampling capacitor C z[n‑5] ，C y[n‑i] ，C y[n‑i‑1] ，C y[n‑i‑2] ，C z[n‑i‑3] And redundant bit capacitance C zr[n‑4] 、C zr[n‑i‑2] . The problem of the reference level establishment speed of a large capacitor part in the switch capacitor array is optimized by emphasis, and the problem of the accuracy of the large capacitor during rapid establishment is relieved by combining a redundant capacitor, so that the total capacitor can be obviously reduced in area compared with the traditional scheme, and the conversion speed can be allowed to be faster.
Description
Technical Field
The invention belongs to the technical field of capacitors of SAR ADC, and particularly relates to a switch capacitor array applied to a high-speed high-precision SAR ADC.
Background
The input rail-to-rail ADC (analog to digital converter) has the largest input range and is widely used in measurement and other applications. To fit the input range, its reference Voltage (VREF) is typically tapped off from an off-chip reference source to obtain a precise reference level close to the supply voltage. The speed of the capacitor array DAC (digital to analog converter) in the ADC is limited by the parasitic inductance and parasitic resistance of the chip pins. The conventional scheme needs to place a large-size decoupling capacitor on the chip, which is similar to the area of the ADC itself, and also needs to put high requirements on the packaging of the chip.
FIG. 1 is a diagram of a conventional high-precision SAR ADC capacitor array, which requires higher precision in establishing the switch capacitor due to higher precision of the SAR ADC; meanwhile, as the precision of the SAR ADC is high, the value of the unit capacitor of the SAR ADC can be larger, for example, the sampling capacitor of the 16bit ADC can reach a capacitor of tens of pF, the MSB (most significant bit) bit of the SAR ADC is more than 5pF, the large current can be pulled to the external reference voltage in the process of establishing the large capacitor, and the disturbance voltage is generated through the parasitic inductance of the package, so that the voltage on the DAC needs to be established for a long time. The conventional solution would put a large area decoupling capacitance on the chip up to the nF level and require a sufficiently small package inductance on the reference voltage pin, thus increasing the package cost.
Disclosure of Invention
The invention aims to provide a switch capacitor array for a high-speed high-precision SAR ADC (analog to digital converter) so as to solve the problem of establishing speed of a reference level of a large capacitor part in a key optimization capacitor array, and relieve the problem of precision when the large capacitor is established quickly by combining a redundant capacitor.
In order to achieve the above purpose, the present invention provides the following technical solutions: a switched capacitor array for use in a high speed, high accuracy SAR ADC that employs a bridge structure to reduce the total capacitive area, the switched capacitor array comprising: sampling capacitor C x[n-1] ，C x[n-2] ，C x[n-3] ，C x[n-4] Non-sampling capacitor C z[n-5] ，C y[n-i] ，C y[n-i-1] ，C y[n-i-2] ，C z[n-i-3] And redundant bit capacitance C zr[n-4] 、C zr[n-i-2] ；
Sampling capacitor comprising DAC capacitor C xn[n-1] ，C xp[n-1] Sampling switch S in[n-1] ，S ip[n-1] High-precision reference switch S vn[n-1] ，S vp[n-1] Fast change-over switch S cn[n-1] ，S cp[n-1] Self-contained DAC capacitor C xn[n-1] /C xp[n-1] Corresponding reference voltage storage capacitor C r[n-1] Storage capacitor switch S rn ，S rp DAC capacitor top plate switch S tp ，S tn ；
Redundant bit capacitance including DAC capacitance C zn[n-j] ，C zp[n-j] Common mode switch S in[n-j] ，S ip[n-j] High-precision reference switch S vn[n-j] ，S vp[n-j] DAC capacitor top plate switchS tp ，S tn 。
Preferably, in the switched capacitor array, the capacitor C is not sampled z[n-5] ，C y[n-i] ，C y[n-i-1] ，C y[n-i-2] ，C z[n-i-3] And sampling capacitor C x[n-1] ，C x[n-2] ，C x[n-3] ，C x[n-4] Is distinguished by a sampling switch S in[n-1] ，S ip[n-1] Is connected to VCM level instead of input signal V inp /V inn 。
Preferably, DAC capacitance C xn[n-1] /C xp[n-1] Capacitance value of 2 n-1 * Cu, cu is the unit capacitance of the SAR ADC.
Preferably, in the switched capacitor array, the redundant bit capacitor C zr[n-4] Capacitance value of (C) and common switch capacitance C z[n-4] The capacitance value of (C) is the same and the common switch capacitance is C z[n-5] C (C) B The former switch has the structure similar to C zr[n-4] And consistent.
Preferably, in the switched capacitor array, the redundant bit capacitor C zr[n-i-3] And the capacitance and redundancy bit capacitance C therebehind zr[n-4] Is consistent in structure.
Compared with the prior art, the invention has the beneficial effects that:
the invention has the integral idea that the load on the reference voltage can be reduced by using fast conversion and matching with the redundant capacitor when the large capacitor is converted. Fast switching is not only used on sampling capacitance, but also due to bridging capacitance C B The latter capacitance is also typically large in size, so this fast switching mode is also used.
Taking a 16bit SAR ADC as an example, the decoupling capacitance of the sampling capacitor of 10pF is usually required to reach 2nF, and the area of the decoupling capacitance is usually larger than the size of the SAR ADC. The Cr capacitor is added in the structure, but the capacitance value is about 0.3nF, and the total capacitance of 0.8nF can be obviously reduced in area compared with the traditional scheme only by matching with the decoupling capacitor of 0.5nF, and the conversion speed can be allowed to be faster.
Drawings
Fig. 1 is a circuit diagram of a conventional high-precision capacitor array.
Fig. 2 is a schematic diagram of a capacitor array circuit according to the present application.
Fig. 3 is a schematic diagram of the capacitor Cx involved in sampling and its switching circuit.
Fig. 4 is a schematic diagram of a capacitor Cy without taking part in sampling, wherein the switch band switches the circuit rapidly.
Fig. 5 is a schematic diagram of a capacitor Cz without a fast changeover switch circuit for the switch without taking part in the sampling.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
As shown in fig. 2, a switched capacitor array applied to a high-speed high-precision SAR ADC adopts a bridge structure to reduce the total capacitance area, which is schematically shown as a single-sided part in the figure, and the other side of the differential structure is the same as the second side of the figure, and the switched capacitor array includes: sampling capacitor C x[n-1] ，C x[n-2] ，C x[n-3] ，C x[n-4] Non-sampling capacitor C z[n-5] ，C y[n-i] ，C y[n-i-1] ，C y[n-i-2] ，C z[n-i-3] And redundant bit capacitance C zr[n-4] 、C zr[n-i-2] ；
As shown in fig. 3, the switch capacitor includes DAC capacitor C xn[n-1] ，C xp[n-1] Sampling switch S in[n-1] ，S ip[n-1] High-precision reference switch S vn[n-1] ，S vp[n-1] Fast change-over switch S cn[n-1] ，S cp[n-1] Self-contained DAC capacitor C xn[n-1] /C xp[n-1] Corresponding reference voltage storage capacitor C r[n-1] Storage capacitor switch S rn ，S rp DAC capacitor top plate switch S tp ，S tn . DAC capacitor C xn[n-1] /C xp[n-1] Capacitance value of 2 n-1 * Cu, cu is the unit capacitance of the SAR ADC.
As shown in FIG. 2, C zr[n-4] Is the redundant bit capacitance of the SAR ADC, whose switched capacitor structure is shown in fig. 5. The switch capacitor is of a traditional switch capacitor structure and comprises a DAC capacitor C zn[n-j] ,C zp[n-j] Common mode switch S in[n-j] ,S ip[n-j] High-precision reference switch S vn[n-j] ,S vp[n-j] DAC capacitance roof switch S tp ，S tn 。
As shown in FIG. 2, C zr[n-4] Capacitance value of (C) and C z[n-4] The capacitance values are the same. C (C) z[n-5] Isocenter C B The former switch has the structure similar to C zr[n-4] And consistent.
As shown in FIG. 2, C y[n-i] To C y[n-i-2] Is a fast transfer switch which does not participate in sampling. The difference from the switch of fig. 3 is its sampling switch S in[n-1] ,S ip[n-1] Is connected to VCM level instead of input signal V inp /V inn 。
As shown in FIG. 2, C zr[n-i-2] Is the redundant bit capacitance that remains for the SAR ADC as shown in fig. 5. C in FIG. 2 zr[n-i-3] And the capacitance thereof is shown in fig. 5.
As shown in fig. 3-5, the switched capacitor array is divided into 3 types of switched capacitors, and the rapid switching switched capacitors respectively participating in sampling are denoted as C x (FIG. 3), fast switching capacitor memory C not participating in sampling y (FIG. 4), common capacitor C z (FIG. 5).
For C x There are 3 phases, respectively:
sampling phase is controlled by sampling switch S in[n-1] /S ip[n-1] Connecting capacitive backplane to input signal V inp /V inn And reference level storage capacitor C r[n-1] Also through S rp ，S rn Switch closure to connect to reference level V RP /V RN Applying;
during fast phase transition, the backplane switch is connected to C r[n-1] As reference signals, it builds up at a much faster rate than conventional reference levels due to the fact that only charge transfer is involved and no package parasitic inductance is passed through at this time, due to the consideration of the areaProduct C r[n-1] The size is about 30 times of the corresponding DAC capacitance;
in the high-precision phase conversion, the capacitor bottom plate is connected to the reference level as in the conventional structure, and the disturbance to the reference level is much smaller at the moment due to the rapid phase conversion, so that the requirement on the external reference voltage is reduced.
For C y Also have 3 phases, and C x Except that the sampling switch is connected to the VCM at the time of sampling. Cz is a conventional switched capacitor.
The working logic of the SAR ADC switch capacitor is as follows:
c at sampling phase x[n-1] To C x[n-4] Is connected to the input signal Vin, the other switched capacitances are all connected to the VCM level.
At the transition stage, from C x[n-1] To C x[n-4] The conversion of (2) is performed by rapid conversion, so that a plurality of capacitors with the largest size can be rapidly established; when switching to C zr[n-4] At times other than C zr[n-4] Outside normal conversion, C x[n-1] To C x[n-4] Also switch to the precision switching mode at the same time, due to C zr[n-4] Is a redundant capacitor, can tolerate C x[n-1] To C x[n-4] Errors caused by insufficient storage capacitance during the fast switching phase; and C is z[n-5] C (C) B The previous transition states are all as in the conventional structure; at the transition to C y[n-i] To C y[n-i-2] Also by fast switching up to the redundant capacitance C zr[n-i-2] The accurate conversion mode is switched in when the conversion is performed.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (5)
1. The switched capacitor array for the high-speed high-precision SAR ADC adopts a bridging structure to reduce the total capacitance area, and is characterized in that the switched capacitor array comprises: sampling capacitor C x[n-1] ，C x[n-2] ，C x[n-3] ，C x[n-4] Non-sampling capacitor C z[n-5] ，C y[n-i] ，C y[n-i-1] ，C y[n-i-2] ，C z[n-i-3] And redundant bit capacitance C zr[n-4] 、C zr[n-i-2] ；
Sampling capacitor comprising DAC capacitor C xn[n-1] ，C xp[n-1] Sampling switch S in[n-1] ，S ip[n-1] High-precision reference switch S yn[n-1] ，S yp[n-1] Fast change-over switch S cn[n-1] ，S cp[n-1] Self-contained DAC capacitor C xn[n-1] /C xp[n-1] Corresponding reference voltage storage capacitor C r[n-1] Storage capacitor switch S rn ，S rp DAC capacitor top plate switch S tp ，S tn ；
Redundant bit capacitance including DAC capacitance C zn[n-j] ，C zp[n-j] Common mode switch S in[n-j] ，S ip[n-j] High-precision reference switch S vn[n-j] ，S vp[n-j] DAC capacitor top plate switch S tp ，S tn ；
The sampling capacitor has 3 phases, specifically: sampling phase, fast switching phase and high accuracy switching phase;
sampling phase is controlled by sampling switch S in[n-1] /S ip[n-1] Connecting capacitive backplane to input signal V inp /V inn And reference level storage capacitor C r[n-1] Also through S rp ，S rn Switch closure to connect to reference level V RP /V RN Applying;
during fast phase transition, the backplane switch is connected to C r[n-1] As reference signals, since only charge transfer is involved and is not passed throughThe over-package parasitic inductance is built up much faster than the conventional reference level, due to the consideration of C r[n-1] The area size of the capacitor is about 30 times of the corresponding DAC capacitor;
in the high-precision phase conversion, the capacitor bottom plate is connected to the reference level, and the disturbance to the reference level is much smaller at the moment due to the rapid phase conversion, so that the requirement on the external reference voltage is also reduced;
the non-sampling capacitor has 3 phases as well, specifically: sampling phase, fast switching phase and high accuracy switching phase;
the working logic of the SAR ADC switch capacitor is as follows:
c at sampling phase x[n-1] To C x[n-4] The bottom plate of (a) is connected to the input signal Vin, and other switch capacitors are connected to the VCM level;
at the transition stage, from C x[n-1] To C x[n-4] The conversion of (2) is performed by rapid conversion, so that a plurality of capacitors with the largest size can be rapidly established; when switching to C zr[n-4] At times other than C zr[n-4] Outside normal conversion, C x[n-1] To C x[n-4] Also switch to the precision switching mode at the same time, due to C zr[n-4] Is a redundant capacitor, can tolerate C x[n-1] To C x[n-4] Errors caused by insufficient storage capacitance during the fast switching phase; at the transition to C y[n-i] To C y[n-i-2] Also by fast switching up to the redundant capacitance C zr[n-i-2] The accurate conversion mode is switched in when the conversion is performed.
2. The switched capacitor array for a high speed high accuracy SAR ADC of claim 1, wherein: in the switched capacitor array, the non-sampling capacitor C y[n-i] ，C y[n-i-1] ，C y[n-i-2] And sampling capacitor C x[n-1] ，C x[n-2] ，C x[n-3] ，C x[n-4] Is distinguished by a sampling switch S in[n-1] ，S ip[n-1] Is connected to VCM level instead of input signal V inp /V inn 。
3. According to claimThe switched capacitor array for a high-speed high-precision SAR ADC of claim 1, wherein: DAC capacitor C xn[n-1] /C xp[n-1] Capacitance value of 2 n-1 * Cu, cu is the unit capacitance of SARADC.
4. The switched capacitor array for use in a high speed high accuracy SAR ADC of claim 2, wherein: in the switch capacitor array, a redundant bit capacitor C zr[n-4] Capacitance value of (C) and common switch capacitance C z[n-4] The capacitance value of (C) is the same and the common switch capacitance is C z[n-5] C (C) B The former switch has the structure similar to C zr[n-4] And consistent.
5. The switched capacitor array for high speed high accuracy SARADC of claim 4 wherein: in the switch capacitor array, a redundant bit capacitor C zr[n-i-3] And the capacitance and redundancy bit capacitance C therebehind zr[n-4] Is consistent in structure.
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104079298A (en) * | 2014-06-24 | 2014-10-01 | 复旦大学 | Successive approximation type analog-to-digital converter of self-calibration bridge-connection capacitor structure |
| US8902093B1 (en) * | 2012-12-05 | 2014-12-02 | Cadence Design Systems, Inc. | Parallel analog to digital converter architecture with charge redistribution and method thereof |
| CN104660264A (en) * | 2015-03-20 | 2015-05-27 | 中国电子科技集团公司第二十四研究所 | Analog-digital converter and chip of non-binary capacitor array with redundancy bit |
| CN105915220A (en) * | 2016-04-05 | 2016-08-31 | 天津大学 | Successive approximation type analog-to-digital converter with digital calibration based on one bit redundant bit |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8902093B1 (en) * | 2012-12-05 | 2014-12-02 | Cadence Design Systems, Inc. | Parallel analog to digital converter architecture with charge redistribution and method thereof |
| CN104079298A (en) * | 2014-06-24 | 2014-10-01 | 复旦大学 | Successive approximation type analog-to-digital converter of self-calibration bridge-connection capacitor structure |
| CN104660264A (en) * | 2015-03-20 | 2015-05-27 | 中国电子科技集团公司第二十四研究所 | Analog-digital converter and chip of non-binary capacitor array with redundancy bit |
| CN105915220A (en) * | 2016-04-05 | 2016-08-31 | 天津大学 | Successive approximation type analog-to-digital converter with digital calibration based on one bit redundant bit |
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