CN112653463A - Analog domain calibration method applied to SAR-ADC - Google Patents
Analog domain calibration method applied to SAR-ADC Download PDFInfo
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Abstract
The invention discloses an analog domain calibration method applied to an SAR-ADC. In the invention, only 2 logic levels need to be connected to the one-bit capacitor, which are respectively as follows: VREFP, VREFN. Compared with the traditional bottom plate sampling, the invention saves a logic switch connected with the VCM level and omits a buffer of the VCM level of the bottom plate. Based on the split capacitor array, a method for calibrating SAR-ADC errors in an analog domain is provided. The specific content comprises the following steps: firstly, adding a row of binary weighted capacitor arrays beside a capacitor to be calibrated to compensate the mismatch of the capacitor; then, the output digital codes are marked, and when the marked digital codes are detected, calibration logic is started, and compensation capacitors are switched; and finally, the calibration sequence forces the calibration from the low position to the high position, so that the calibration effectiveness is ensured.
Description
Technical Field
The invention relates to the field of integrated circuit design, in particular to a method for calibrating an analog domain of a capacitor array of a successive approximation type analog-to-digital converter SAR-ADC.
Background
With the continuous advance of integrated circuit process nodes, the advantages of successive approximation analog-to-digital converters (sar adc for short) are gradually revealed, and low power consumption and small area are one of the advantages. The demand of the current society for mobile electronic equipment is continuously reduced, and the reduction of the chip area is still a hot direction for the research of the mobile electronic equipment;
the logic switch array of the capacitor array (CDAC) in the sar ADC is part of a digital control circuit, which is composed of basic logic switch units that are repeatedly called a number of times, the number of times depending on the number of bits of the ADC. The Split-Cap-Array can reduce one logic level for each capacitor, effectively reduce logic complexity and reduce digital logic area;
the capacitance may be deviated in an actual manufacturing process, which may seriously affect the linear characteristic of the ADC and reduce the accuracy of the ADC. In high precision applications, calibration techniques are indispensable. Currently, the mainstream calibration mode in the industry is foreground calibration, error compensation is required after the ADC stops working, the defect that calibration cannot follow environmental changes is overcome by the background calibration technology.
Disclosure of Invention
The invention aims to provide an analog domain calibration method applied to SAR-ADC (synthetic aperture radar-analog converter) aiming at the defects of the prior art, which is improved on the traditional bottom plate sampling capacitor array and divides each bit capacitor into two parts. Compared with a traditional mode capacitor array in which 4 switches are arranged on a capacitor bottom plate, the number of the switches is reduced because the number of the switches is only 3; in addition, an equal weight capacitor is constructed, and conditions are provided for the calibration method of the invention.
The purpose of the invention is realized by the following technical scheme: an analog domain calibration method applied to a SAR-ADC comprises the following steps:
(1) the method comprises the steps of sampling an analog input signal and converting the analog input signal into a digital code by using a switch timing sequence based on a Split capacitor Array, wherein the Split capacitor Array comprises n main capacitors, each main capacitor is Split into two identical sub capacitors, and each main capacitor is attached with a compensation capacitor Array. The specific process of sampling and converting the analog input signal into the digital code is as follows:
(1.1) sampling the analog input signal, and transferring the information stored in the main capacitor array of the analog input signal from the bottom plate to the top plate;
(1.2) comparing the positive-end input signal VIP with the negative-end input signal VIN, and if the comparison result is 1, connecting the highest-order capacitor on the positive-end input signal VIP side with VREFP, and connecting the highest-order capacitor on the negative-end input signal VIN side with VREFN; if the comparison result is 0, the highest bit capacitance of the positive end input signal VIP side is connected with VREFN, and the highest bit capacitance of the negative end input signal VIN side is connected with VREFP;
(1.3) after comparison, if the output digital code is not the lowest bit, repeating the step (1.2); if the digital code is the lowest bit, the digital code is directly output, and finally the output digital code sequence is obtained.
(2) Recording the digital code sequence obtained in the step (1) as a mark code if the logic levels after the ith bit in the digital code sequence are all consistent, wherein the ith bit in the mark code is a calibration bit; i is 2,3,4, …, n is the number of bits of SAR-ADC; carrying out analog domain calibration on calibration bits from a low bit to a high bit; the calibration procedure for the ith bit calibration bit is as follows:
(2.1) configuring an asynchronous clock, and additionally generating two cycles for calibration, namely the total cycle number is SAR-ADC digit n + 2;
(2.2) carrying out comparison processes of the step (1.2) twice in additional two periods generated by the asynchronous clock to obtain additional two-bit digital codes, wherein the two additional comparison results determine how the compensation capacitor array is switched; the method specifically comprises the following steps: if the obtained two-digit digital codes are different, the compensation capacitor array is not switched, if the obtained two-digit digital codes are both low levels, the VIN side compensation capacitor is switched, and if the obtained two-digit digital codes are both high levels, the VIP side compensation capacitor is switched;
and (2.3) the compensation capacitor array of the ith bit capacitor is provided with a plurality of compensation capacitors, and when calibration is performed each time, one compensation capacitor is switched from a high bit to a low bit in the compensation capacitor array of the ith bit capacitor, until all the compensation capacitors are switched, the calibration of the ith bit calibration is finished.
Furthermore, the bottom plate of the sampling capacitor of the SAR-ADC is only connected with two logic levels, the VCM logic level is not required to be connected, and the top plate is only connected with one logic level VCM; the two logic levels are VREFP and VREFN.
Further, before calibration is performed, it is determined whether all the capacitors of the calibration bits before the i-th bit have been calibrated. If not, skipping the calibration of the ith calibration bit; if all the calibration is finished, the calibration of the ith calibration bit is executed.
Further, the judgment basis of the i-th calibration bit after the capacitance calibration is as follows: the compensation capacitors in the capacitance-dependent compensation capacitor array of the ith calibration bit participate in the calibration.
Furthermore, the number of the compensation capacitors in the compensation capacitor array is determined according to the capacitance value of the main capacitor, and the larger the capacitance value is, the larger the number of the compensation capacitors is.
Further, the unit capacitance of the compensation capacitor array is smaller than that of the main capacitor array.
The beneficial technical effects of the invention are as follows:
compared with the traditional bottom plate sampling capacitor array, the capacitor array applied by the invention does not need to be connected with a third level (VCM), so that: firstly, a switch MOS tube connected with a bottom plate of a capacitor and a third level is saved, and the layout and wiring complexity can be effectively reduced on the premise of repeated calling; ② the logic level often needs to be provided by a buffer circuit, which occupies a lot of power consumption. The omission of VCM means that one buffer circuit can be omitted, thereby significantly reducing power consumption;
secondly, a common-centroid structure is easier to realize on the layout by decomposing a large capacitor into smaller capacitors, so that the matching characteristic is better, and meanwhile, the wiring complexity in the layout can be reduced;
thirdly, compared with the traditional foreground digital calibration, the calibration does not need to stop the work of the ADC, and can update the calibration result in real time along with the change of the environment, thereby ensuring the effectiveness of the calibration;
fourthly, the multi-layer judgment logic is provided, so that invalid calibration is effectively avoided, and power consumption is saved;
fifthly, as mismatch compensation is carried out in the analog domain, the expense of a large number of digital circuits is avoided, and the layout area is greatly reduced.
Drawings
The principles of the present invention will now be described in detail with reference to the accompanying drawings.
FIG. 1 is a diagram of the SARADC architecture of the present invention;
FIG. 2 is a schematic diagram of a conventional bottom plate sampling logic switch array;
FIG. 3 is a schematic diagram of a logic switch array of a split bottom plate sampling capacitor array;
FIG. 4 is a flowchart of a split bottom plate sampling capacitor array operation;
FIG. 5 is a schematic diagram of the switching from the sampling phase to the charge redistribution phase;
FIG. 6 is a schematic diagram of the diverter switch after the first comparison;
FIGS. 7 and 8 are schematic diagrams of the switch after the second comparison;
fig. 9, fig. 10, fig. 11, and fig. 12 are schematic diagrams of the change-over switch after the third comparison;
FIG. 13 is a flowchart of a calibration sequence;
FIG. 14 is a schematic diagram of a main capacitor array calibration;
FIG. 15 is a timing diagram of an asynchronous clock triggered to calibrate according to the detection of a flag;
FIG. 16 illustrates the compensated capacitor array switching mechanism after triggering calibration;
FIG. 17 is a high calibration trigger mechanism;
fig. 18, 19, 20 show two extra compensation capacitor switches after triggering the calibration of the main capacitor array MSB.
Detailed Description
The present invention will be further described with reference to specific examples, but the embodiments of the present invention are not limited thereto.
A basic SAR-ADC comprises the main blocks shown in fig. 1, including differential signal inputs VIP, VIN, signal sampling switches, capacitor arrays, comparators, SAR digital logic, and digital logic switch arrays, wherein each main capacitor in the capacitor arrays is attached with a compensation capacitor array. The top plate is controlled by one logic level (VCM), while the bottom plate is controlled by three logic levels (VREFP, VREFN, VCM); as shown in fig. 3, in the present invention, each bit of capacitor is divided into two sub-capacitors with equal size, and the bottom plate is controlled by only two logic levels (VREFP, VREFN), so that the switch required for connecting the bottom plate to the VCM is eliminated. Where VCM ═ 2 (VREFP + VREFN). Fig. 4 illustrates the workflow of a split capacitor array.
Taking a bottom plate sampling technology of a 4-bit SAR-ADC as an example:
[ sampling procedure ]
During sampling, the bottom electrode plates of all capacitors are connected with input signals (the two sides of each capacitor sample VIP and VIN respectively), and the top electrode plates are connected with a third level VCM.
[ converting cycle step ]
The capacitor array switching sequence is illustrated with 4 bits as an example:
step one, charge redistribution is carried out. As shown in fig. 5, the specific operation connects the bottom plates of the two sub-capacitors included in each bit in the capacitor array to VREFP and VREFN, respectively, and the VCM switch of the top plate is turned off. At this time, the first comparison is carried out to obtain a first digit code D3. In the comparison process, if the output digital code is not the lowest bit, the comparison process is repeated; if the bit is the lowest bit, the digital code is directly output.
Step two, according to the first digit digital code D3The logic switch of the highest order capacitor is switched as a result of the comparison. As shown in FIG. 6, assume D3If the number of the capacitors is 1, two sub-capacitors of the VIP side highest-order capacitor are all connected with VREFP, and two sub-capacitors of the VIN side highest-order capacitor are all connected with VREFN; suppose D3And if the capacitance is 0, the two sub-capacitors of the VIP side highest bit capacitance are all connected to VREFN, and the two sub-capacitors of the VIN side highest bit capacitance are all connected to VREFP. At this time, the second comparison is performed to obtain a second digit code D2。
Step three, according to the second digit code D2The logic switch of the next highest capacitor is switched according to the comparison result. As shown in FIGS. 7-8, assume D2If the number of the capacitors is 1, two sub-capacitors of the VIP side secondary high-order capacitor are all connected with VREFP, and two sub-capacitors of the VIN side secondary high-order capacitor are all connected with VREFN; suppose D 20, then VIP sideTwo sub-capacitors of the sub-high-order capacitor are all connected with VREFN, and two sub-capacitors of the sub-high-order capacitor on VIN side are all connected with VREFP. At this time, a third comparison is performed to obtain a third digit code D1。
Step four, according to the third digit code D1The logic switch of the highest order capacitor is switched as a result of the comparison. As shown in FIGS. 9-12, assume D1If the number of the capacitors is 1, two sub-capacitors of the VIP side secondary low-order capacitor are all connected with VREFP, and two sub-capacitors of the VIN side secondary low-order capacitor are all connected with VREFN; suppose D1And if the voltage is 0, the two sub-capacitors of the VIP side secondary low-order capacitor are all connected to VREFN, and the two sub-capacitors of the VIN side secondary low-order capacitor are all connected to VREFP. At this time, the fourth comparison is performed to obtain a fourth digit code D0。
Step five, obtaining a four-digit digital code D3 D2 D1 D0And saved in a register for output.
And step six, after the digital code converted from the analog value sampled at the moment is output, waiting for the arrival of the next sampling moment.
[ CALIBRATION STEP ]
As shown in fig. 13, a judgment mechanism when calibration is triggered is described, which is implemented by a flag code detection module and a calibration sequence monitoring module.
The calibration timing is illustrated with 6 bits as an example:
the method comprises the following steps: when the conversion phase comes, the asynchronous clock generates 6 comparison cycles, and 6-bit digital codes are output by the ADC after 6 times of comparison;
step two: when the ADC finishes digital code output every time, inputting a 6-bit digital code into a mark code detection module, detecting whether the 6-bit digital code is a mark code, if the logic levels behind the ith bit in the digital code sequence are all consistent, recording the digital code sequence as a mark code, and the ith bit in the mark code is a calibration bit; i is 2,3,4, …, n is the number of bits of SAR-ADC; the concrete form is as follows;
| mark code | Calibration object |
| 011111 | MSB |
| 001111 | MSB-1 |
| 010111 | MSB-2 |
| 011011 | MSB-3 |
| 011101 | MSB-4 |
Step three: as shown in fig. 14, if the 6-bit digital code is a FLAG code, the FLAG code detection module monitors that the FLAG is set to 1, activates the calibration sequence monitoring module, and checks whether the capacitor with lower weight than the corresponding capacitor of the FLAG code has been calibrated. If the low level has finished calibrating, the calibration sequence monitoring module outputs CHECK to be set to be 1, and a calibration mechanism of the capacitor at the low level is activated; if the low position does not finish the calibration, the calibration sequence monitoring module outputs CHECK to be set to be 0, and the calibration is skipped;
step four: as shown in fig. 15, after calibration is enabled, the configurable asynchronous clock generates two additional cycles, so that the comparator will compare twice more, and generate a two-bit digital code, referred to as a "calibration code". Taking the MSB calibration as an example, when the flag code is 011111, the calibration is triggered, and the bottom plate connections in the main capacitor array are as shown in fig. 18. In two additional comparison cycles, the bottom plate connections in the main capacitor array are as shown in FIGS. 19 and 20; when a first extra comparison period comes, logic levels of two sub-capacitors corresponding to the MSB-1 bit are inverted, and a logic level connected with one of the two sub-capacitors corresponding to the MSB bit is inverted to perform first comparison to generate a first bit of calibration code; a second additional comparison cycle is initiated to flip the logic level of the other sub-capacitor in the MSB bit for a second comparison to generate a second bit "calibration code".
Step five: as shown in fig. 16 and 17, the switching manner of the compensation capacitor array is determined according to the result of the "calibration code", the compensation capacitor array of the i-th bit capacitor has a plurality of compensation capacitors, and the number of the compensation capacitors in the compensation capacitor array is determined according to the value of the main capacitor, and the larger the capacitance value is, the larger the number of the compensation capacitors is. The unit capacitance of the compensation capacitor array is smaller than that of the main capacitor array. When calibration is performed each time, one compensation capacitor is switched according to the sequence from high bit to low bit in the compensation capacitor array of the ith bit capacitor, only one bit in the compensation capacitor array is switched each time, which means that the same mark code needs to appear for many times to calibrate one bit in the main capacitor array, and finally all the compensation capacitors of the ith bit capacitor participate in calibration, and then the logic for switching the compensation capacitors is as follows: if the obtained two-digit digital codes are different, the compensation capacitor array is not switched, if the obtained two-digit digital codes are both low levels, the VIN side compensation capacitor is switched, and if the obtained two-digit digital codes are both high levels, the VIP side compensation capacitor is switched; the concrete steps are as follows;
| first bit calibration code | Second bit calibration code | Compensation |
| 0 | 0 | VIN |
| 0 | 1 | Is not changed |
| 1 | 0 | Is not changed |
| 1 | 1 | VIP side compensation capacitor |
Step six: and repeating the first step to the sixth step until the calibration of the main capacitor array capacitor is finished.
It should be noted that the calibration mark code can be selected according to its own requirements. For example, the following steps are carried out:
(1) the ADC is required to complete calibration quickly, a plurality of digital codes corresponding to a single-bit capacitor can be used for calibration, and the voltage range corresponding to the digital codes is near the common-mode voltage VCM, so that the occurrence probability of the digital codes is high, the probability of calibrating the single-bit capacitor is increased, and the calibration time is shortened.
(2) The power consumption required for ADC calibration is as low as possible, and then a special class of digital codes can be used, such as: 011111. compared with the corresponding calibration code which needs to be switched, the digital code only needs to be switched into individual switches, so that unnecessary power consumption can be saved.
In summary, the present invention provides a method for switching a split capacitor array and a calibration procedure, which is described in detail with reference to specific examples, and the examples are only used to help understand the contents and core ideas of the present invention. Modifications of the embodiments and applications are intended to fall within the scope of the appended claims.
Claims (6)
1. An analog domain calibration method applied to a SAR-ADC is characterized by comprising the following steps:
(1) the method comprises the steps of sampling an analog input signal and converting the analog input signal into a digital code by using a switching time sequence based on a split capacitor array, wherein the split capacitor array comprises n main capacitors, each main capacitor is split into two identical sub capacitors, and each main capacitor is attached with a compensation capacitor array. The specific process of sampling and converting the analog input signal into the digital code is as follows:
(1.1) sampling the analog input signal, and transferring the information stored in the main capacitor array of the analog input signal from the bottom plate to the top plate;
(1.2) comparing the positive-end input signal VIP with the negative-end input signal VIN, and if the comparison result is 1, connecting the highest-order capacitor on the positive-end input signal VIP side with VREFP, and connecting the highest-order capacitor on the negative-end input signal VIN side with VREFN; if the comparison result is 0, the highest bit capacitance of the positive end input signal VIP side is connected with VREFN, and the highest bit capacitance of the negative end input signal VIN side is connected with VREFP;
(1.3) after comparison, if the output digital code is not the lowest bit, repeating the step (1.2); if the digital code is the lowest bit, the digital code is directly output, and finally the output digital code sequence is obtained.
(2) Recording the digital code sequence obtained in the step (1) as a mark code if the logic levels after the ith bit in the digital code sequence are all consistent, wherein the ith bit in the mark code is a calibration bit; i is 2,3,4, …, n is the number of bits of SAR-ADC; carrying out analog domain calibration on calibration bits from a low bit to a high bit; the calibration procedure for the ith bit calibration bit is as follows:
(2.1) configuring an asynchronous clock, and additionally generating two cycles for calibration, namely the total cycle number is SAR-ADC digit n + 2;
(2.2) carrying out comparison processes of the step (1.2) twice in additional two periods generated by the asynchronous clock to obtain additional two-bit digital codes, wherein the two additional comparison results determine how the compensation capacitor array is switched; the method specifically comprises the following steps: if the obtained two-digit digital codes are different, the compensation capacitor array is not switched, if the obtained two-digit digital codes are both low levels, the VIN side compensation capacitor is switched, and if the obtained two-digit digital codes are both high levels, the VIP side compensation capacitor is switched;
and (2.3) the compensation capacitor array of the ith bit capacitor is provided with a plurality of compensation capacitors, and when calibration is performed each time, one compensation capacitor is switched from a high bit to a low bit in the compensation capacitor array of the ith bit capacitor, until all the compensation capacitors are switched, the calibration of the ith bit calibration is finished.
2. The analog domain calibration method applied to the SAR-ADC of claim 1, wherein a bottom plate of a sampling capacitor of the SAR-ADC is connected with two logic levels only without being connected with VCM logic levels, and a top plate is connected with one logic level VCM only; the two logic levels are VREFP and VREFN.
3. The method as claimed in claim 1, wherein before calibration, it is determined whether all the capacitances of the calibration bits before the i-th bit have been calibrated. If not, skipping the calibration of the ith calibration bit; if all the calibration is finished, the calibration of the ith calibration bit is executed.
4. The analog domain calibration method applied to the SAR-ADC of claim 1, wherein the judgment basis of the i-th calibration bit after the capacitance calibration is that: the compensation capacitors in the capacitance-dependent compensation capacitor array of the ith calibration bit participate in the calibration.
5. The method according to claim 1, wherein the number of compensation capacitors in the compensation capacitor array is determined according to the value of the main capacitor, and the larger the capacitance value is, the larger the number of compensation capacitors is.
6. The method as claimed in claim 1, wherein the unit capacitance of the compensation capacitor array is smaller than that of the main capacitor array.
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