CN116260459A - Single-ended SAR ADC circuit with lockable capacitor array and working method thereof - Google Patents
Single-ended SAR ADC circuit with lockable capacitor array and working method thereof Download PDFInfo
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- CN116260459A CN116260459A CN202211598534.XA CN202211598534A CN116260459A CN 116260459 A CN116260459 A CN 116260459A CN 202211598534 A CN202211598534 A CN 202211598534A CN 116260459 A CN116260459 A CN 116260459A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/002—Provisions or arrangements for saving power, e.g. by allowing a sleep mode, using lower supply voltage for downstream stages, using multiple clock domains or by selectively turning on stages when needed
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/124—Sampling or signal conditioning arrangements specially adapted for A/D converters
Abstract
The invention provides a single-ended SAR ADC circuit with a lockable capacitor array and a working method thereof. Before starting the analog-to-digital conversion, it is necessary to determine whether a lock switch in the capacitive array needs to be closed. Therefore, the input signal is compared with a specific voltage, the turn-off condition of the locking switch is judged according to the comparison result, and if the locking switch is turned off, the single-ended SAR ADC performs normal analog-digital conversion; if the lock switch is closed, the capacitance in the capacitive array of the single-ended SAR ADC that is connected to the lock switch will be locked, keeping the lock connected to GND. When the input signal is smaller, the locking switch is closed to lock the high-order capacitor, so that unnecessary switching of the capacitor array can be reduced, and the power consumption generated by the capacitor array and the switch can be greatly saved only at the cost of less hardware cost.
Description
Technical Field
The invention is applicable to the field of analog integrated circuit design, and particularly relates to a single-ended SAR ADC circuit and a working method thereof.
Background
With the rapid development of microelectronics and digital signal processing technologies, analog-to-digital converters (Analog to Digital Converters, ADC) are in wide-ranging application in various fields and have also made significant progress. Summarizing the progress of analog-to-digital converters, it is readily observed that ADCs are currently evolving towards low power consumption, high speed and high resolution.
There are many different structures of ADCs, and there are various advantages and disadvantages associated with different types of ADCs. SAR ADCs are an architecture that was proposed earlier and are basically characterized by serial operation, with the entire process from sampling the input signal to the end of the analog-to-digital conversion of the entire ADC. In view of the serial operation, the SAR ADC must wait until the entire analog-to-digital conversion process is completed before the next sampling of the input signal can be performed. Typically, the sampling rate of SAR ADCs is lower compared to Flash ADCs and Pipelined ADCs; SAR ADCs have lower accuracy than sigma-delta ADCs.
However, with the rapid progress of semiconductor manufacturing processes, SAR ADCs can be said to be the most improved. This is because, in the SAR ADC, only one analog circuit is used as the comparator, the reduction of the semiconductor process causes restrictions on the analog circuit, and the design of the SAR ADC is not greatly affected. On one hand, the semiconductor manufacturing process is continuously reduced, so that the operating speed of a digital circuit is doubled, the speed of a switch capacitor circuit of the SAR ADC is obviously improved, and the SAR ADC is separated from a mark of a low-speed ADC; on the other hand, the reduction of the power supply voltage makes the advantage of low power consumption of the SAR ADC more prominent. Moreover, by using digital correction techniques, the quantization accuracy of the SAR ADC can also be greatly improved. In general, this is the main method of reducing the figure of merit (FoM) of SAR ADCs by optimizing the core modules of sampling switches, comparators, SAR logic, DAC arrays, etc. in SAR ADCs.
As the development process of the ADC is just like the development process of the ADC, with the increasing demands of application, the requirements on the precision and the speed of the SAR ADC are more and more severe, and the design of the SAR ADC circuit faces many challenges, so that the SAR ADC circuit needs to be continuously developed to low power consumption, high speed and high resolution, and a trade-off is often required among the three.
Accordingly, the present invention proposes a single-ended SAR ADC circuit with lockable capacitor array.
Disclosure of Invention
In view of the development direction of the above analysis SAR ADC, the present invention aims to provide a single-ended SAR ADC circuit with lockable capacitor array, so as to adapt to the development requirement.
The technical scheme of the invention is as follows:
a capacitive array lockable single ended SAR ADC circuit comprising:
sampling switch circuit, sampling switch circuit includes sampling switch S 1 And sampling capacitor C S Sampling switch S 1 The first terminal of (a) is connected with the input signal VIN, and the second terminal is connected with the sampling capacitor C S Sampling capacitor C S Is connected to GND.
The DAC capacitor array with the locking switch comprises capacitors, switches, selectable switches and locking switches, wherein the number of the capacitors is N+1, and the number of the capacitors is C 0 ，C 1 ，C 2 ···C N The capacity of (2) is arranged according to the binary weight bit, such as C,2 0 C，2 1 C，2 2 C···2 N-1 C, where N<12; the N+1 capacitors C 0 ，C 1 ，C 2 ···C N Is connected together, capacitor C 0 A second terminal connected to GND, a capacitor C 0 ，C 1 ，C 2 ···C N Respectively with the second terminals of the selectable switches SW 1 ，SW 2 ···SW N Is connected to the first terminal of (a); the optional switch SW 1 ，SW 2 ···SW N A second terminal connected to VREF and a third terminal connected to GND, the optional switch SW 1 ，SW 2 ···SW N Can be selectively connected to GND or VREF; the locking switchThe first terminal of the switch is also connected with the high-order capacitor C N Is connected to the second terminal of (2), the second terminal is connected to GND; switch S 4 A second terminal connected to GND, a first terminal and N+1 capacitors C 0 ，C 1 ，C 2 ···C N Is connected to form an output VDAC of the DAC capacitive array.
A comparator with positive end input VP and C in the sampling switch circuit S Is connected to the first terminal of the switch, the negative terminal input VN is connected to the switch S 2 Is connected to the second terminal of (c); switch S 2 The first terminal is connected to a voltage VTH; switch S 3 The first terminal of which is also connected to the negative input VN of the comparator and the second terminal is connected to the output VDAC of the DAC capacitive array.
The input end of the SAR control logic module is connected with the output end of the comparator, and the SAR control logic module can control the turn-off condition of a locking switch and control a selectable switch SW in the DAC capacitor array with the locking switch 1 ，SW 2 ···SW N Connection condition of connecting GND and VREF and digital code D 1 ，D 2 ，··D N 。
As described above, the capacitor array lockable single-ended SAR ADC provided by the invention comprises a sample hold circuit, a comparator, an SAR control logic module and a DAC capacitor array with a locking switch. Before starting the analog-to-digital conversion, it is necessary to determine whether a lock switch in the capacitive array needs to be closed. Therefore, the input signal is compared with a specific voltage, the turn-off condition of the locking switch is judged according to the comparison result, and if the locking switch is turned off, the single-ended SAR ADC performs normal analog-digital conversion; if the lock switch is closed, the capacitance in the capacitive array of the single-ended SAR ADC that is connected to the lock switch will be locked, keeping the lock connected to GND.
The beneficial effects of the invention are as follows: when the input signal is smaller, the locking switch is closed to lock the high-order capacitor, so that unnecessary switching of the capacitor array can be reduced, and the power consumption generated by the capacitor array and the switch can be greatly saved only at the cost of less hardware cost.
Drawings
FIG. 1 is a block diagram of a most basic single ended SAR ADC circuit;
FIG. 2 is a block diagram of a capacitor array lockable single-ended SAR ADC circuit according to the present invention;
FIG. 3 is a block diagram of a 4-bit capacitor array lockable single-ended SAR ADC circuit according to the present disclosure;
FIG. 4 is a flow chart of the operation of the capacitive array lockable single-ended SAR ADC according to the present invention;
FIG. 5 shows a binary search algorithm waveform diagram of a 4-bit capacitor array lockable single-ended SAR ADC according to the present invention when the analog input voltage is relatively small and the locking switch is opened and closed, (a) is an algorithm waveform diagram when the locking switch is opened, and (b) is an algorithm waveform diagram when the locking switch is closed;
in the figure: 1-a sampling switch circuit; a 2-comparator; a 3-SAR control logic module; 4-DAC capacitor array with lock-in switch.
Detailed Description
The invention will be described in detail below with reference to the attached drawings and specific examples:
fig. 1 is a schematic diagram of a most basic single-ended SAR ADC circuit, including a sample-and-hold circuit, a comparator, a DAC binary capacitor array, SAR control logic, and an N-bit register. This construction principle is simple and will be explained briefly below to understand the capacitive array lockable single-ended SAR ADC proposed by the present invention.
The analog input voltage is held by a sample-and-hold circuit, the MSB of the DAC binary capacitor array is firstly set to be '1', and the other positions are '0', namely the output VDAC of the DAC is=VREF/2; a first comparison is then made to compare VIN to VDAC to determine if VIN is greater or less than VDAC. If VIN is greater than VDAC, the comparator outputs a logic level of "1", with the most significant MSB remaining at "1"; if VIN is less than VDAC, the comparator outputs a logic level "0", with the most significant MSB changing to "0". The SAR control logic then shifts the next higher order bits and first sets the next higher order bit "1", makes a second comparison, and so on, until the least significant LSB is determined, and analog-to-digital conversion is completed. Such an algorithm is called a binary search algorithm.
Fig. 2 shows a capacitor array lockable single-ended SAR ADC according to the present invention. Improvements are made on the basis of the most basic single-ended SAR ADC structure. The working principle of the lockable single-ended SAR ADC with the capacitor array is as follows: the positive end input VP of the comparator is connected with the sampling switch circuit, the negative end input of the comparator is respectively connected with the VTH and the DAC capacitor array through two switches, and the DAC capacitor array is arranged on the highest capacitor C N A lock switch connected with GND is added, and when the lock switch is closed, a capacitor C N Will be locked to GND. Before starting the analog-to-digital conversion, it is necessary to determine whether a lock switch in the capacitive array needs to be closed. The analog input voltage VIN is compared with the VTH, whether the locking switch is closed or open is determined according to the comparison result, and then a binary search algorithm is performed to complete analog-to-digital conversion. When the input signal is smaller, the locking switch is closed to lock the high-order capacitor, so that unnecessary switching of the capacitor array can be reduced, and the power consumption generated by the capacitor array and the switch can be greatly saved only at the cost of less hardware cost.
Embodiments of the present invention are described below by way of specific examples.
FIG. 3 is a block diagram of a 4-bit capacitor array lockable single-ended SAR ADC circuit according to the present disclosure; fig. 4 is a flowchart of the operation of the capacitor array lockable single-ended SAR ADC according to the present invention. Wherein, the capacitor C in the 4-bit DAC capacitor array with locking switch in FIG. 3 0 ，C 1 ，C 2 ，C 3 ，C 4 The capacitance value size ratio of the distributed capacitor according to the binary weight is as follows: c (C) 0 ：C 1 ：C 2 ：C 3 ：C 4 ＝C：2 0 C：2 1 C：2 2 C：2 3 C＝C：C：2C：4C：8C。
An embodiment of the present invention is described with reference to fig. 3 and 4.
First, the ADC starts sampling the analog input signal, switch S 1 Closed, analog input signal VIN is sample-and-holdSampling-to-sampling capacitor C S On, then switch S 1 Off, the analog input signal VIN is held onto the positive input VP of the comparator; simultaneous switch S 2 Closing, switch S 3 The negative input VN of the comparator is connected to VTH, due to the one locking switch and the capacitor C 4 In connection, VTH is equal to or greater than the capacitance C 4 The weight size occupied is VREF/2, i.e., vth=vref/2. At this time, vp=vin, vn=vth.
And then determining whether the locking switch in the capacitor array needs to be closed or not, comparing the VP and the VN by a comparator, and determining whether the locking switch in the DAC capacitor array needs to be closed or not according to the comparison result. If VP is greater than VN, the lock switch is opened. If VP is less than VN, then the lock switch is closed, capacitor C 4 Will be locked and remain connected to GND.
After determining the closing of the locking switch in the capacitor array, switch S 2 Open, switch S 3 The negative terminal input of the comparator is connected to the output VDAC of the DAC capacitive array. Simultaneous switch S 4 Closing, optional switch SW 1 Selectable switch SW 2 Selectable switch SW 3 Selectable switch SW 4 The connection GND is selected and the entire DAC capacitor array is reset.
Analog-to-digital conversion, i.e., binary search algorithms as described above, is performed next. At this time, since the states of the lock switches are different, the following two cases occur.
Case one: the locking switch is in an off state, the capacitor C 4 Is not locked, and is a normal binary search algorithm. First, switch S 4 The off, reset state ends. The SAR control logic module controls the MSB capacitor C at the highest position in the DAC capacitor array 4 Connected optional switch SW 4 Connected to VREF, the output of the DAC capacitive array vdac=vref/2, i.e., the negative input of the comparator vn=vdac=vref/2, and the positive input of the comparator vp=vin. The first comparison of the analog-to-digital conversion is started, the comparator works, comparing the magnitudes of VP and VN. SAR control if VP is greater than VNThe logic control module outputs the highest bit D 1 =1, the most significant MSB capacitance C 4 Connected optional switch SW 4 Still connected to VREF, the optional switch SW to which the next highest capacitance C3 is connected 3 Connected to VREF, the value of VDAC will become VREF 3/4; if VP is less than VN, SAR control logic module controls output D 1 =0, the most significant MSB capacitance C 4 Connected optional switch SW 4 Switch-over connected to GND, next highest capacitance C 3 Connected optional switch SW 3 Connected to VREF, the value of VDAC will become VREF 1/4. Then the second comparison of analog-to-digital conversion is carried out, the comparator works, the magnitudes of VP and VN are compared again, and the next highest order D is determined 2 And so on until the least significant bit D 4 And determining that the whole analog-to-digital conversion process is finished.
And a second case: the locking switch is in a closed state, and the capacitor C 4 Is locked, this time slightly different from the binary search algorithm described above. First, switch S 4 The off, reset state ends. Capacitor C due to the closed state of the locking switch 4 Locked, SAR control logic module outputs the highest bit D 1 It should be noted that this result is locked, skipping the first comparison of the binary algorithm described above, the SAR control logic does not change the highest MSB capacitance C 4 Connected optional switch SW 4 Is connected to the connection state of the device. Then, binary search algorithm is carried out, and SAR control logic module directly controls the next highest capacitance C 3 Connected optional switch SW 3 Connected to VREF, the value of VDAC will become VREF 1/4. Then the first comparison of analog-to-digital conversion is carried out, the comparator works, the magnitudes of VP and VN are compared, and the next highest order D is determined 2 And an optional switch SW 3 If the VREF is continuously connected, if the VP is larger than the VN, the SAR control logic module controls the output of the highest bit D 2 =1, next highest capacitance C 3 Connected optional switch SW 3 Still connected to VREF, capacitor C 2 Connected optional switch SW 2 Connected to VREF, the value of VDAC will become VREF 3/8; if VP is less than VN, SAR control logic module controls output D 2 =0, next highest capacitance C 3 Connected optional switch SW 3 Switch-over connected to GND, capacitor C 2 Connected optional switch SW 2 Connected to VREF, the value of VDAC will become VREF 1/8. Then the second comparison of analog-to-digital conversion is carried out, the comparator works, the VP and VN are compared again, and D is determined 3 And so on until the least significant bit D 4 And determining that the whole analog-to-digital conversion process is finished.
FIG. 5 is a diagram of a binary search algorithm in the case of the 4-bit capacitor array lockable single-ended SAR ADC according to the present invention, when the analog input voltage is relatively small, the locking switch is opened and closed, FIG. 5 (a) is a diagram of an algorithm when the locking switch is opened, and FIG. 5 (b) is a diagram of an algorithm when the locking switch is closed; it can be seen that when VIN is less than vth=vref/2, it can be seen that when the significantly locked switch is closed, an unnecessary switching of the capacitive array is reduced once when analog-to-digital conversion is performed, thereby reducing power consumption.
The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Similarly, a lock switch may be added to the next highest capacitor, or even to all capacitors.
According to the binary search algorithm described above, when the single-ended SAR ADC performs analog-to-digital conversion, the N-th bit is determined, all the corresponding capacitors are required to be connected with VREF first, then whether the corresponding capacitor of the bit is continuously connected with VREF is judged according to the comparison result, if the comparison result is '1', the corresponding capacitor of the bit is continuously connected with VREF, and no 'unnecessary' charge and discharge consumption is generated; if the comparison result is "0", the corresponding capacitor of this bit is switched to GND, resulting in "unnecessary" charge and discharge consumption. If the highest capacitance is locked by the locking switch closing when the analog input voltage VIN is smaller, this time the power consuming maximum and "unnecessary" switching can be reduced during the binary search algorithm, and the power consumption during the analog to digital conversion will be greatly reduced.
In summary, the present invention provides a single-ended SAR ADC circuit with lockable capacitor array, which includes a sample-hold circuit, a comparator, a SAR control logic module, and a DAC capacitor array with a locking switch. Before starting the analog-to-digital conversion, it is necessary to determine whether a lock switch in the capacitive array needs to be closed. Therefore, the input signal is compared with a specific voltage, the turn-off condition of the locking switch is judged according to the comparison result, and if the locking switch is turned off, the single-ended SAR ADC performs normal analog-digital conversion; if the lock switch is closed, the capacitance in the capacitive array of the single-ended SAR ADC that is connected to the lock switch will be locked, keeping the lock connected to GND. When the input signal is smaller, the locking switch is closed to lock the high-order capacitor, so that unnecessary switching of the capacitor array can be reduced, and the power consumption generated by the capacitor array and the switch can be greatly saved only at the cost of less hardware cost.
Claims (3)
1. A capacitor array lockable single ended SAR ADC circuit, comprising:
sampling switch circuit, sampling switch circuit includes sampling switch S 1 And sampling capacitor C S Sampling switch S 1 The first terminal of (a) is connected with the input signal VIN, and the second terminal is connected with the sampling capacitor C S Sampling capacitor C S Is connected to GND;
the DAC capacitor array with the locking switch comprises a capacitor, a switch, an optional switch and a locking switch; the number of the capacitors is N+1, and the capacitor C 0 ，C 1 ，C 2 ···C N The capacity value of (2) is correspondingly arranged according to binary weight bits, wherein N is<12; the N+1 capacitors C 0 ，C 1 ，C 2 ···C N Is connected together, capacitor C 0 A second terminal connected to GND, a capacitor C 0 ，C 1 ，C 2 ···C N Respectively with the second terminals of the selectable switches SW 1 ，SW 2 ···SW N Is connected to the first terminal of (a); the optional switch SW 1 ，SW 2 ···SW N A second terminal connected to VREF and a third terminal connected to GND, the optional switch SW 1 ，SW 2 ···SW N Can be selectively connected to GND or VREF; the first terminal of the locking switch is also connected with the high-order capacitor C N Is connected to the second terminal of (2), the second terminal is connected to GND; switch S 4 A second terminal connected to GND, a first terminal and N+1 capacitors C 0 ，C 1 ，C 2 ···C N Is connected to form an output VDAC of the DAC capacitive array;
a comparator with positive end input VP and C in the sampling switch circuit S Is connected to the first terminal of the switch, the negative terminal input VN is connected to the switch S 2 Is connected to the second terminal of (c); switch S 2 The first terminal is connected to a voltage VTH; switch S 3 A first terminal connected to the comparator negative terminal input VN and a second terminal connected to the output VDAC of the DAC capacitive array;
the input end of the SAR control logic module is connected with the output end of the comparator, and the SAR control logic module can control the turn-off condition of a locking switch and control a selectable switch SW in the DAC capacitor array with the locking switch 1 ，SW 2 ···SW N Connection condition of connecting GND and VREF and digital code D 1 ，D 2 ，··D N 。
2. The capacitor array lockable single-ended SAR ADC circuit of claim 1, wherein in the DAC capacitor array with locking switch: not only in the highest capacitance C N Adding a locking switch, and adding the locking switch to the next-highest capacitor or adding all capacitors to the locking switch; first terminal of locking switch and corresponding capacitor C i Is connected to GND, i=0 to N.
3. The method of claim 1 or 2, wherein the positive input VP of the comparator is connected with the sampling switch circuit, the negative input of the comparator is respectively connected with the VTH and the DAC capacitor array through two switches, and the DAC capacitor array is electrically connected at the highest positionCapacitor C N Capacitor C when the locking switch is closed N Will be locked to connect to GND; before starting the analog-to-digital conversion, it is necessary to determine whether a lock switch in the capacitor array needs to be closed; comparing the analog input voltage VIN with VTH, determining whether the locking switch is closed or open according to the comparison result, and then performing a binary search algorithm to finish analog-to-digital conversion; when the input signal is smaller, the high-order capacitor is locked by closing the locking switch, so that the switching of the capacitor array is reduced.
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| CN202211598534.XA CN116260459A (en) | 2022-12-12 | 2022-12-12 | Single-ended SAR ADC circuit with lockable capacitor array and working method thereof |
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