CN117336947A

CN117336947A - Electronic device, circuit board thereof and manufacturing method of electronic device

Info

Publication number: CN117336947A
Application number: CN202210717880.9A
Authority: CN
Inventors: 廖致傑; 孙育民; 程志丰
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd; Global Unichip Corp
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd; Global Unichip Corp
Priority date: 2022-06-23
Filing date: 2022-06-23
Publication date: 2024-01-02

Abstract

An electronic device comprises a semiconductor component, a circuit board, a plurality of first conductive pads and second conductive pads. The circuit board is provided with a flip-chip area, and the flip-chip area is rectangular. The first conductive pads are distributed in the central area or the corner area of the flip-chip area, and the second conductive pads are distributed in the rest positions of the flip-chip area. The first conductive pads are respectively welded with a part of welding spots of the semiconductor component through the first solder ball parts, and the second conductive pads are respectively welded with another part of welding spots through the second solder ball parts. The area of each second conductive pad is smaller than that of the first conductive pad, and the width of each second solder ball part is larger than that of the first solder ball part. Through the structure, the probability of solder ball bridging of the circuit board can be reduced, the connection performance between the semiconductor component and the circuit board is improved, and the reliability of the semiconductor packaging element is improved.

Description

Electronic device, circuit board thereof and manufacturing method of electronic device

Technical Field

The present invention relates to an electronic device, and more particularly, to an electronic device with circuit boards having conductive pads with different sizes.

Background

Generally, a semiconductor component (semiconductor assembly) is mounted on a circuit board by a surface mount technology (Surface Mount Technology, SMT) of a Ball Grid Array (BGA).

However, in practice, heat concentration occurs at the corners of the semiconductor device, and the heat load caused by the heat concentration causes warpage of the substrate of the semiconductor device, so that bridging between adjacent solder balls at the corner regions of the semiconductor device is caused. Therefore, the connection performance between the semiconductor assembly and the circuit board is lowered, thereby affecting the reliability of the semiconductor package element.

It is evident from this that the above-described technique still has inconveniences and drawbacks, and needs to be further improved. Therefore, how to effectively solve the above-mentioned inconveniences and defects is one of the important research and development problems at present, and is also an urgent need for improvement in the related art.

Disclosure of Invention

An objective of the present invention is to provide an electronic device, a circuit board thereof and a manufacturing method of the electronic device, which are used for solving the above-mentioned difficulties in the prior art.

An embodiment of the invention provides an electronic device. The electronic device comprises a semiconductor component, a circuit board, a plurality of first conductive pads and second conductive pads. The semiconductor component comprises a substrate, a die and a packaging material, wherein the substrate comprises a first surface and a second surface which are opposite to each other. The first surface of the substrate is provided with a plurality of welding spots which are arranged at intervals. The crystal grain is fixed on the second surface of the base material, and the packaging material wraps the crystal grain on the base material. The circuit board has a flip-chip region. The flip chip area is rectangular and has a central area and a plurality of corner areas. The first conductive pads are arranged in the central area or all corner areas of the flip-chip area at intervals. The first conductive pads are respectively connected with a part of the welding spots through first welding ball parts. The second conductive pads are arranged in the rest positions of the flip chip area at intervals, and are respectively connected with the other parts of the welding spots through second solder ball parts. The area of each second conductive pad is smaller than that of one of the conductive pads, and the maximum width of each second solder ball part is larger than that of one of the first solder ball parts.

According to one or more embodiments of the present invention, in the electronic device, the first conductive pads are elongated, each of the first conductive pads has a long axis direction, the flip chip area has a horizontal line, and the long axis direction and the horizontal line have an included angle of 45 ° to 60 °.

According to one or more embodiments of the present invention, in the electronic device, the shapes of the first conductive pads are respectively elliptical, and the long axis direction of each first conductive pad passes through two adjacent sides of the flip chip area.

According to one or more embodiments of the present invention, in the electronic device, the shapes of the first conductive pads and the second conductive pads are respectively circular with different areas.

According to one or more embodiments of the present invention, in the above-mentioned electronic device, when the flip-chip area is divided into a plurality of square cells with the same size by performing an image division technique, the square cells are directly arranged according to an N by N matrix. N is an integer greater than 2, the central region is at least one square corresponding to or adjacent to the rectangular centroid of the flip-chip region, and all corner regions are four squares located at a plurality of rectangular corners of the flip-chip region.

In one or more embodiments of the present invention, in the electronic device, the substrate is curved like a smiling face, and the central region is connected with a maximum virtual square. Four corners of the maximum virtual square are respectively contacted with four side lines of the square, and the first guide pads are only distributed in the maximum virtual square.

According to one or more embodiments of the present invention, in the electronic device, the substrate is curved in a crying face shape, and the four squares are divided into two virtual regular triangles by a diagonal line respectively. The first conductive pads are only distributed in the two virtual regular triangles, and are connected with one corresponding rectangular angle.

An embodiment of the invention provides a circuit board. The circuit board comprises a board body, a first conductive pad and a second conductive pad. One side of the board body is provided with a flip-chip area. The flip chip area is rectangular and has a central area and a plurality of corner areas. The first conductive pads are arranged in the central area or all corner areas at intervals. The second conductive pads are arranged in the rest positions of the flip chip area at intervals. The area of each second conductive pad is smaller than that of one first conductive pad.

According to one or more embodiments of the present invention, in the above-mentioned circuit board, the first conductive pads are elongated, each of the first conductive pads has a long axis direction, the flip chip area has a horizontal line, and the long axis direction and the horizontal line have an included angle of 45 ° to 60 °.

According to one or more embodiments of the present invention, in the above-mentioned circuit board, the shapes of the first conductive pads are respectively elliptical, and a long axis direction of each first conductive pad passes through two adjacent sides of the flip chip area.

According to one or more embodiments of the present invention, in the above-mentioned circuit board, the shapes of the first conductive pads and the second conductive pads are respectively circular with different areas.

According to one or more embodiments of the present invention, in the above-mentioned circuit board, when the flip-chip area is divided into a plurality of square cells with the same size by performing an image division technique, the square cells are directly arranged according to an N by N matrix. N is an integer greater than 2, the central region is at least one square corresponding to or adjacent to the rectangular centroid of the flip-chip region, and all corner regions are four squares located at a plurality of rectangular corners of the flip-chip region.

According to one or more embodiments of the present invention, in the above circuit board, a maximum virtual square is connected in the central area, four corners of the maximum virtual square contact all edges of the square respectively, and the first conductive pads are only distributed in the maximum virtual square.

According to one or more embodiments of the present invention, in the above-mentioned circuit board, the four squares are respectively divided into two virtual regular triangles by a diagonal line, and the first conductive pads are distributed only in the two virtual regular triangles, and have one rectangular angle corresponding to the connection.

An embodiment of the invention provides a method for manufacturing an electronic device. The manufacturing method comprises the following steps. A semiconductor component is provided, the semiconductor component comprises a substrate and a crystal grain, the crystal grain is fixed on one surface of the substrate, and a plurality of welding spots are arranged on the other surface of the crystal grain. Designing a circuit layout pattern on a circuit board, and manufacturing the circuit board according to the circuit layout pattern, wherein the circuit layout pattern is provided with a flip chip area, a plurality of first conductive connection pads and second conductive connection pads, the first conductive connection pads are distributed in a central area or all corner areas of the flip chip area, the second conductive connection pads are distributed on other positions of the flip chip area, and the area of each second conductive connection pad is smaller than that of one of the first conductive connection pads. The first conductive pads are respectively welded with one part of welding spots through the first solder ball parts, and the second conductive pads are respectively welded with the other part of welding spots through the second solder ball parts, and the maximum width of each second solder ball part is larger than that of one first solder ball part.

According to one or more embodiments of the present invention, in the method for manufacturing an electronic device, designing the circuit layout pattern on the circuit board further includes the following steps. Performing warp measurement on the semiconductor component; judging whether the substrate of the semiconductor component is in a smiling face type bending shape or not; when the substrate is judged to be in a smiling face bending shape, the shapes of the first guide connection pads of the circuit layout pattern are designed to be elliptical and distributed in the central area of the flip chip area, and the second guide connection pads are distributed in other positions except the central area of the flip chip area; the long axis direction of each first guide connection pad passes through two adjacent edges of the flip chip area; performing a soldering virtual experiment, and judging whether a soldering condition is generated between the first solder ball parts in the central area of the circuit layout pattern; and continuing to manufacture the circuit board when the welding condition is not generated between the first solder ball parts.

According to one or more embodiments of the present invention, in the method for manufacturing an electronic device, when it is determined that a soldering condition occurs between the first solder ball portions, the method further includes the following steps. And gradually adjusting the quantity proportion of the first conductive pads and the second conductive pads according to a plurality of directions from the rectangular centroid of the flip chip region to all corner regions of the flip chip region, and continuing the step of welding virtual experiments.

According to one or more embodiments of the present invention, in the method for manufacturing an electronic device, when it is determined that the substrate of the semiconductor device is curved in a crying face shape, the method further includes the following steps. The shapes of the first guide connection pads of the circuit layout patterns are designed to be elliptical and distributed in all corner areas of the flip chip area, and the second guide connection pads are distributed in the rest positions of the flip chip area except all corner areas, wherein a long axis direction of each first guide connection pad passes through two adjacent sides of the flip chip area; performing a soldering virtual experiment, and judging whether the soldering condition is generated between the first solder ball parts in all corner areas of the flip chip area of the circuit layout pattern; and continuing to manufacture the circuit board when the welding condition is not generated between the first solder ball parts.

According to one or more embodiments of the present invention, in the method for manufacturing an electronic device, when it is determined that a soldering condition occurs between the first solder ball portions, the method further includes the following steps. And gradually adjusting the quantity proportion of the first conductive pads and the second conductive pads from all the corner areas of the flip chip area towards the multi-directions of the rectangular centroid of the flip chip area, and continuing the step of the welding virtual experiment.

Thus, through the framework, the probability of solder ball bridging on the circuit board can be reduced, and the connection performance between the semiconductor component and the circuit board can be improved, so that the reliability of the semiconductor packaging element can be improved.

The above description is only intended to illustrate the problems to be solved, the technical means to solve the problems, the effects to be produced, etc. the specific details of the present invention will be described in the following description and the related drawings.

Drawings

The foregoing and other objects, features, advantages and embodiments of the invention will be apparent from the following description taken in conjunction with the accompanying drawings in which:

FIG. 1 is a schematic diagram of an electronic device according to an embodiment of the invention;

fig. 2 is a top view of the circuit board of the present embodiment;

fig. 3 is a partial enlarged view of the region M of fig. 2;

FIG. 4 is a top view of a circuit board according to an embodiment of the invention;

FIG. 5 is a flow chart of a method of manufacturing an electronic device according to an embodiment of the invention;

FIG. 6 is a detailed flow chart of step 502 of FIG. 5;

FIG. 7A is a schematic diagram of step 606 in conjunction with FIG. 6; and

fig. 7B is a schematic diagram of step 610 in conjunction with fig. 6.

[ symbolic description ]

10 electronic device

100 semiconductor assembly

110 substrate

111 first side

112 second side

113 first welding point

114 second welding point

115 solder pad

120 crystal grain

121, guide connection convex column

130 packaging material

200. 201 Circuit Board

210 front face

220. 222, 223 flip chip area

221 rectangular centroid

230 central zone

231 side line

240 corner area

241 rectangular corners

250. 251 first conductive pad

252 major axis direction

260 second conductive pad

310 first solder ball portion

320 second solder ball portion

400 square grid

410 diagonal line

420 maximum virtual square

421 corner

430 diagonal line

431 first virtual regular triangle

432 second virtual regular triangle

501-504, 601-611 steps

a, semi-long axis

b semi-minor axis

D1 first direction

D2, second direction

E adjacent edges

G1, G2 spacing

H horizontal line

M region

R1, R2 area

Maximum width W1, W2

Theta is the included angle

Detailed Description

Various embodiments of the invention are disclosed in the accompanying drawings, and for purposes of explanation, numerous practical details are set forth in the following description. However, it should be understood that these practical details are not to be taken as limiting the invention. That is, in embodiments of the present invention, these practical details are not necessary. Furthermore, for the sake of simplicity of the drawing, some conventional structures and elements are shown in the accompanying drawings in a simplified schematic manner.

Fig. 1 is a schematic diagram of an electronic device 10 according to an embodiment of the invention. Fig. 2 is a top view of the circuit board 200 of the present embodiment. Fig. 3 is a partial enlarged view of the region M of fig. 2. As shown in fig. 1 and 2, in the present embodiment, the electronic device 10 includes a semiconductor assembly 100, a circuit board 200, a plurality of first conductive pads 250, a plurality of second conductive pads 260, a plurality of first solder ball portions 310 (e.g., solder balls), and a plurality of second solder ball portions 320 (e.g., solder balls). The semiconductor device 100 has a plurality of pads (hereinafter, a plurality of first pads 113 and a plurality of second pads 114). A portion of the front side 210 of the circuit board 200 has a flip-chip area 220. The flip-chip region 220 has a rectangular shape with a central region 230 and four corner regions 240, in other words, the corner regions 240 are spaced around the central region 230, and the central region 230 is located at the intersection of the diagonal lines of the corner regions 240. The first conductive pads 250 are respectively arranged in all corner regions 240 of the flip-chip area 220 at intervals, and the second conductive pads 260 are respectively arranged in the rest positions (including the central region 230) of the flip-chip area 220 except for all corner regions 240 at intervals. The shape of each first conductive pad 250 is substantially different from the shape of the second conductive pad 260, and the area R1 of each first conductive pad 250 is substantially larger than the area R2 of the second conductive pad 260. The first pads 250 are connected to the first pads 113 through the first solder ball portions 310, and the second pads 260 are connected to the second pads 114 through the second solder ball portions 320.

More specifically, the semiconductor device 100 includes a substrate 110, a die 120, and a package 130. The substrate 110 includes a first surface 111 and a second surface 112 opposite to each other. The first solder joints 113 and the second solder joints 114 are respectively spaced apart from the first surface 111 of the substrate 110, and the second surface 112 of the substrate 110 has a plurality of pads 115 spaced apart from each other. The die 120 has a plurality of conductive bumps 121. The conductive bumps 121 are spaced apart from one surface of the die 120. The conductive bumps 121 of the die 120 are soldered to the pads 115 of the substrate 110 by solder (not shown), so that the die 120 is fixed to the second surface 112 of the substrate 110. The package material 130 encapsulates the die 120 on the substrate 110.

Thus, whether or not the substrate 110 of the semiconductor device 100 is curved due to the heat load, since the area R1 of one of the first conductive pads 250 located in the corner region 240 of the flip chip area 220 is larger than the area R2 of one of the second conductive pads 260, the maximum width W1 (e.g., the waist maximum perimeter) of the first solder ball portion 310 is smaller than the maximum width W2 (e.g., the waist maximum perimeter) of the second solder ball portion 320 on the basis of the same solder ball size (i.e., the volume of the first solder ball portion 310 is substantially equal to the volume of the second solder ball portion 320). Therefore, the spacing G1 between any two adjacent first solder ball portions 310 is greater than the spacing G2 between any two adjacent second solder ball portions 320, so as to reduce the bridging probability between the first solder ball portions 310 located in the corner region 240.

Fig. 3 is a partial enlarged view of the region M of fig. 2. Further, as shown in fig. 2 and 3, the first pads 250 are elongated, for example, elliptical in shape, and the second pads 260 are circular in shape. The long axis direction 252 of each first conductive pad 250 passes through two adjacent sides E (i.e., two adjacent sides of the rectangle) of the flip chip region 220, and an included angle θ is formed between the long axis direction 252 of each first conductive pad 250 and the horizontal line H of the flip chip region 220, for example, the included angle θ is between 45 ° and 60 °, so as to minimize the problem of the mutual welding of the first solder ball portions 310. However, the present invention is not limited to the shape of the first conductive pad 250 and the second conductive pad 260.

For example, the semi-major axis a of the first conductive pad 250 is 0.23 mm and the semi-minor axis b is 0.2 mm, so that the area of the first conductive pad 250 is 0.145 (0.2×0.23×pi) square mm (mm) ² ). The radius of the second conductive pad 260 is 0.2 mm, and therefore, the area of the second conductive pad 260 is 0.126 (0.2++2) square millimeters (mm) ² ) And is 15% smaller than the area of the first conductive pad 250.

Fig. 4 is a top view of a circuit board 201 according to an embodiment of the present invention. As shown in fig. 4, the circuit board 201 of the present embodiment is substantially the same as the circuit board 200 of fig. 2, except that the shape of the first conductive pad 251 is the same as the shape of the second conductive pad 260, and the area R1 of the first conductive pad 251 is still larger than the area R2 of the second conductive pad 260. For example, the first conductive pad 251 and the second conductive pad 260 have different areas and circular shapes.

Thus, even though the first conductive pads 251 and the second conductive pads 260 have the same shape, since the area R1 of one of the first conductive pads 251 located in the corner region 240 of the flip chip area 220 is larger than the area R2 of one of the second conductive pads 260, the present embodiment can increase the spacing G1 between the first solder ball portions 310 compared to the spacing G2 between the second solder ball portions 320, thereby reducing the bridging probability between the first solder ball portions 310 located in the corner region 240.

Fig. 5 is a flowchart of a method for manufacturing an electronic device according to an embodiment of the invention. As shown in fig. 1 and fig. 5, in the present embodiment, the method for manufacturing an electronic device includes steps 501 to 504 as follows.

In step 501, a semiconductor device 100 is provided. In more detail, the semiconductor device 100 includes a substrate 110 and a die 120, the die 120 is fixed on one surface of the substrate 110, and the other surface of the substrate 110 has a plurality of pads. In step 502, a circuit layout pattern of a circuit board 200 is designed. In step 503, a circuit board 200 is manufactured according to the circuit layout pattern. More specifically, the circuit board 200 has a flip-chip area 220, first conductive pads 250 and second conductive pads 260, the first conductive pads 250 are distributed in the central area 230 or all corner areas 240 of the flip-chip area 220, the second conductive pads 260 are distributed in the rest positions of the flip-chip area 220 except the positions of the first conductive pads 250, and the area R2 of each second conductive pad 260 is smaller than the area R1 of the first conductive pad 250. In step 504, the first pads 250 are connected to a portion of the solder joints through the first solder ball portions 310, and the second pads 260 are connected to another portion of the solder joints through the second solder ball portions 320, respectively, and the maximum width W1 of each of the second solder ball portions 320 is greater than the maximum width W2 of the first solder ball portions 310.

Fig. 6 is a detailed flow chart of step 502 of fig. 5. Fig. 7A is a schematic diagram of step 606 in conjunction with fig. 6. Fig. 7B is a schematic diagram of step 610 in conjunction with fig. 6. As shown in fig. 6, the step 502 further includes steps 601 to 611 as follows. In step 601, the semiconductor device 100 is subjected to warp measurement, and then, in step 602, the warp measurement is performed. In step 602, it is determined whether the substrate 110 of the semiconductor device 100 is curved in a smiling face shape, if so, step 603 is performed when it is determined that the substrate 110 is curved in a smiling face shape, otherwise, step 607 is performed.

In step 603, the design of the circuit layout pattern is changed such that the shape of the first conductive pads 250 is changed to be elliptical (fig. 3), the first conductive pads 250 are distributed in the central region 230 of the flip-chip region 220, and the second conductive pads 260 are distributed in the rest positions of the flip-chip region 220 except the central region 230 (including all corner regions 240 thereof), and the long axis direction 252 of each first conductive pad 250 passes through two adjacent sides E of the flip-chip region 220; next, the process proceeds to step 604. In step 604, a weld dummy test is performed; next, step 605 is performed. In step 605, according to the soldering virtual test, it is determined whether a soldering condition occurs between the first solder ball portions 310 in the central region 230, if yes, step 606 is performed, otherwise, step 503 (fig. 6) is continued. In step 606, the ratio of the numbers of the first conductive pads 250 to the second conductive pads 260 is gradually adjusted from the rectangular centroid 221 of the flip-chip region 220 toward the four directions (hereinafter referred to as the first direction D1) of all corner regions 240, respectively, and the process returns to step 604.

In step 607, it is determined whether the base 110 is curved in a crying face shape, if so, when it is determined that the base 110 is curved in a crying face shape, the process proceeds to step 608, otherwise, the process returns to step 601. In step 608, the design of the circuit layout pattern is changed such that the shape of the first conductive pads 250 is changed to be elliptical, the first conductive pads 250 are distributed in all corner regions 240 of the flip-chip area 220, and the second conductive pads 260 are distributed in the rest positions (including the central region 230) of the flip-chip area 220 except for all corner regions 240, and the long axis direction 252 of each first conductive pad 250 passes through two adjacent sides E of the flip-chip area 220. In step 609, a weld dummy test is performed, and then, in step 609, a weld dummy test is performed. In step 610, it is determined whether a fusion bonding condition occurs between the first solder ball portions 310 in all corner regions 240 according to the soldering virtual test, if so, step 611 is performed, otherwise, step 503 (fig. 5) is continued. In step 611, the ratio of the numbers of the first conductive pads 250 to the second conductive pads 260 is gradually adjusted from all corner regions 240 of the flip-chip region 220 toward the four directions (hereinafter referred to as the second direction D2) of the rectangular centroid 221, and the process returns to step 609.

More specifically, in step 601, the method further comprises performing moire optical measurement on the semiconductor device 100 to collect Shadow moire (Shadow)Data. As can be seen from the shadow moire data, the substrate 110 of the semiconductor device 100 is in a smiling face shape (e.g. the center of the substrate 110 is raised upwards, fig. 1) or a crying face shape (e.g. the center of the substrate 110 is raised downwards, not shown), but the invention is not limited thereto. In step 604 and step 609, the experimental design (Design of Experiments, DOE) is further included to perform a plurality of (e.g., 100) surface mount technologies (Surface Mount Technology, SMT), however, the present inventionThe invention is not limited thereto. The steps 605 and 610 further include the following steps. Whether or not a fusion condition occurs between the first solder ball portions 310 in the central region 230 is judged by a Failure Analysis (FA) tool or an X-ray (X-ray) perspective tool, however, the present invention is not limited thereto.

As shown in fig. 7A, the dots of the flip-chip region 222 in fig. 7A represent the pad (i.e., the first pad 250 and the second pad 260, refer to fig. 2). More specifically, in the step 502, the rectangular flip-chip region 222 is first divided into a plurality of square grids 400 (i.e. squares) with the same size by performing an image division technique, so that the square grids 400 are directly arranged according to a matrix of n×n (e.g. 4*4), and N is an integer greater than 2. The number of N may be determined according to the number of pads to be covered in each square 400.

Thus, when N is even, as shown in fig. 7A, the central region 230 is defined as four squares 400 adjacent to the rectangular centroid 221 of the flip-chip region 222; alternatively, when N is singular, the central region is defined as a single square (not shown) in the flip-chip region covering the centroid of the rectangle. In addition, all corner regions 240 are four squares 400 located at the rectangular corners 241 of the flip-chip region 222, respectively.

The details are further included in step 603 as follows. The first pads are not filled in the central region 230. More specifically, in the present embodiment, each diagonal 410 of the four squares 400 of the central area 230 together form a maximum virtual square 420 located in the four squares 400, and the maximum virtual square 420 is inscribed in the central area 230, and four corners 421 of the maximum virtual square 420 contact four side lines 231 of the central area 230, and the first pads 250 (fig. 2) are distributed only in the maximum virtual square 420 and not in the rest positions except the maximum virtual square 420 in the central area 230.

In step 606, the second conductive pad encountered by the first conductive pad is gradually changed to be configured with the first conductive pad according to the first direction D1. For example, the second pads in the rest positions of the central region 230 except the maximum virtual square 420 are changed to the first pads; then, if the welding condition still exists after the next welding virtual experiment (step 604 to step 605), step 606 may continue to change the second conductive pad encountered next into the first conductive pad according to the first direction D1, and thus, step 604 to step 606 are repeated until the welding condition no longer exists in the welding virtual experiment.

Similarly, as shown in fig. 7B, the dots of the flip-chip area 223 in fig. 7B represent the pad (i.e., the first pad 250 and the second pad 260, refer to fig. 2), and the flip-chip area 223 is divided into a plurality of square grids 400 with the same size, such that the square grids 400 are directly arranged according to a matrix of n×n (e.g., 4*4), and N is an integer greater than 2. The number of N may be determined according to the number of pads to be covered in each square 400. Thus, the definition of the central region 230 and all corner regions 240 are as described above.

The details are further included in step 608 as follows. The first conductive pad is not filled in all corner regions 240. More specifically, in the present embodiment, each corner area 240 is divided into a first virtual regular triangle 431 and a second virtual regular triangle 432 by a diagonal 430, respectively, and the first virtual regular triangle 431 connects the corresponding rectangular corners 241. These first pads are only distributed in the first virtual regular triangle 431 and not in the rest of the corner area 240 (i.e. the second virtual regular triangle 432).

In step 611, the second conductive pad encountered by the first conductive pad is gradually changed to be configured with the first conductive pad according to the second direction D2. For example, the second pads within the second virtual regular triangle 432 of the corner region 240 are modified to configure the first pads; then, if the welding condition still exists after the next welding virtual experiment (steps 609 to 610), step 611 may continue to change the second conductive pad encountered next into the first conductive pad according to the second direction D2, and thus, steps 608 to 611 are repeated until the welding condition no longer exists in the welding virtual experiment.

Thus, through the above structure, the present disclosure can reduce the chance of solder ball bridging on the circuit board, improve the connection performance between the semiconductor component and the circuit board, and improve the reliability of the semiconductor package element.

Finally, the embodiments disclosed above are not intended to limit the invention, but one skilled in the art can make various modifications and adaptations without departing from the spirit and scope of the invention. The scope of the invention is therefore defined in the appended claims.

Claims

1. An electronic device, comprising:

a semiconductor component comprising a substrate, a die and a packaging material, wherein the substrate comprises a first surface and a second surface which are opposite to each other, the first surface of the substrate is provided with a plurality of welding spots which are arranged at intervals, the die is fixed on the second surface of the substrate, and the packaging material coats the die on the substrate;

the circuit board is provided with a flip-chip area, wherein the flip-chip area is rectangular and is provided with a central area and a plurality of corner areas;

the first conductive pads are arranged in the central area or all the corner areas of the flip chip area at intervals, and are respectively connected with a part of welding spots through a plurality of first solder ball parts; and

a plurality of second conductive pads arranged in the rest positions of the flip chip region at intervals, and connected with the welding spots of the other part through a plurality of second solder ball parts respectively,

the area of each of the plurality of second conductive pads is smaller than that of one of the plurality of first conductive pads, and the maximum width of each of the plurality of second solder ball portions is larger than that of each of the plurality of first solder ball portions.

2. The electronic device of claim 1, wherein the plurality of first conductive pads are elongated, each of the plurality of first conductive pads has a long axis direction, the flip chip region has a horizontal line, the long axis direction has an angle with the horizontal line, and the angle is between 45 ° and 60 °.

3. The electronic device of claim 1, wherein the plurality of first pads are each elliptical in shape and each of the plurality of first pads has a major axis passing through two sides of the flip-chip region.

4. The electronic device of claim 1, wherein the first conductive pads and the second conductive pads are circular in shape with different areas.

5. The electronic device of claim 1, wherein when the flip chip region is divided into a plurality of equally sized squares by an image division technique, the squares are arranged directly according to an N by N matrix pattern,

wherein N is an integer greater than 2, the central region is at least one of the plurality of squares corresponding to or adjacent to the rectangular centroid of the flip-chip region, and all the plurality of corner regions are four of the plurality of squares located at the plurality of rectangular corners of the flip-chip region, respectively.

6. The electronic device of claim 5, wherein the substrate is curved in a smiling face shape, and a maximum virtual square is inscribed in the central region, four corners of the maximum virtual square respectively contact four edges of the at least one square, and the plurality of first conductive pads are only distributed in the maximum virtual square.

7. The electronic device of claim 5, wherein the substrate is curved in a crying face shape, and the four squares are each divided into two virtual regular triangles by a diagonal line, wherein the plurality of first conductive pads are distributed only in one of the two virtual regular triangles, and the two virtual regular triangles are connected to one of the corresponding rectangular corners.

8. A circuit board, comprising:

the plate body is provided with a flip-chip area on one surface, the flip-chip area is rectangular and is provided with a central area and a plurality of corner areas;

a plurality of first conductive pads arranged in the central area or all the corner areas at intervals; and

the second conductive pads are arranged in the rest positions of the flip chip area at intervals, wherein the area of each second conductive pad is smaller than that of one of the first conductive pads.

9. The circuit board of claim 8, wherein the plurality of first conductive pads are elongated, each of the plurality of first conductive pads has a long axis direction, the flip chip area has a horizontal line, the long axis direction has an angle with the horizontal line, and the angle is between 45 ° and 60 °.

10. The circuit board of claim 8, wherein the shapes of the plurality of first pads are respectively elliptical, and a long axis direction of each of the plurality of first pads passes through two sides of the flip chip region.

11. The circuit board of claim 8, wherein the first conductive pads and the second conductive pads are circular in shape with different areas.

12. The circuit board of claim 8, wherein when the flip-chip region is divided into a plurality of equally sized squares by an image division technique, the squares are arranged directly according to an N by N matrix pattern,

13. The circuit board of claim 12, wherein a largest virtual square is connected in the central region, four corners of the largest virtual square contact all edges of the at least one square, and the plurality of first conductive pads are distributed only in the largest virtual square.

14. The circuit board of claim 12, wherein the four squares are each divided into two virtual regular triangles by a diagonal, wherein the plurality of first pads are distributed only in one of the two virtual regular triangles, and the corresponding one of the plurality of rectangular corners is connected.

15. A method of manufacturing an electronic device, comprising:

providing a semiconductor component, wherein the semiconductor component comprises a substrate and a crystal grain, the crystal grain is fixed on one surface of the substrate, and the other surface of the substrate is provided with a plurality of welding spots;

designing a circuit layout pattern on a circuit board;

manufacturing the circuit board according to the circuit layout pattern, wherein the circuit layout pattern is provided with a flip-chip area, a plurality of first conductive connection pads and a plurality of second conductive connection pads, the plurality of first conductive connection pads are distributed in a central area or a plurality of corner areas of the flip-chip area, the plurality of second conductive connection pads are distributed on the rest positions of the flip-chip area, and the area of each of the plurality of second conductive connection pads is smaller than that of one of the plurality of first conductive connection pads; and

the first conductive pads are respectively welded with one part of the welding spots through a plurality of first solder balls, and the second conductive pads are respectively welded with the other part of the welding spots through a plurality of second solder balls, wherein the maximum width of each second solder ball is larger than that of each first solder ball.

16. The method of claim 15, wherein designing the circuit layout pattern on the circuit board further comprises:

performing warp measurement on the semiconductor component;

judging whether the substrate of the semiconductor component is in a smiling face type bending shape or not;

when the substrate is judged to be in a smiling face bending shape, the shapes of the first guide connection pads of the circuit layout pattern are designed to be elliptical and distributed in the central area of the flip chip area, and the second guide connection pads are distributed at the rest positions of the flip chip area except the central area, wherein a long axis direction of each first guide connection pad passes through two adjacent edges of the flip chip area;

performing a soldering virtual experiment, and judging whether a soldering condition is generated among the plurality of first solder ball parts in the central area of the circuit layout pattern; and

and when judging that the welding condition does not occur among the plurality of first solder ball parts, continuing to manufacture the circuit board.

17. The method of manufacturing an electronic device according to claim 16, wherein when it is determined that a fusion condition occurs between the plurality of first solder ball portions, further comprising:

and gradually adjusting the quantity proportion of the first conductive pads and the second conductive pads according to the directions from the rectangular centroid of the flip chip region to all the corner regions, and continuing the step of the welding virtual experiment.

18. The method of claim 16, wherein when the substrate of the semiconductor device is determined to be curved in a crying face shape, further comprising:

the shapes of the first guide connection pads of the circuit layout pattern are designed to be elliptical and distributed in all corner areas of the flip-chip area, and the second guide connection pads are distributed in other positions except all corner areas of the flip-chip area, wherein a long axis direction of each first guide connection pad passes through two adjacent sides of the flip-chip area;

performing a soldering virtual experiment, and judging whether the soldering condition is generated among the plurality of first solder ball parts in all corner areas of the flip chip region of the circuit layout pattern; and

19. The method of manufacturing an electronic device according to claim 18, wherein when it is determined that a fusion condition occurs between the plurality of first solder ball portions, further comprising:

and gradually adjusting the quantity proportion of the first conductive pads and the second conductive pads from all the corner areas of the flip chip area towards the directions of the rectangular centroids of the flip chip area, and continuing the step of the welding virtual experiment.