CN117336391A

CN117336391A - Detection method and device for analyzing CPU instruction, test system and equipment

Info

Publication number: CN117336391A
Application number: CN202311353418.6A
Authority: CN
Inventors: 刘金强; 黄河
Original assignee: Beijing Wuxin Technology Co ltd
Current assignee: Beijing Wuxin Technology Co ltd
Priority date: 2023-10-18
Filing date: 2023-10-18
Publication date: 2024-01-02

Abstract

The application provides a detection method and device for analyzing CPU instructions, a test system and equipment, wherein the method comprises the following steps: acquiring a first message sent to equipment to be tested, wherein the first message comprises a plurality of CPU instructions; executing a command analysis process when the first message is judged to be correct, wherein the command analysis process comprises the following steps: and analyzing the plurality of CPU instructions in the first message one by one, and when the analysis is normal, sequentially packaging the analysis results into corresponding second messages and sequentially sending the corresponding second messages to the comparator for verifying the instruction analysis results of the equipment to be tested by the comparator. The method and the device can not only check the message packaged with the plurality of CPU instructions, but also verify the analysis correctness and the processing correctness of the plurality of CPU instructions of the equipment to be tested.

Description

Detection method and device for analyzing CPU instruction, test system and equipment

Technical Field

The present invention relates to the field of internet communications, and in particular, to a method and apparatus for detecting CPU instruction resolution, a test system, and a device.

Background

In the field of internet communication, a CPU instruction is generally transmitted in a message form, and a receiving end parses the message, processes the CPU instruction contained in the message, generates a response message, and returns the response message to a transmitting end, thereby completing the interaction process of the CPU instruction.

For some application scenarios with high security requirements, when the receiving end analyzes the CPU instruction, a CPU instruction checker needs to be set, the CPU instruction is analyzed by the CPU instruction checker, and the analysis processing result of the CPU instruction checker is compared with the analysis result of the receiving end, so as to verify the correctness of the CPU instruction analyzed by the receiving end. However, the existing CPU instruction checker can only verify the resolution correctness of a single CPU instruction, and has insufficient capability for verifying the resolution correctness of a plurality of CPU instructions simultaneously.

Disclosure of Invention

In view of this, the present application proposes a method and apparatus for detecting CPU instruction analysis, a test system, and a device, which not only can check a packet in which a plurality of CPU instructions are packaged, but also can verify analysis correctness and processing correctness of a plurality of CPU instructions of a device to be tested.

In a first aspect, the present application provides a method for detecting CPU instruction resolution, including:

acquiring a first message sent to equipment to be tested, wherein the first message comprises a plurality of CPU instructions;

executing a command analysis process when the first message is judged to be correct, wherein the command analysis process comprises the following steps:

and analyzing the plurality of CPU instructions in the first message one by one, and when the analysis is normal, sequentially packaging the analysis results into corresponding second messages and sequentially sending the corresponding second messages to the comparator for verifying the instruction analysis results of the equipment to be tested by the comparator.

In the method for detecting the analysis of the CPU instructions, the first message sent to the equipment to be detected is judged, when the first message is correct, the plurality of CPU instructions packaged in the first message are analyzed one by one, analysis results are sequentially packaged into a plurality of second messages and sent to the comparator, the comparator also receives a plurality of messages generated by analysis results of the plurality of CPU instructions sent by the equipment to be detected, and the comparator can realize verification of the instruction analysis results of the equipment to be detected by comparing the plurality of second messages with the plurality of messages sent by the equipment to be detected.

Optionally, the method further comprises:

sequentially obtaining first response messages generated by the comparator for the second messages;

and packaging the data contained in each first response message into a second response message, and sending the second response message to the comparator for verifying the instruction processing result of the equipment to be tested by the comparator.

And the comparator can compare the second response messages with the response messages sent by the packaging of the equipment to be tested, thereby realizing verification of instruction processing results of the equipment to be tested.

Optionally, the method further comprises:

when judging that the first message is abnormal according to the message type contained in the first message, packaging the abnormal first message as a third response message of a suspension type;

and sending the third response message to a comparator for verifying the abnormal message analysis result of the equipment to be tested by the comparator.

From the above, the first message may be determined according to the message type included in the first message, and when the first message is determined to be abnormal, the abnormal first message is encapsulated into a third response message of the suspension type, and the third response message is sent to the comparator, so as to be used for verifying the abnormal message analysis result of the device to be tested by the comparator.

Optionally, the method further comprises:

when judging that the first message is a discarded message according to the message type contained in the first message, skipping the analysis of the discarded first message and generating no response message.

From the above, the first message can be judged according to the message type contained in the first message, and when the first message is judged to be the discarded message, the discarded first message is not required to be analyzed, and a response message is not required to be generated.

Optionally, the command parsing process further includes:

and discarding the CPU instruction exceeding the preset command length and the rest CPU instructions when any CPU instruction exceeding the preset command length is analyzed.

Optionally, the command parsing process further includes:

when any CPU instruction is analyzed to be abnormal, stopping analyzing the rest CPU instructions and executing an abnormal command processing process, wherein the abnormal command processing process comprises the following steps:

and packaging a fourth response message of a corresponding type according to the abnormal type, and sending the fourth response message to the comparator so as to be used for verifying an abnormal CPU instruction analysis result of the equipment to be tested by the comparator.

Therefore, the method and the device are mainly used for verifying the analysis accuracy and the processing accuracy of the CPU instructions by the device to be tested, and in the analysis process of the CPU instructions, when the CPU instructions exceed the preset command length, the CPU instructions and the remaining CPU instructions in the message can be directly discarded without being sent to the comparator for verifying the analysis results. When the CPU instruction is abnormal, the type of the abnormal CPU instruction can be packaged into a fourth response message of a corresponding type, the fourth response message is sent to the comparator to be used for verifying the analysis result of the abnormal CPU instruction of the equipment to be tested by the comparator, the type of the abnormality is recorded through an ERROR.TYPE variable, the counter is used for counting, and meanwhile, the analysis of the residual CPU instruction contained in the message can be stopped.

In a second aspect, the present application provides a detection apparatus for analyzing a CPU instruction, including:

the device comprises an acquisition unit, a processing unit and a processing unit, wherein the acquisition unit is used for acquiring a first message sent to equipment to be tested, and the first message comprises a plurality of CPU instructions;

an analysis unit: and executing a command analysis process when the first message is judged to be correct, wherein the command analysis process comprises the following steps: analyzing the CPU instructions in the first message one by one, and when the analysis is normal, sequentially packaging analysis results into corresponding second messages;

and the sending unit is used for sequentially sending the second messages to the comparator so as to be used for verifying the instruction analysis result of the equipment to be tested by the comparator.

Optionally, the obtaining unit is further configured to sequentially obtain each first response message generated by the comparator for each second message; the analysis unit is also used for packaging the data contained in each first response message into a second response message; the sending unit is further configured to send the second response packet to the comparator, so that the comparator is used to verify the instruction processing result of the device to be tested.

In a third aspect, the present application provides a test system for analyzing a CPU instruction, including the above-mentioned detection device and comparator for analyzing a CPU instruction;

the comparison device is used for receiving the analysis result of the first message by the detection device, receiving the analysis result of the first message by the equipment to be detected, and verifying the instruction analysis result of the equipment to be detected by comparing the two analysis results.

In a fourth aspect, the present application provides a computing device comprising:

a processor;

a memory for storing one or more programs;

when the one or more programs are executed by the processor, the processor is enabled to implement a method for detecting CPU instruction resolution as described above.

These and other aspects of the application will be apparent from and elucidated with reference to the embodiment(s) described hereinafter.

Drawings

FIG. 1 is a flowchart of a method for detecting CPU instruction resolution according to an embodiment of the present application;

fig. 2 is a block diagram of a detection device for analyzing CPU instructions according to an embodiment of the present application;

FIG. 3 is a block diagram of a test system for analyzing CPU instructions according to an embodiment of the present application;

fig. 4 is a block diagram of a computing device according to an embodiment of the present application.

It should be understood that in the foregoing structural schematic diagrams, the sizes and forms of the respective block diagrams are for reference only and should not constitute an exclusive interpretation of the embodiments of the present application. The relative positions and inclusion relationships between the blocks presented by the structural diagrams are merely illustrative of structural relationships between the blocks, and are not limiting of the physical connection of the embodiments of the present application.

Detailed Description

The technical scheme provided by the application is further described below by referring to the accompanying drawings and examples. It should be understood that the system structures and service scenarios provided in the embodiments of the present application are mainly for illustrating possible implementations of the technical solutions of the present application, and should not be construed as the only limitation of the technical solutions of the present application. As one of ordinary skill in the art can know, with the evolution of the system structure and the appearance of new service scenarios, the technical scheme provided in the application is applicable to similar technical problems.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. If there is a discrepancy, the meaning described in the present specification or the meaning obtained from the content described in the present specification is used. In addition, the terminology used herein is for the purpose of describing embodiments of the present application only and is not intended to be limiting of the present application.

The embodiment of the application provides a detection method for analyzing CPU instructions, which not only can be used for checking a message packaged with a plurality of CPU instructions, but also can be used for verifying the analysis correctness and the processing correctness of the plurality of CPU instructions of equipment to be tested.

As shown in fig. 1, the method for detecting CPU instruction analysis provided in the embodiments of the present application may be implemented by a detection device, where in a normal state, the analysis processing logic of the detection device for CPU instructions is the same as the analysis processing logic of the device to be tested for CPU instructions, so that the analysis processing result of the detection device for CPU instructions and the analysis processing result of the device to be tested for CPU instructions are compared, so that the analysis correctness and the processing correctness of multiple CPU instructions of the device to be tested can be verified. Referring to fig. 1, the method includes:

s110: acquiring a first message sent to equipment to be tested;

in this step, the first message sent to the device under test may be obtained synchronously by the detection device, where the first message may specifically be an RMU (Remote Management Unit, remote management) message, and the first message may include a plurality of mixed CPU instructions, for example, a normal CPU instruction, an abnormal CPU instruction, or a CPU instruction exceeding a preset length.

S120: executing a command analysis process when the first message is judged to be correct;

by checking the general bit field (e.g., message type) included in the obtained first message, it can be determined whether the first message is normal, and when the first message is normal, step S130 can be entered to execute the command parsing process.

In some embodiments, when the first message is judged to be an abnormal message according to the message type included in the first message, the abnormal first message is encapsulated into a third response message of a suspension (Abort) type, and the third response message is sent to the comparator, so that the comparator can be used for verifying an abnormal message analysis result of the device to be tested.

In other embodiments, when the first message is determined to be a dropped message according to the message type included in the first message, the parsing of the dropped first message may be skipped directly, and no response message need be generated.

S130: analyzing a plurality of CPU instructions in the first message one by one, and when the analysis is normal, sequentially packaging analysis results into corresponding second messages and sequentially sending the corresponding second messages to the comparator for verifying the instruction analysis results of the equipment to be tested by the comparator;

in this step, the detecting device analyzes the plurality of CPU instructions included in the normal first packet, stores the normal CPU instructions in an instruction+data manner in an analysis queue, and continues to analyze the next CPU instruction until the analysis of all the CPU instructions included in the first packet is completed, and then encapsulates the plurality of instructions+data stored in the analysis queue one by one to generate a plurality of corresponding second packets and sequentially sends the second packets to the comparator. Meanwhile, the comparator also receives a plurality of actual analysis messages sent by the device to be tested, the plurality of actual analysis messages are generated by analyzing a plurality of CPU instructions by the device to be tested through the same analysis logic, the second messages can be used as expected analysis messages in the comparator and used for comparing the plurality of actual analysis messages sent by the device to be tested, and therefore accuracy verification of analysis results of the plurality of CPU instructions of the device to be tested can be achieved.

In some embodiments, the comparator may be integrated with the detection device into one device, or may be used as a separate device to verify the analysis results of the detection device and the device under test.

It should be noted that, in the embodiment of the present application, when a certain resolved CPU instruction exceeds a preset command length in the resolving process of multiple CPU instructions, the CPU instruction exceeding the preset command length and the remaining CPU instructions in the message may be directly discarded, so that it is not necessary to generate a corresponding second message and send the second message to the comparator for verifying the resolving result. Or, in the process of analyzing the plurality of CPU instructions, when a certain analyzed CPU instruction is abnormal, a fourth response message of a corresponding type can be generated according to the type package of the abnormal CPU instruction, the fourth response message is sent to the comparator so as to be used for verifying the analysis result of the abnormal CPU instruction of the equipment to be tested by the comparator, then the comparator stops analyzing the rest CPU instructions included in the first message, the type of the abnormality is recorded through an ERROR.TYPE variable, and a corresponding abnormality type counter is increased by 1 so as to facilitate the user to review the recorded abnormality type.

In some embodiments, after the comparator completes verification of the instruction analysis result of the device to be tested, the comparator may further verify the instruction processing result of the device to be tested, where a specific verification process is as follows:

s140: sequentially obtaining first response messages generated by the comparator for the second messages;

in step S130, the detection device sequentially encapsulates the analysis result into corresponding second messages and sequentially sends the corresponding second messages to the comparator, specifically, a ping-pong sending manner may be adopted, that is, after each message is sent by the detection device, the detection device needs to receive a response message for the message, and then sends the next message. Therefore, the detection device can sequentially acquire the first response messages generated by the comparator for the second messages according to the sequence of the sent second messages.

S150: packaging data contained in each first response message into a second response message and sending the second response message to the comparator, so that the comparator can be used for verifying the instruction processing result of the equipment to be tested;

in this step, after the detection device sequentially obtains each first response message generated by the comparator for each second message, the first response message is stored in the response queue in a mode of command type + response state + data, after the storage of all the first response messages is completed, the check values of all the stored first response messages can be calculated, all the data stored in the response queue are packaged into one second response message, and the second response message is sent to the comparator. Similarly, when the device to be tested sends a plurality of actual analysis messages to the comparator in a ping-pong sending manner, a plurality of response messages generated by the comparator aiming at the plurality of actual analysis messages are sequentially obtained, and the device to be tested packages the plurality of response messages with the same processing logic to generate an actual response message and sends the actual response message to the comparator. The second response message can be used as an expected response message in the comparator and is used for comparing the actual response message sent by the equipment to be tested, so that the correctness verification of the processing results of the plurality of CPU instructions of the equipment to be tested can be realized.

In summary, in the method for detecting CPU instruction analysis provided in the embodiments of the present application, by determining a first packet sent to a device to be detected, when the first packet is correct, performing piece-by-piece analysis on a plurality of CPU instructions encapsulated in the first packet, and sequentially encapsulating analysis results into a plurality of second packets to be sent to a comparator, where the comparator further receives a plurality of packets generated by analysis results of the plurality of CPU instructions sent by the device to be detected, and the comparator performs a comparison between the plurality of second packets sent by the detection device and the plurality of packets sent by the device to be detected, so that verification of instruction analysis results of the device to be detected can be achieved; besides, the comparator can package a plurality of first response messages generated by the comparator for a plurality of second messages, generate a second response message and send the second response message to the comparator, the comparator also receives response messages packaged by processing results of a plurality of CPU instructions sent by the equipment to be tested, and the comparator can verify the instruction processing results of the equipment to be tested by comparing the second response messages sent by the detection device with the response messages sent by the equipment to be tested. Therefore, the embodiment of the application can realize verification of the analysis correctness and the processing correctness of a plurality of CPU instructions of the device to be tested, and overcomes the defect that the conventional CPU instruction checker can only verify the analysis correctness of a single CPU instruction.

As shown in fig. 2, the embodiment of the present application provides a device for detecting CPU instruction parsing, which may be used to implement any step of a method for detecting CPU instruction parsing shown in fig. 1 and an alternative embodiment thereof. Referring to fig. 2, the detecting apparatus includes an acquisition unit 210, an analysis unit 220, and a transmission unit 230.

The acquiring unit 210 is configured to acquire a first packet sent to a device under test, where the first packet includes a plurality of CPU instructions; the parsing unit 220 is configured to execute a command parsing process when the first message is determined to be correct, where the command parsing process includes: analyzing the CPU instructions in the first message one by one, and when the analysis is normal, sequentially packaging analysis results into corresponding second messages; the sending unit 230 is configured to send the second messages to the comparator in sequence, so as to be used for verifying the instruction analysis result of the device to be tested by the comparator.

In some embodiments, the obtaining unit 210 is further configured to sequentially obtain each first response message generated by the comparator for each second message; the parsing unit 220 is further configured to encapsulate data included in each first response packet into a second response packet; the sending unit 230 is further configured to send the second response message to the comparator, so that the comparator verifies the instruction processing result of the device to be tested.

As shown in fig. 3, the embodiment of the present application provides a system for testing CPU instruction resolution, which may be used to implement any of the steps of a method for testing CPU instruction resolution and an alternative embodiment thereof, as shown in fig. 1. Referring to fig. 3, the system includes a detection device 200, an comparator 300;

the comparator 300 is configured to receive an analysis result of the first message by the detection device 200, receive an analysis result of the first message by the device to be tested, and verify an instruction analysis result of the device to be tested by comparing the two analysis results.

It should be understood that the apparatus, system or unit in the embodiments of the present application may be implemented by software, for example, by a computer program or an instruction having the above functions, and the corresponding computer program or instruction may be stored in a memory inside the terminal, and the processor reads the corresponding computer program or instruction inside the memory to implement the above functions. Alternatively, the apparatus or module of the embodiments of the present application may be implemented by hardware. Still further, an apparatus or module in an embodiment of the present application may also be implemented by a combination of a processor and software modules.

It should be understood that, for details of processing of the apparatus, system or unit in the embodiments of the present application, reference may be made to the embodiments shown in fig. 1-2 and related expressions of related extended embodiments, and the embodiments of the present application will not be repeated here.

Fig. 4 is a block diagram of a computing device 500 provided in an embodiment of the present application. The computing device 500 includes: processor 510, memory 520, communication interface 530, bus 540.

It should be appreciated that the communication interface 530 in the computing device 500 shown in fig. 4 may be used to communicate with other devices.

Wherein the processor 510 may be coupled to a memory 520. The memory 520 may be used to store the program codes and data. Accordingly, the memory 520 may be a storage unit internal to the processor 510, an external storage unit independent of the processor 510, or a component including a storage unit internal to the processor 510 and an external storage unit independent of the processor 510.

Optionally, computing device 500 may also include a bus 540. The memory 520 and the communication interface 530 may be connected to the processor 510 via a bus 540. Bus 540 may be a peripheral component interconnect standard (Peripheral Component Interconnect, PCI) bus or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, among others. The bus 540 may be classified as an address bus, a data bus, a control bus, or the like. For ease of illustration, only one line is shown in fig. 4, but not only one bus or one type of bus.

It should be appreciated that in embodiments of the present application, the processor 510 may employ a central processing unit (central processing unit, CPU). The processor may also be other general purpose processors, digital signal processors (digital signal processor, DSP), application specific integrated circuits (application specific integrated circuit, ASIC), field programmable gate arrays (field programmable gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. Or the processor 510 may employ one or more integrated circuits for executing associated programs to carry out the techniques provided in embodiments of the present application.

The memory 520 may include read only memory and random access memory, and provides instructions and data to the processor 510. A portion of the processor 510 may also include non-volatile random access memory. For example, processor 510 may also store information of the device type.

When the computing device 500 is running, the processor 510 executes computer-executable instructions in the memory 520 to perform the operational steps of the method described above.

It should be understood that the computing device 500 according to the embodiments of the present application may correspond to a respective subject performing the methods according to the embodiments of the present application, and that the above-described other operations and/or functions of the respective modules in the computing device 500 are respectively for implementing the respective flows of the methods of the embodiments, and are not described herein for brevity.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Embodiments of the present application also provide a computer-readable storage medium having stored thereon a computer program for performing the above-described method when executed by a processor, the method comprising at least one of the aspects described in the above-described embodiments.

Any combination of one or more computer readable media may be employed as the computer storage media of the embodiments herein. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.

The computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations of the present application may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).

It should be noted that the embodiments described in this application are only some embodiments of the present application, and not all embodiments. The components of the embodiments of the present application, as generally described and illustrated in the figures, may be arranged and designed in a wide variety of different configurations. Thus, the above detailed description of the embodiments of the present application, provided in the accompanying drawings, is not intended to limit the scope of the application as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.

The terms first, second, third, etc. or module a, module B, module C, etc. in the description and in the claims, etc. are used solely for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order, as may be appreciated, if permitted, to interchange particular orders or precedence orders to enable embodiments of the present application described herein to be implemented in orders other than those illustrated or described herein.

In the above description, reference numerals indicating steps are not necessarily meant to be performed as such, but intermediate steps or replaced by other steps may be included, and the order of the steps may be interchanged or performed simultaneously where permitted.

The term "comprising" as used in the description and claims should not be interpreted as being limited to what is listed thereafter; it does not exclude other elements or steps. Thus, it should be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the expression "a device comprising means a and B" should not be limited to a device consisting of only components a and B.

Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, in the various embodiments of the application, where no special description or logic conflicts exist, the terms and/or descriptions between the different embodiments are consistent and may be mutually referenced, the technical features of the different embodiments may be combined to form a new embodiment according to their inherent logic relationships.

Note that the above is only the preferred embodiments of the present application and the technical principles applied. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, while the present application has been described in connection with the above embodiments, the present invention is not limited to the above embodiments, but may include many other equivalent embodiments without departing from the spirit of the present invention, and the present invention is also within the scope of protection.

Claims

1. The method for detecting the CPU instruction analysis is characterized by comprising the following steps:

2. The method as recited in claim 1, further comprising:

3. The method as recited in claim 1, further comprising:

4. The method as recited in claim 1, further comprising:

5. The method of claim 1, wherein the command parsing process further comprises:

6. The method of claim 1, wherein the command parsing process further comprises:

7. A detection apparatus for analyzing a CPU instruction, comprising:

8. The apparatus according to claim 7, wherein:

the acquisition unit is further used for sequentially acquiring each first response message generated by the comparator for each second message;

the analysis unit is also used for packaging the data contained in each first response message into a second response message;

the sending unit is further configured to send the second response packet to the comparator, so that the comparator is used to verify the instruction processing result of the device to be tested.

9. A test system for analyzing CPU instructions, comprising the detection device for analyzing CPU instructions and the comparator according to claim 7 or 8;

the comparison device is used for receiving the analysis result of the first message by the detection device, receiving the analysis result of the first message by the equipment to be detected, and verifying the instruction analysis result of the equipment to be detected by comparing the two processing results.

10. A computing device, comprising:

a processor;

a memory for storing one or more programs;

the one or more programs, when executed by the processor, cause the processor to implement a method of detecting CPU instruction resolution as claimed in any one of claims 1 to 6.