CN112699626B - Scheduling detection method and device, equipment and computer readable storage medium - Google Patents
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Abstract
The application relates to a scheduling detection method, a scheduling detection device, scheduling detection equipment and a computer readable storage medium. In an embodiment of the present application, the scheduling detection method may include: monitoring a scheduling module in the device to be tested; caching information in a scheduling request when the scheduling request entering the scheduling module is monitored; when the scheduling feedback sent by the scheduling module is monitored, releasing information of a corresponding scheduling request from a cache; and verifying the scheduling behavior of the tested device according to the scheduling feedback and/or the information in the scheduling request. The embodiment of the application can efficiently complete the system-level or subsystem-level verification of the chip.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method and apparatus for scheduling detection, a device, and a computer readable storage medium.
Background
Typically, the operation effect of the system-on-chip level or its subsystem level is verified by simulation. At present, system-level simulation and subsystem-level simulation are mainly realized by respectively performing module-level simulation on a plurality of circuit modules in a chip system or a subsystem. In the module-level simulation, the time sequence level comparison is mainly realized by comparing the simulation module (RM) with the scheduling result of the chip, and the time sequence level comparison simulation module needs to monitor the internal signal of the chip to ensure the accuracy of the comparison. When netlist simulation verification such as a synthesized netlist and a PR netlist is carried out, internal signals of a chip are presented in a netlist mode, accurate sampling and positioning are difficult to carry out, great difficulty is brought to time sequence level comparison, and because clocks of each circuit module in the chip are different and delay of each circuit module is dynamically changed, codes of simulation modules need to be debugged for each circuit module when the internal signals of the chip are sampled when the netlist simulation is carried out for each electronic module in the chip, a large amount of debugging time is needed, and efficiency is low. Especially after adding a standard delay format (Standard Delay Format, SDF) delay.
Disclosure of Invention
In view of the foregoing technical problems in the related art, the present application provides a scheduling detection method, apparatus, device, and computer-readable storage medium, so as to efficiently complete system-level or subsystem-level verification of a chip.
To achieve the above object, a first aspect of the present application provides a scheduling detection method, including:
monitoring a scheduling module in the device to be tested;
caching information in a scheduling request when the scheduling request entering the scheduling module is monitored;
when the scheduling feedback sent by the scheduling module is monitored, releasing information of a corresponding scheduling request from a cache;
and verifying the scheduling behavior of the tested device according to the scheduling feedback and/or the information in the scheduling request.
By the method, the interface signal of the tested device can be detected through monitoring the chip, namely the scheduling request and the scheduling feedback of the scheduling module in the tested device, so that the subsystem-level scheduling behavior or the system-level scheduling behavior of the chip can be detected efficiently, the chip can be realized without repeated debugging, the time can be effectively saved, and the efficiency is improved.
In at least some embodiments, the scheduling request includes a port number to which the message belongs and a priority to which the message belongs; the caching of the information in the scheduling request includes: and caching the information in the scheduling request by taking the combined information of the port to which the message belongs and the priority to which the message belongs in the scheduling request as an index.
By the method, efficient access of information in the scheduling request is realized.
In at least some embodiments, the verifying the scheduling behavior of the device under test includes: verifying whether the scheduling behavior of the tested device accords with a preset scheduling rule, if so, indicating that the scheduling behavior of the tested device is normal, and if not, indicating that the scheduling behavior of the tested device is abnormal; wherein the scheduling rules include one or more of the following: the method comprises the steps of signal time sequence of information in a scheduling request, signal time sequence of information in scheduling feedback, consistency of the scheduling feedback and channel associated information of a corresponding scheduling request, consistency of the number of the scheduling feedback and the number of cells of the corresponding scheduling request, and a preemption frame function.
By the method, verification of various system-level or subsystem-level scheduling behaviors in the device under test can be achieved through the monitoring chip, namely the scheduling request and the scheduling feedback of the scheduling module in the device under test.
In at least some embodiments, the verifying the scheduling behavior of the device under test includes: and if yes, indicating that the preemption frame scheduling behavior of the tested device is abnormal, and if not, indicating that the preemption frame scheduling behavior of the tested device is normal.
By the method, the detection of the scheduling behavior of the preemption frame function of the device under test can be realized through the monitoring chip, namely the scheduling request and the scheduling feedback of the scheduling module in the device under test.
In at least some embodiments, the verifying the scheduling behavior of the device under test comprises: verifying whether the quantity of scheduling feedback corresponding to a scheduling request is matched with the quantity of cells in the information of the scheduling request, if so, indicating that the scheduling behavior of the tested device is normal, and if not, indicating that the scheduling behavior of the tested device is abnormal.
By the method, the detection of the consistency of the number of the cells can be realized through the monitoring chip, namely the scheduling request and the scheduling feedback of the scheduling module in the tested device.
In at least some embodiments, the verifying the scheduling behavior of the device under test comprises: verifying whether the rising edge and the falling edge of the signal of the information in the scheduling request and/or the scheduling feedback are aligned with the clock divide-by-two of the tested device, if so, indicating that the scheduling behavior of the tested device is normal, and if not, indicating that the scheduling behavior of the tested device is abnormal.
By the method, the detection of the signal time sequence can be realized through the monitoring chip, namely the scheduling request and the scheduling feedback of the scheduling module in the tested device.
In at least some embodiments, the scheduling detection method further includes: and when the scheduling behavior of the tested device is verified to be abnormal, corresponding error information is generated.
By the method, the corresponding generation of error information during abnormality is realized, so that the report and the check by technicians are facilitated.
The first aspect of the present application provides a scheduling detection apparatus, including: the device comprises a monitoring module, a cache module, a release module and a verification module; wherein,
the monitoring module is configured to monitor the scheduling module in the tested device;
the cache module is configured to cache information in the scheduling request when the scheduling request entering the scheduling module is monitored;
the release module is configured to release the information of the corresponding scheduling request from the cache when the scheduling feedback sent by the scheduling module is monitored;
and the verification module is configured to verify the scheduling behavior of the tested device according to the scheduling feedback and/or the information in the corresponding scheduling request.
A third aspect of the present application provides a computing device comprising: a communication interface, and at least one processor; wherein the at least one processor is configured to execute program instructions that, when executed by the at least one processor, cause the computing device to implement the method of the first aspect described above.
A fourth aspect of the present application provides a computer readable storage medium having stored thereon program instructions which when executed by a computer cause the computer to implement the method of the first aspect described above.
Drawings
The various features of the present application and the connections between the various features are further described below with reference to the figures. The figures are exemplary, some features are not shown in actual scale, and some features that are conventional in the art to which this application pertains and are not essential to the application may be omitted from some figures, or features that are not essential to the application may be additionally shown, and combinations of the various features shown in the figures are not meant to limit the application. In addition, throughout the specification, the same reference numerals refer to the same. The specific drawings are as follows:
fig. 1 is a schematic flow chart of a scheduling detection method provided in an embodiment of the present application;
fig. 2 is a schematic structural diagram of a scheduling detection apparatus provided in an embodiment of the present application;
fig. 3 is a schematic deployment diagram of a scheduling detection apparatus provided in an embodiment of the present application;
fig. 4 is a schematic diagram of a computing device provided by an embodiment of the present application.
Detailed Description
The terms first, second, third, etc. or module a, module B, module C, etc. in the description and in the claims, etc. are used solely for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order, as may be appreciated, if permitted, to interchange particular orders or precedence orders to enable embodiments of the present application described herein to be implemented in orders other than those illustrated or described herein.
In the following description, reference numerals indicating steps such as S110, S120, … …, etc. do not necessarily indicate that the steps are performed in this order, and the order of the steps may be interchanged or performed simultaneously as allowed.
The term "comprising" as used in the description and claims should not be interpreted as being limited to what is listed thereafter; it does not exclude other elements or steps. Thus, it should be interpreted as specifying the presence of the stated features, integers, steps or components as referred to, but does not preclude the presence or addition of one or more other features, integers, steps or components, or groups thereof. Thus, the expression "a device comprising means a and B" should not be limited to a device consisting of only components a and B.
Reference in the specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but may. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments as would be apparent to one of ordinary skill in the art from this disclosure.
Through intensive research on system-level or subsystem-level verification of a chip, the inventor finds that the focus of the subsystem-level or system-level verification of the chip is not on details of specific scheduling sequences, specific scheduling times and the like of various circuit modules inside the chip, but on whether the scheduling behavior of the subsystem-level or system-level of the chip (i.e., macro scheduling behavior of the chip) accords with corresponding scheduling rules. Therefore, in order to solve the technical problems of long debugging time, low efficiency and the like in chip subsystem level or system level verification, the embodiments of the present application provide a scheduling detection method, a device, equipment and a computer readable storage medium, which realize the detection of a device interface signal to be tested by monitoring the scheduling request and the scheduling feedback of a scheduling module in a chip (i.e. a Device Under Test (DUT)) so as to efficiently complete the detection of subsystem level scheduling behavior or system level scheduling behavior of the chip, which can be realized without multiple times of debugging, thereby effectively saving time and improving efficiency.
Fig. 1 illustrates an exemplary flow of a schedule detection method 100 of an embodiment of the present application. Referring to fig. 1, the scheduling detection method in the embodiment of the present application may include the following steps:
step S110, monitoring a scheduling module in the tested device.
Step S120, when the scheduling request entering the scheduling module is monitored, information in the scheduling request is cached.
Step S130, when the scheduling feedback sent by the scheduling module is monitored, the information of the corresponding scheduling request is released from the cache.
Step S140, according to the information in the scheduling feedback and/or the scheduling request, the scheduling behavior of the tested device is verified.
By the steps, the detection of the interface signals of the tested device can be realized through monitoring the scheduling request and the scheduling feedback of the scheduling module in the chip (namely the tested device), so that the detection of the subsystem-level scheduling behavior or the system-level scheduling behavior of the chip can be efficiently finished, the detection can be realized without repeated debugging, the time can be effectively saved, and the efficiency is improved.
Fig. 2 shows an exemplary structure of a schedule detection apparatus 200 provided in an embodiment of the present application. Referring to fig. 2, the schedule detection apparatus 200 may include: a monitoring module 210, a caching module 220, a releasing module 230, and a verifying module 240. Wherein,
a monitoring module 210 configured to monitor a scheduling module in the device under test;
a caching module 220 configured to cache information in a scheduling request when the scheduling request entering the scheduling module is monitored;
the releasing module 230 is configured to release the information of the corresponding scheduling request from the cache when the scheduling feedback sent by the scheduling module is monitored;
and the verification module 240 is configured to verify the scheduling behavior of the device under test according to the scheduling feedback and/or the information in the scheduling request.
FIG. 3 shows a schematic diagram of a deployment architecture of a dispatch detection module, dispatch module, in a DUT in an embodiment of the present application.
An exemplary implementation of an embodiment of the present application is described in detail below in conjunction with fig. 1, 2, and 3.
Referring to fig. 3 below, a scheduling module of a device under test may receive a call request from its upper level module (e.g., the ingress scheduling module shown in fig. 3) through its ingress (e.g., the ingress queue management module shown in fig. 3), and the calling module may send scheduling feedback to its lower level module (e.g., the egress queue management module shown in fig. 3) through its egress (e.g., the egress scheduling module shown in fig. 3), whereby the DUT may schedule its individual electronic modules to implement its related functions (e.g., when the DUT is applied to a switch, its related functions may be, but are not limited to, message conversion, forwarding, etc.). In practice, both the ingress (e.g., the ingress scheduler module in FIG. 3) and egress (e.g., the egress scheduler module in FIG. 3) of the scheduler module may be, but are not limited to, software-defined interfaces.
In step S110, the entrance and exit of the scheduling module may be monitored simultaneously, that is, the entrance scheduling module and the exit scheduling module of the scheduling module in the DUT are monitored simultaneously. The following step S120 may be continued every time a scheduling request is detected to enter the scheduling module, and the following step S130 may be continued every time a scheduling feedback is detected to be sent out by the scheduling module. Because the scheduling request and the scheduling feedback both carry relevant information of the interface signal of the tested device (for example, a message received by the tested device, a port of a message sent by the tested device, a priority and the like), the embodiment of the application can realize the detection of the interface signal of the tested device through the monitoring scheduling module, thereby realizing the efficient detection of the scheduling behavior of the system level or the subsystem level of the tested device.
In some embodiments, taking fig. 3 as an example, the scheduling request herein may be, but is not limited to, a port queue scheduling request, and the information in the scheduling request may include, but is not limited to, the following information:
queue scheduling requests (e.g., 2 scheduling requests per message queue may be sent at most) by an egress queue management module (EQM);
the Port number to which the message belongs, namely the Port number of a Port Extender (PE) to which the message belongs, corresponds to a message scheduling destination Port number described below, and includes a physical Port number and an extended Port number, where the extended Port number may be a preemptive media access control (Preamble MAC, PMAC) Port number or a fast media access control (Express MAC, EMAC) Port number;
priority to which the message belongs;
the number of cells contained in the message;
the number of unused bytes in the tail cell;
message timestamp information, such as the time of receipt of the scheduling request;
the message discarding enabling can be returned when the scheduling result is fed back;
and sending an error flag of a message of the scheduling application to an exit scheduling module (ESCH).
In practical applications, a scheduling module usually identifies a port to which a message in a corresponding scheduling request belongs, a priority to which the message belongs, and other information, and the scheduling request and the scheduling feedback are associated through the information. Thus, in some embodiments, in step S120, the information in the scheduling request may be cached with the combined information of the port number to which the message belongs and the priority to which the message belongs in the scheduling request (for example, the scheduling queue number calculated by the port to which the message belongs and the priority to which the message belongs) as an index, so as to perform verification for the preemption frame function and the like in step S130.
For example, referring to fig. 3 below, a plurality of first-in first-out (FIFO) queues may be created in advance according to the message scheduling destination port and its priority, each FIFO queue being identified by the combined information of the message scheduling destination port number and the message priority (e.g., a scheduling queue number calculated from the message scheduling destination port number and the message priority). In step S120, the information in the scheduling request may be sent to the corresponding FIFO queue for buffering based on the port number to which the message in the scheduling request belongs and the priority to which the message belongs.
In some embodiments, still taking fig. 3 as an example, the scheduling feedback sent by the scheduling module (e.g., via the ESCH in the scheduling module) may be, but is not limited to, port queue scheduling feedback, which may be classified into low priority and high priority.
In some embodiments, the information in the scheduling feedback may include, but is not limited to, the following information:
a queue scheduling result is effectively indicated;
scheduling result port number, namely scheduling result PE port number;
scheduling result priority;
scheduling a cell sof (first cell flag bit) of the result;
scheduling cell eof (last cell flag bit) of the result;
the number of cells contained in the message;
the number of unused bytes in the tail cell;
scheduling an aging time scale corresponding to the result cell;
discarding registration corresponding to the scheduling result cell;
discarding marks corresponding to the scheduling result cells;
real time stamp information sent to the EQM.
In step S130, the corresponding FIFO queues may be queried according to the scheduling result port number and the scheduling result priority in the scheduling feedback, and the information corresponding to the scheduling request may be released therefrom.
In system level scheduling or subsystem scheduling of the DUT, the scheduling queue number of the scheduling request is consistent with the scheduling queue number requirement of the scheduling feedback. Here, the schedule queue number may be calculated according to the port number and the priority. For example, schedule queue number=port×8+prio, port represents port number, prio represents priority. In some embodiments, the information in the scheduling request may be cached according to the scheduling queue number, and in step S130, the scheduling queue number may be calculated by using the scheduling result port number and the scheduling result priority in the scheduling feedback, and then the information of the corresponding scheduling request may be released based on the scheduling queue number.
In step S140, whether the scheduling behavior of the device under test meets the predetermined scheduling rule or not may be verified by using the information in the scheduling feedback and/or the information in the scheduling request, if yes, it is indicated that the scheduling behavior of the device under test is normal, and if not, it is indicated that the scheduling behavior of the device under test is abnormal. Therefore, the purpose of detecting whether the scheduling of the tested device is correct can be achieved by verifying whether the scheduling rule is met.
Specifically, in step S140, verification may be performed for, but not limited to, the following scheduling rules: the method comprises the steps of signal time sequence of information in a scheduling request, signal time sequence of information in scheduling feedback, consistency of the scheduling feedback and channel associated information of a corresponding scheduling request, consistency of the number of the scheduling feedback and the number of cells (cells) of the corresponding scheduling request, and a preemptive frame function. Therefore, the detection of the system-level or subsystem-level scheduling behavior of the device under test (i.e., the macro-scheduling behavior of the device under test) can be realized based on the entry message and the exit message of the scheduling module such as the scheduling request, the scheduling feedback and the like. If any one or more scheduling rules are not satisfied, corresponding error information is generated, and the scheduling behavior of the device to be tested can be correct under the condition that all the scheduling rules are satisfied.
In practical applications, the signal timing requirements are generally predetermined (e.g., the length of the signal timing is not less than two clocks or one clock, etc.), and the signals of each circuit module in the DUT need to meet the predetermined requirements. Likewise, the scheduling request and the scheduling feedback also need to meet the requirements of the signal timing. In some embodiments, in step S140, it is verified whether the rising edge and the falling edge of the signal of the information in the scheduling request and/or the scheduling feedback are aligned with the clock divide by two of the device under test, if so, it indicates that the scheduling behavior of the device under test is normal, and if not, it indicates that the scheduling behavior of the device under test is abnormal. Specifically, verifying the signal timing of the information in the scheduling request includes verifying whether the rising edge and the falling edge of the signal of each information in the scheduling request information are aligned with the clock divide by two of the device under test, and verifying the signal timing of the information in the scheduling feedback includes verifying whether the rising edge and the falling edge of the signal of each information in the scheduling feedback are aligned with the clock divide by two of the device under test. Specifically, the signal timing for verifying an information in the scheduling request may include whether the rising edge of the signal is aligned with clock divide-by-two (soc) =0, and whether the falling edge of the signal is aligned with soc=1. Likewise, verifying the timing of the signal of an information in the scheduling feedback may include monitoring whether the rising edge of the signal of an information in the scheduling feedback is aligned with the soc=0 of the device under test and the falling edge is aligned with the soc=1 of the device under test.
The associated information is generally used for recovering the packet, and thus, it is necessary to ensure that the associated information in the scheduling feedback is consistent with the associated information in the scheduling request. In some embodiments, in step S140, it may be ensured that the next module of the scheduling module will not make an error when recovering the packet by verifying whether the associated information in the scheduling feedback is consistent with the associated information in the corresponding scheduling request. Specifically, the associated information may include message timestamp information, message discard enable, and number of unused bytes of the tail cell, and the verifying the associated information consistency in step S140 may include: judging whether the message time stamp information, the message discarding enabling information and the number of unused bytes of the message tail cell in the scheduling feedback are the same as the corresponding information in the corresponding scheduling request.
Typically, each scheduling feedback corresponds to one cell (cell), and each scheduling request may correspond to a plurality of cells. In some embodiments, in step S140, verifying the cell number consistency includes verifying whether the number of scheduling feedback corresponding to a scheduling request matches the cell number in the information of the scheduling request, that is, determining whether the number of scheduling feedback of a scheduling request is equal to the cell number. If the number of scheduling feedback of a scheduling request is matched with the number of cells in the information of the scheduling request, the scheduling behavior of the tested device is indicated to meet the requirement of consistency of the number of cells, and the scheduling behavior is normal; if the number of the scheduling feedback of a scheduling request is not matched with the number of the cells in the information of the scheduling request, the scheduling behavior of the tested device is not satisfied with the consistency requirement of the number of the cells, and the scheduling behavior is abnormal.
Here, the number of scheduling feedback of a scheduling request may be counted while monitoring the scheduling feedback. Specifically, counting starts when a scheduling feedback with a cell sof of 1 is detected, counting ends when a scheduling feedback with a scheduling queue number consistent with the scheduling feedback and a scheduling feedback with a cell eof of 1 is detected, and the value obtained by counting is the number of scheduling feedback of the same scheduling request.
In at least some embodiments, the verification of the preemption frame function may include: and if the low-priority scheduling feedback is detected, inquiring whether the information of the high-priority scheduling request with the same physical port number exists in the cache according to the physical port number of the scheduling feedback. If the message queue exists, the message queue of the high-priority port queue scheduling request is not scheduled according to the preemption rule, namely the scheduling of the device to be tested violates the preemption rule, and the preemption frame scheduling behavior of the device to be tested is abnormal; if the message queue does not exist, the scheduling of the message queue of the high-priority port queue scheduling request meets the preemption rule, namely the scheduling of the device to be tested meets the preemption rule, and the preemption frame scheduling of the device to be tested is normal.
The verification of the preemption frame function is described in detail below with one example.
Taking fig. 3 as an example, if the egress scheduling module is a KD6630 egress scheduling module, it needs to support the 802.1Qbu/802.3br Preemption Frame (Frame Preemption) function. The logical ports of the message scheduling can be divided into EMAC ports (high priority) and PMAC ports (low priority), and each combination of EMAC ports and PMAC ports corresponds to the same physical port. Assuming that a physical port is identified as n, its corresponding EMAC logical port may be identified as 2n+1 and its corresponding PMAC logical port may be identified as 2n. Correspondingly, the scheduling request is a port queue scheduling request, and the scheduling feedback is a port queue scheduling feedback.
Referring to fig. 3, a plurality of FIFO queues may be pre-established according to the destination port of the packet schedule and its physical port and priority, where each FIFO queue corresponds to a combination of the port number (including the physical port identifier and the logical port identifier) and the priority of the destination port of the packet schedule. In step S120, after monitoring a port queue scheduling request (a high priority port queue scheduling request or a low priority port queue scheduling request), the information in the port queue scheduling request is stored in the corresponding FIFO queue based on the port number and priority to which the message belongs. In step S130, if the port number to which the message of the scheduling feedback belongs indicates that the destination port of the message scheduling is PMAC logical port 2n of physical port n, it is queried whether the FIFO queue of physical port n and logical port EMAC logical port 2n+1 is empty, and if the FIFO queue is not empty, it is determined that there is still information of the scheduling request of the high priority port queue (i.e. the scheduling request of physical port n and logical port EMAC logical port 2n+1) in the buffer, and it may be determined that the scheduling of the device under test violates the preemption rule of the PMAC scheduling time slot of the EMAC preemptible physical port. If the physical port is n and the FIFO queue with the logical port being the EMAC logical port 2n+1 is empty, the information of the scheduling request of the high priority port queue (i.e. the scheduling request with the physical port being n and the logical port being the EMAC logical port 2n+1) does not exist in the buffer memory, and the scheduling accords with the preemption rule that the EMAC can preempt the PMAC scheduling time slot of the same physical port.
In this embodiment, after step S140, the scheduling detection method 100 may further include: step S150, when the scheduling behavior of the tested device is verified to be abnormal, corresponding error information is generated. Correspondingly, the schedule detecting apparatus 200 may further include: the prompting module 250 may be configured to generate corresponding error information when the verification module 240 verifies that the scheduling behavior of the device under test is abnormal. In the embodiment of the application, the abnormal condition of the scheduling behavior of the tested device can be recorded in real time through the error information, so that a user (for example, a chip debugging person) can check the abnormal condition of the tested device to correct the circuit design of the tested device in time.
Here, the error information may be used to describe the scheduling behavior in which the error occurred and the type of error thereof. That is, the error information may be used to describe at what time the scheduling of the device under test has made what kind of error. For example, the error information may include a port number to which the message belongs, a priority to which the message belongs, and message timestamp information, through which the user can know which schedule of the device under test has an error. In addition, information indicating a specific error type may be included in the error information. For example, assuming that the errors of the multiple scheduling rules mentioned in the above step S130 occur in the scheduling of the device under test, the error information may include an error code corresponding to each verification error in the multiple scheduling rules, so that, without multiple software debugging, a user (e.g., a debugger) can comprehensively know whether or not there are errors and which errors exist in the macro scheduling behavior of the system level or the subsystem level of the DUT by checking the error information, which is convenient, fast, time-saving and labor-saving.
In some embodiments, in step S150, after the error information is generated, the error information may be written in a predetermined file. Thus, not only can the error information be saved in real time, but also the error information in the predetermined file can be displayed in response to the operation of the user (such as a debugger) on the predetermined file, so that the user can conveniently check the error information at any time. Of course, any other similar manner of saving the error information may be used.
Fig. 4 is a schematic diagram of a computing device 400 provided by an embodiment of the present application. The computing device 400 includes: processor 410, memory 420, communication interface 430, bus 440.
It should be appreciated that the communication interface 430 in the computing device 400 shown in fig. 4 may be used to communicate with other devices.
Wherein the processor 410 may be coupled to a memory 420. The memory 420 may be used to store the program codes and data. Accordingly, the memory 420 may be a storage unit internal to the processor 410, an external storage unit independent of the processor 410, or a component including a storage unit internal to the processor 410 and an external storage unit independent of the processor 410.
Optionally, computing device 400 may also include a bus 440. The memory 420 and the communication interface 430 may be connected to the processor 410 through a bus 440. Bus 440 may be a peripheral component interconnect standard (Peripheral Component Interconnect, PCI) bus, or an extended industry standard architecture (Extended Industry Standard Architecture, EISA) bus, among others. The bus 440 may be classified as an address bus, a data bus, a control bus, etc. For ease of illustration, only one line is shown in fig. 4, but not only one bus or one type of bus.
It should be appreciated that in embodiments of the present application, the processor 410 may employ a central processing unit (central processing unit, CPU). The processor may also be other general purpose processors, digital signal processors (digital signal processor, DSP), application specific integrated circuits (application specific integrated circuit, ASIC), off-the-shelf programmable gate arrays (field programmable gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. Or the processor 410 may employ one or more integrated circuits for executing associated programs to carry out the techniques provided in embodiments of the present application.
The memory 420 may include read only memory and random access memory and provides instructions and data to the processor 410. A portion of the processor 410 may also include non-volatile random access memory. For example, the processor 410 may also store information of the device type.
When the computing device 400 is running, the processor 410 executes computer-executable instructions in the memory 420 to perform the operational steps of the schedule detection method described above.
It should be understood that the computing device 400 according to the embodiments of the present application may correspond to a respective subject performing the methods according to the embodiments of the present application, and that the above and other operations and/or functions of the respective modules in the computing device 400 are respectively for implementing the respective flows of the methods of the embodiments, and are not described herein for brevity.
Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.
In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The embodiments of the present application also provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, is configured to perform a scheduling detection method comprising at least one of the schemes described in the respective embodiments above.
Any combination of one or more computer readable media may be employed as the computer storage media of the embodiments herein. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. The computer readable storage medium can be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the computer-readable storage medium would include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In this document, a computer readable storage medium may be any tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device.
The computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, either in baseband or as part of a carrier wave. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A computer readable signal medium may also be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.
Program code embodied on a computer readable medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
Computer program code for carrying out operations of the present application may be written in one or more programming languages, including an object oriented programming language such as Java, smalltalk, C ++ and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computer (for example, through the Internet using an Internet service provider).
Note that the above is only a preferred embodiment of the present application and the technical principle applied. Those skilled in the art will appreciate that the present application is not limited to the particular embodiments described herein, but is capable of numerous obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the present application. Thus, while the present application has been described in terms of the foregoing embodiments, the present application is not limited to the foregoing embodiments, but may include many other equivalent embodiments without departing from the spirit of the present application, all of which fall within the scope of the present application.
Claims (9)
1. The scheduling detection method is characterized in that a device to be detected comprises a scheduling module, an entrance queue management module and an exit queue management module, wherein the scheduling module comprises an entrance scheduling module and an exit scheduling module, and the method comprises the following steps:
monitoring a scheduling module in the device to be tested;
when a scheduling request entering an entrance scheduling module of the scheduling module from an entrance queue management module is monitored, information in the scheduling request is cached;
when monitoring the scheduling feedback sent by the outlet scheduling module of the scheduling module to the outlet queue management module, releasing the information of the corresponding scheduling request from the cache;
verifying the scheduling behavior of the device under test according to the scheduling feedback and/or the information in the scheduling request;
the verifying the scheduling behavior of the device under test includes: verifying whether the scheduling behavior of the tested device accords with a preset scheduling rule, if so, indicating that the scheduling behavior of the tested device is normal, and if not, indicating that the scheduling behavior of the tested device is abnormal;
wherein the scheduling rules include one or more of the following: the method comprises the steps of signal time sequence of information in a scheduling request, signal time sequence of information in scheduling feedback, consistency of the scheduling feedback and channel associated information of a corresponding scheduling request, consistency of the number of the scheduling feedback and the number of cells of the corresponding scheduling request, and a preemption frame function.
2. The schedule detection method of claim 1, wherein,
the scheduling request comprises a port number to which a message belongs and a priority to which the message belongs;
the caching of the information in the scheduling request includes: and caching the information in the scheduling request by taking the combined information of the port to which the message belongs and the priority to which the message belongs in the scheduling request as an index.
3. The schedule detection method of claim 1, wherein validating the preemption frame function comprises: and if yes, indicating that the preemption frame scheduling behavior of the tested device is abnormal, and if not, indicating that the preemption frame scheduling behavior of the tested device is normal.
4. The schedule detection method of claim 1, wherein verifying the schedule feedback number consistent with the number of cells of the corresponding schedule request comprises: verifying whether the quantity of scheduling feedback corresponding to a scheduling request is matched with the quantity of cells in the information of the scheduling request, if so, indicating that the scheduling behavior of the tested device is normal, and if not, indicating that the scheduling behavior of the tested device is abnormal.
5. The scheduling detection method according to claim 1, wherein verifying the signal timing of the information in the scheduling request, the signal timing of the information in the scheduling feedback, comprises: verifying whether the rising edge and the falling edge of the signal of the information in the scheduling request and/or the scheduling feedback are aligned with the clock divide-by-two of the tested device, if so, indicating that the scheduling behavior of the tested device is normal, and if not, indicating that the scheduling behavior of the tested device is abnormal.
6. The schedule detection method according to claim 1, further comprising: and when the scheduling behavior of the tested device is verified to be abnormal, corresponding error information is generated.
7. A schedule detection apparatus, comprising: the device comprises a monitoring module, a cache module, a release module and a verification module; wherein,
the monitoring module is configured to monitor the scheduling module in the tested device; the device to be tested comprises a scheduling module, an inlet queue management module and an outlet queue management module, wherein the scheduling module comprises an inlet scheduling module and an outlet scheduling module;
the cache module is configured to cache information in a scheduling request when the scheduling request entering an entrance scheduling module of the scheduling module from the entrance queue management module is monitored;
the release module is configured to release information of a corresponding scheduling request from the cache when scheduling feedback sent by the outlet scheduling module of the scheduling module to the outlet queue management module is monitored;
the verification module is configured to verify the scheduling behavior of the tested device according to the scheduling feedback and/or the information in the corresponding scheduling request, and comprises the following steps: verifying whether the scheduling behavior of the tested device accords with a preset scheduling rule, if so, indicating that the scheduling behavior of the tested device is normal, and if not, indicating that the scheduling behavior of the tested device is abnormal; wherein the scheduling rules include one or more of the following: the method comprises the steps of signal time sequence of information in a scheduling request, signal time sequence of information in scheduling feedback, consistency of the scheduling feedback and channel associated information of a corresponding scheduling request, consistency of the number of the scheduling feedback and the number of cells of the corresponding scheduling request, and a preemption frame function.
8. A computing device, comprising:
a communication interface, a processor, a memory;
wherein the memory is for storing program instructions that, when executed by the processor, cause the computing device to implement the schedule detection method of any one of claims 1 to 6.
9. A computer readable storage medium having stored thereon program instructions, which when executed by a computer cause the computer to implement the schedule detection method of any one of claims 1 to 6.
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