CN1173277C - Device and method for transmitting registered data to PCI bus - Google Patents
Device and method for transmitting registered data to PCI bus Download PDFInfo
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- CN1173277C CN1173277C CNB011120053A CN01112005A CN1173277C CN 1173277 C CN1173277 C CN 1173277C CN B011120053 A CNB011120053 A CN B011120053A CN 01112005 A CN01112005 A CN 01112005A CN 1173277 C CN1173277 C CN 1173277C
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Abstract
The present invention relates to a device and a method for transmitting registered data to a PCI bus. The device and the method can reduce the delay time of output signals while circuit complexity does not have to be greatly increased. The device uses a 2R1W data buffer for delivering the data of a current phase and the data of a next phase the pulse period of an actual AD action of a PCI bus ahead, and the data of a current phase or the data of a next phase is selected by a multiplexer according to a selection signal which is the result of an or operation carried out by an IRDY# signal and a TRDY# signal. The device uses a trigger for driving the output signal of the multiplexer to the PCI bus in an actual AD action period. Therefore, the device of the present invention reduces the delay time of the output signal and can also be easily implemented.
Description
Technical field
Present invention is directed to the method and apparatus that transmits data, particularly about reducing the output delay of output signal time and not needing significantly to increase the apparatus and method of the data to PCI bus that the transmission of circuit complexity deposited.
Background technology
Computer system adopts one or more peripheral bus to make between the various devices and can connect each other usually.Contact between these devices (agent) is general to be carried out according to agreement.Wherein an agreement is Peripheral Component Interconnect (PCI) bus, when pulsed frequency during at 66MHz, allows the data communication frequency range of per second 266Mb.
Basically have a lot of devices simultaneously and be connected to pci bus.When the request end sent bus activity (bustransaction) to other receiving ends, pci bus was promptly carried out data and is transported.The request end is called as " main control end ", and receiving end is called as " controlled end ".When main control end OPADD/order to the controlled end, if the order of main control end is " writing " action, then main control end is then exported one group of data, controlled end is with the address/command decoding and receive data simultaneously; If the order of main control end is " reading " action, then controlled end echo back data.Therefore, bus activity comprises an address phase place (address phase) and one or more data phases afterwards (data phase).
It is to be controlled by three signals such as FRAME#, IRDY# and TRDY# that pci data transmits.The FRAME# signal is to be driven by main control end, uses the starting and ending that expression transmits action.The IRDY# signal is also driven by main control end, uses the controlled end of information notification of main control end being prepared to transmit data.And the TRDY# signal is to be driven by controlled end, uses the information notification main control end of controlled end being prepared to transmit data.If when FRAME# and IRDY# signal were not enabled, interface was to be in idle state.When the FRAME# signal is enabled, be regarded as the address phase place, and address/bus line command sign indicating number is sent at first edge of a pulse.When IRDY# and TRDY# are enabled, data after data phase during be sent.Transmit when main control end finishes last data, the FRAME# signal is not enabled.After controlled end was finished last data transmission, the TRDY# signal also was not enable, and interface is got back to idle state.
Fig. 1 shows that the output control logic of known main control end is connected to the functional block diagram of pci bus.Definition surpasses 47 pin positions in the regulation of pci bus, but only indicates AD bus AD[31:0 in this figure] 101.Phase data pointer 105, present phase place address pointer 106 and address phase place selection signal 107 are internal state signals of device at present.Phase data pointer 105 and present phase place address pointer 106 are the pointers by output action control at present, use and switch data and the address that is stored in impact damper 113 and 112 respectively.It is to be used for selecting address phase place or data phase that the address phase place is selected signal 107.Multiplexer 111 and I/O impact damper 110 are to be used for drive signal to pci bus.Data buffer and address buffer can be any type of enforcement.
Fig. 2 is a sequential chart of describing the running of the known main control end of Fig. 1.This figure first half shows the waveform of the internal signal of main control end, and Lower Half shows by the waveform of main control end drive output signal to pci bus.In the 3rd recurrence interval, this main control end utilizes multiplexer 111 to select signal 107 to select the address A that is exported from address buffer 112 according to the address phase place
j, and behind the delay D2 through this multiplexer 111 and I/O impact damper 110, with address A
jBe urged to pci bus.During the cycle, the address phase place selects signal 107 not enabled at next pulse, and this main control end utilizes multiplexer 111 to select signal 107 to select the data D that is exported from data buffer 113 according to the address phase place
j, and behind the delay D3 through this multiplexer 111 and I/O impact damper 110, with data D
jBe urged to pci bus.Because the no datat conversion is created in the 6th recurrence interval, D
jBe to keep to be urged to pci bus.After the 6th recurrence interval, TRDY# and IRDY# signal are enabled simultaneously, and the pointer j of phase data pointer 105 will change into j+1 at present.In addition, produce output delay by multiplexer 111 and I/O impact damper 110, data phase changes from D
jTo D
J+1Also cause some delays.
In addition, main control end will comprise a large amount of delays, for example D1 and D2 driving the AD signal to the pci bus as shown in Figure 1.This delay will be lowered controlled end in the time utilized that receives same pci bus signal.When the sequential cycle become shorter and shorter the time, will be difficult to make controlled end processing signals effectively.For example, at that time pulsed frequency when 66MHz and sequential cycle are 15ns, controlled end can't be at this short or even more in short-term during the preface in processing signals.
In order to solve above-mentioned delay issue, Fig. 3 discloses other circuit with two-layer pipeline (pipeline).The output control logic of known pipeline device is described by functional block diagram system shown in Figure 3.In this circuit structure, before sending to pci bus, earlier output signal is deposited, and before signal was transmitted, by 1R1W data buffer 310 one-period preparation in advance data, these data were next data 321.Apparently, this circuit must use other registers, uses and stored the initial value phase data before first data are output in pci bus.As shown in Figure 3, this circuit use two multiplexers 311 and 312 and two triggers 313 and 314 to keep just Value Data transmits successfully up to data.Yet the circuit of Fig. 3 is quite complicated.
Summary of the invention
The purpose of this invention is to provide and a kind ofly can reduce output signal time delay and not need significantly to increase the apparatus and method that data to PCI bus has been deposited in the transmission of circuit complexity.
The device of the data to PCI bus that transmission according to the present invention has been deposited, comprise: one has two reads the data buffer that mouth and is write inlet, be used for storing a plurality of data of depositing, and export present data-signal and next data-signal respectively according to present phase data pointer and next phase data pointer; One address buffer is used for storing the address, and according to the present address of phase place address pointer output at present; One first multiplexer is the present data-signal of receive data buffer and the address of address buffer, and selects signal to export present data-signal or address according to the address phase place; One logic gate is to receive IRDY# signal and TRDY# signal from pci bus, and output data transmits the selection signal; One second multiplexer is next data-signal of receive data buffer and the signal of first multiplexer output, and transmits the output signal of selecting signal to export next data-signal or first multiplexer according to data; And a trigger, be the output that receives second multiplexer, and the signal of this second multiplexer being exported according to reference pulse is urged to this pci bus.
The method of the data to PCI bus that a kind of transmission has been deposited comprises following steps:
(a) output step in address is exported an address signal to one first multiplexer by address buffer;
(b) data output step is exported present data-signal and next data-signal respectively to aforementioned first multiplexer and one second multiplexer by a data buffer;
(c) first logic step selects signal to export aforementioned present data-signal or aforementioned addresses signal by aforementioned first multiplexer according to an address phase place;
(d) second logic step transmits the signal of selecting signal aforementioned next data-signal of output or the output of aforementioned first multiplexer by aforementioned second multiplexer according to data; And
(e) actuation step is sent the output signal of aforementioned second multiplexer to pci bus by a trigger according to working pulse.
Therefore, present data and next data of being exported by the 2R1W data buffer are switched in combination by utilization IRDY# signal and TRDY# signal, and carry the previous work period address or data are sent to the trigger input end, send data or address to pci bus by trigger according to working pulse more at last.So data or address only can be subjected to the delay of trigger.
Description of drawings
Fig. 1 is the functional block diagram of known main control end output control logic.
Fig. 2 is a sequential chart of describing the known main control end practical operation of Fig. 1.
Fig. 3 is the functional block diagram of another output control logic of known main control end.
Fig. 4 is the functional block diagram that the present invention is applied to the output control logic of main control end.
Fig. 5 is a sequential chart of describing the circuit of Fig. 4 practical operation.
Fig. 6 is the functional block diagram that the present invention is applied to the output control logic of controlled end.
Fig. 7 is a sequential chart of describing the circuit of Fig. 6 practical operation.
Embodiment
Describe the apparatus and method that the present invention transmits the data to PCI bus of having deposited in detail below with reference to accompanying drawing, using is increasing under the circuit complexity not significantly, reduces the time delay that signal is sent in operation.
Fig. 4 shows that the present invention is applied to the functional block diagram of the output control logic of main control end.In the present embodiment, main control end 400 comprises the address buffer 411 that (2R1W) data buffer 410, a plurality of addresses of a storage are write in the second reading one that stores complex data.These 2R1W data buffer 410 foundations phase data pointer 407 are at present exported present data 404 and next data 403 respectively with next phase data pointer 406, and this 1R1W address date impact damper 411 is according to present phase place address pointer 408 output present addresses 405 simultaneously.This main control end 400 more comprises one first multiplexer 412 and one second multiplexer 413, uses and selects present data 404, next data 403 or present address 405.This first multiplexer 412 is connected to 2R1W data buffer 410 and 1R1W address buffer 411, and selects signal 409 to select present data 404 or present address 405 according to the address phase place.Simultaneously, second multiplexer 413 is connected to the 2R1W data buffer 410 and first multiplexer 412, and according to by or door 415 data that enable transmit the signal of selecting signals 401 to select next data 403 or first multiplexer 412 to be exported.Or door 415 reception IRDY# signal 421 and TRDY# signals 422, and carry out or (OR) computing.Main control end 400 uses a trigger 414 that the Pre-AD signal of second multiplexer, 413 outputs is driven into pci bus.This trigger 414 is the upper limb triggerings by pulse 424.
The main difference place of main control end of the present invention and known main control end uses 2R1W data buffer 410 at (as shown in Figure 1).This data buffer 410 is according to phase data pointer 407 and next phase data pointer 406 are exported present data 404 and next data 403 respectively at present.
Multiplexer 412 action is similar to multiplexer shown in Figure 1 111, triggers trigger 414 and uses the output signal that removing has been deposited except carrying the previous recurrence interval (in the cycle of the actual AD action of pci bus).After pci bus successfully transmits data, promptly utilize multiplexer 413 to select next data 403; Otherwise multiplexer 413 is selected the data of multiplexer 412 outputs, uses and keep identical data on pci bus.In addition, the gauge tap of multiplexer 413 is that data transmit to be selected signal 401, just with IRDY# signal 421 and TRDY# signal 422 as output that import or gate logic 415.After data successfully transmitted, data buffer 410 can next data of output.Otherwise multiplexer 413 will be selected by present phase data pointer 407 present data 404 pointed, and be output into Pre-AD signal 402.Trigger 414 and I/O impact damper 416 are used for depositing output signal in the present invention.Because the node of output trigger 414 only is connected to I/O impact damper 416, therefore advantage of the present invention is that the AD signal that slave flipflop 414 is exported can directly be sent to pci bus by I/O impact damper 416.
Fig. 5 is the sequential chart of Fig. 4 circuit running.This waveform also comprises the PCI write activity of most preferred embodiment of the present invention.The configuration of similar Fig. 2, this figure first half shows the waveform of the internal signal of main control end, and Lower Half shows the waveform that is exported to the output signal of pci bus by main control end.Note that internal signal of the present invention is carried the previous recurrence interval and exported data to trigger 414, promptly move fast one-period than actual AD in pci bus.In the present embodiment, it is 1 o'clock that the address phase place is selected signal 409, multiplexer 412 output address datas, and when the data transmission selects signal 401 to be 0, multiplexer 413 next data of output.Each signalizing activity in each cycle below is described, but omits the explanation of period 1.
When second recurrence interval, it is 1 and address buffer 411 OPADD A that the address phase place is selected signal 409
j, and data transmit to select signal 401 be 1.Therefore multiplexer 412 is selected signal 409 OPADD A according to the address phase place
jTo multiplexer 413, multiplexer 413 transmits according to data and selects signal 401 with address A simultaneously
jExport trigger 414 to.So in this cycle, Pre-AD signal 402 is address A
j
When the 3rd recurrence interval, the address phase place select signal 409 be 0 and data transmit that to select signal 401 be 1, data are D at present simultaneously
jMultiplexer 412 is selected the present data D of signal 409 outputs according to the address phase place
jTo multiplexer 413, multiplexer 413 transmits according to data and selects signal 401 with present data D simultaneously
jExport trigger 414 to.So in this cycle, Pre-AD signal 402 is present data D
j, and the AD signal is address A
j
When the 4th recurrence interval, it is 0 that the address phase place is selected signal 409, and data transmit that to select signal 401 be 1, and data are D at present simultaneously
jMultiplexer 412 is selected the present data D of signal 409 outputs according to the address phase place
jTo multiplexer 413, multiplexer 413 transmits according to data and selects signal 401 with present data D simultaneously
jExport trigger 414 to.So in this cycle, Pre-AD signal 402 is present data D
j, and the AD signal is present data A
j
When the period 5, it is 0 that the address phase place is selected signal 409, and because IRDY# signal 421 and TRDY# signal 422 are all 0, is 1 so data transmit selection signal 401, and next data is D simultaneously
J+1Multiplexer 413 transmits according to data selects signal 401 with next data D
J+1Export trigger 414 to.So in this cycle, Pre-AD signal 402 is next data D
J+1, and the AD signal is present data D
j
When the period 6, the address phase place select signal 409 be 0 and data transmit that to select signal 401 be 0, next data is D simultaneously
J+2Multiplexer 413 transmits according to data selects signal 401 with next data D
J+2Export trigger 414 to.So in this cycle, Pre-AD signal 402 is next data D
J+2, and the AD signal is next data D
J+1When the 7th cycle, the AD signal is next data D
J+2
Therefore, can know from Fig. 5 and see that main control end 400 of the present invention obviously shortens the time delay that the AD signal is urged to pci bus.
Fig. 6 shows that the present invention is applied to the functional block diagram of the output control logic of controlled end.As shown in the drawing, the structural similarity of controlled end is in the structure of main control end, except not having the address signal control circuit.Therefore, the circuit of the data transport mechanisms of Fig. 6 is the circuit that is similar to Fig. 4.Note that when main control end transmitted reading order, controlled end was urged to pci bus with corresponding data, so the transmission end can be main control end or controlled end.The present invention also can be applicable to the controller with same bus agreement.
Fig. 7 is the sequential chart of the circuit running of Fig. 6.This sequential chart is about the situation of main control end to controlled end issue reading command.In the 4th recurrence interval, when main control end drove the address or orders in pci bus, controlled end 600 can be to address or command decode.When controlled end 600 is confirmed as " reading " order, can after the 4th recurrence interval, begin to prepare data.The action in each cycle below is described respectively.
When the 4th recurrence interval, data transmit and select signal 601 is 1, and data are D at present
j, next data is D
J+1Therefore, multiplexer 611 transmits according to data and selects signal 601 with present data D
jExport trigger 612 to.So in this cycle, Pre-AD signal 602 is present data D
j, and the AD signal does not need.
When the 5th recurrence interval, data transmit and select signal 601 is 0, and data are D at present
j, next data is D
J+1Therefore, multiplexer 611 transmits according to data and selects signal 601 with next data D
J+1Export trigger 612 to.So in this cycle, Pre-AD signal 602 is next data D
J+1, and the AD signal is data D
j
When the 6th recurrence interval, main control end is set IRDY#621 and is enabled, and data transmit and select signal 601 is 1, and data are D at present
J+1, next data is D
J+2Therefore, multiplexer 611 transmits according to data and selects signal 601 with present data D
J+1Export trigger 612 to.So in this cycle, Pre-AD signal 602 is present data D
J+1, and the AD signal is data D
J+1
When the 7th recurrence interval, main control end is not set IRDY#621 to enable, and data transmit and select signal 601 is 0, and data are D at present
J+1, next data is D
J+2Therefore, multiplexer 611 transmits according to data and selects signal 601 with next data D
J+2Export trigger 612 to.So in this cycle, Pre-AD signal 602 is next data D
J+2, and the AD signal is data D
J+1
When the 8th recurrence interval, the 602 no effects of Pre-AD signal, and the AD signal is data D
J+2
Can recognize with reference to figure 5 to Fig. 7, most preferred embodiment of the present invention, propagation delay time D 4 and D5 are than known propagation delay time D 2 shown in Figure 2 and the next weak point of D3.In addition, the circuit complexity that the circuit of most preferred embodiment of the present invention can be not as shown in Figure 3.
Therefore above reference example of the present invention does not limit scope of the present invention, and only otherwise breaking away from claim covers, all corrections are not deviating under spirit of the present invention and the category, and those skilled in the art can carry out various distortion or change.
Claims (6)
1. the device of the data to PCI bus deposited of a transmission comprises:
One has two reads the data buffer that mouth and is write inlet, is used for storing a plurality of data of depositing, and exports present data-signal and next data-signal respectively according to present phase data pointer and next phase data pointer;
One address buffer is used for storing the address, and according to the present address of phase place address pointer output at present;
One first multiplexer is to receive the aforementioned present data-signal of aforementioned data impact damper and the aforementioned addresses of aforementioned addresses impact damper, and selects signal to export aforementioned present data-signal or aforementioned addresses according to the address phase place;
One logic gate is to receive IRDY# signal and TRDY# signal from pci bus, and output data transmits the selection signal;
One second multiplexer is to receive aforementioned next data-signal of aforementioned data impact damper and the signal of aforementioned first multiplexer output, and transmits the signal of selecting signal aforementioned next data-signal of output or the output of aforementioned first multiplexer according to aforementioned data; And
One trigger be the output that receives aforementioned second multiplexer, and the signal of this second multiplexer being exported according to reference pulse is urged to this pci bus.
2. the device of the data to PCI bus deposited of the transmission of putting down in writing as claim 1 more comprises:
One the one I/O impact damper is to be connected in aforementioned trigger, and the output signal of aforementioned trigger is urged to aforementioned pci bus;
One the 2nd I/O impact damper is to be connected in aforementioned logic gate, and transmits aforementioned IRDY# signal to this logic gate from aforementioned pci bus; And
One the 3rd I/O impact damper is to be connected in aforementioned logic gate, and transmits aforementioned TRDY# signal to this logic gate from aforementioned pci bus.
3. the device of the data to PCI bus deposited of the transmission of putting down in writing as claim 1, wherein aforementioned logic gate are one or door.
4. the device of the data to PCI bus deposited of the transmission of putting down in writing as claim 2, wherein aforementioned logic gate are one or door.
5. the method for the data to PCI bus deposited of a transmission comprises following steps:
Output step in address is exported an address signal to one first multiplexer by address buffer;
Data output step is exported present data-signal and next data-signal respectively to aforementioned first multiplexer and second multiplexer by a data buffer;
First selects step, selects signal to export aforementioned present data-signal or aforementioned addresses signal by aforementioned first multiplexer according to an address phase place;
Second selects step, transmits the signal of selecting signal aforementioned next data-signal of output or the output of aforementioned first multiplexer according to data by aforementioned second multiplexer; And
Actuation step is sent the signal of aforementioned second multiplexer output to pci bus by a trigger according to working pulse.
6. the method for the data to PCI bus deposited of the transmission of putting down in writing as claim 5, wherein aforementioned data transmits and selects signal system to be undertaken by IRDY# signal and TRDY# signal or (OR) result of computing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011120053A CN1173277C (en) | 2001-03-26 | 2001-03-26 | Device and method for transmitting registered data to PCI bus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011120053A CN1173277C (en) | 2001-03-26 | 2001-03-26 | Device and method for transmitting registered data to PCI bus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1376990A CN1376990A (en) | 2002-10-30 |
| CN1173277C true CN1173277C (en) | 2004-10-27 |
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ID=4659183
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB011120053A Expired - Fee Related CN1173277C (en) | 2001-03-26 | 2001-03-26 | Device and method for transmitting registered data to PCI bus |
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| Country | Link |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100424667C (en) * | 2004-11-23 | 2008-10-08 | 笙泉科技股份有限公司 | Data reading and writing method on bridging interface |
-
2001
- 2001-03-26 CN CNB011120053A patent/CN1173277C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100424667C (en) * | 2004-11-23 | 2008-10-08 | 笙泉科技股份有限公司 | Data reading and writing method on bridging interface |
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| Publication number | Publication date |
|---|---|
| CN1376990A (en) | 2002-10-30 |
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Granted publication date: 20041027 |