CN117319278A - Switch testing method and device, electronic equipment and storage medium - Google Patents
Switch testing method and device, electronic equipment and storage medium Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L43/00—Arrangements for monitoring or testing data switching networks
- H04L43/50—Testing arrangements
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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Abstract
The application provides a switch testing method, a device, electronic equipment and a storage medium. The method comprises the following steps: acquiring first information of a test message; forwarding and reflowing the first information of the test message according to a preset application-specific integrated circuit to obtain second information of the test message corresponding to the first information of the test message, wherein a transmitting pin and a receiving pin of the application-specific integrated circuit are connected; and performing switch performance test according to the first information of the test message and the second information of the test message to obtain a switch test result. Because the switch body is used as the carrier, the performance index of the switch can be calculated and obtained according to the receiving and transmitting test message without an Ethernet tester, the test cost and the test instrument requirement of the switch are reduced, the test period of the switch is shortened, and the test efficiency of the switch is improved.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a method and apparatus for testing a switch, an electronic device, and a storage medium.
Background
Along with the continuous expansion of the global network, the market scale of the switch is gradually expanded, so that the port forms of the switch are more and more rich to meet different demands of different users, and the requirements on the number of tester devices are gradually increased according to the scene that multiple projects are performed simultaneously.
In the test of network forwarding devices such as switches and routers, an ethernet traffic analysis tester is generally used for performing auxiliary test. However, these ethernet traffic analysis testers are expensive, and limited by the test cost, which results in shortage of tester equipment resources, and when multiple items are tested in parallel, reservation and scheduling processing are required. The switch test efficiency is low.
Disclosure of Invention
The application provides a switch testing method, a device, electronic equipment and a storage medium. The switch test result can be obtained by connecting the sending pin and the receiving pin of the application-specific integrated circuit, obtaining the first information of the test message, forwarding and reflowing to obtain the second information of the test message, and comparing the first information of the test message with the second information of the test message, thereby solving the problems of high cost of the switch test instrument and low test efficiency when equipment resources are short in the prior art.
In a first aspect, the present application provides a method for testing a switch, the method comprising:
acquiring first information of a test message;
forwarding and reflowing the first information of the test message according to a preset application-specific integrated circuit to obtain second information of the test message corresponding to the first information of the test message, wherein a transmitting pin and a receiving pin of the application-specific integrated circuit are connected;
and performing switch performance test according to the first information of the test message and the second information of the test message to obtain a switch test result.
Optionally, the switch testing method provided by the present application further includes:
and sending the first information of the test message to the application specific integrated circuit through the field programmable gate array.
Optionally, the switch testing method provided by the present application further includes:
determining, by the central processor, the RFC2544 first standard frame information from a plurality of RFC2544 standard frames of different frame lengths;
and sending the RFC2544 first standard frame information to the application specific integrated circuit through the field programmable gate array.
Optionally, the switch testing method provided by the present application further includes:
Transmitting the first information of the test message to the electrical loop jig through the transmitting pin;
and receiving the second information of the test message returned by the electric loop jig through the receiving pin.
Optionally, the switch testing method provided by the present application further includes:
receiving the intermediate information of the test message returned by the first jig through the first receiving pin;
transmitting the intermediate information of the test message to the second jig through the second transmitting pin;
and receiving second information of the test message returned by the second jig through the second receiving pin.
Optionally, the switch testing method provided by the present application further includes:
and connecting the transmitting pin and the receiving pin of the application-specific integrated circuit through the electric loop jig to obtain the application-specific integrated circuit with the flow looped.
Optionally, the switch testing method provided by the present application further includes:
comparing the number of the receiving and transmitting packets of the first information of the test message with the number of the second information of the test message to obtain a comparison result of the number of the first receiving and transmitting packets;
when the comparison result of the first receiving and transmitting packet number is that the number of data packets corresponding to the first information of the test message is the same as the number of data packets corresponding to the second information of the test message, obtaining third information of the test message, wherein the packet sending rate of the third information of the test message is greater than that of the first information of the test message;
Forwarding and reflowing the third information of the test message according to a preset application-specific integrated circuit to obtain fourth information of the test message corresponding to the third information of the test message;
carrying out receiving and transmitting packet number comparison on the third information of the test message and the fourth information of the test message to obtain a second receiving and transmitting packet number comparison result;
and when the comparison result of the second receiving and transmitting packet number is that the number of data packets corresponding to the third information of the test message is different from the number of data packets corresponding to the fourth information of the test message, generating the throughput test result according to the packet sending rate of the third information of the test message.
Optionally, the switch testing method provided by the present application further includes:
acquiring the round trip time of the test message according to the sending time of the first information of the test message and the receiving time of the second information of the test message;
and generating the switch time delay test result according to the round trip time of the test message.
Optionally, the switch testing method provided by the present application further includes:
determining the number of lost messages according to the number of messages of the first information of the test messages and the number of messages of the second information of the test messages;
And generating the switch packet loss rate test result according to the message number of the second information of the test message and the lost message number.
Optionally, the switch testing method provided by the present application further includes:
determining a first round trip time according to the sending time of the first information of the test message and the receiving time of the second information of the test message;
obtaining fifth information of a test message, and forwarding and reflowing the fifth information of the test message according to a preset application-specific integrated circuit to obtain sixth information of the test message corresponding to the fifth information of the test message;
determining a second round trip time according to the sending time of the fifth information of the test message and the receiving time of the sixth information of the test message;
and generating the switch instantaneous jitter test result according to the time difference corresponding to the first round trip time and the second round trip time.
Optionally, the switch testing method provided by the present application further includes:
comparing the switch test result with a preset RFC2544 standard to obtain a standard comparison result;
and outputting and displaying the standard comparison result.
In a second aspect, the present application further provides a switch testing apparatus, including:
The first test message acquisition module is used for acquiring first information of the test message;
the second test message acquisition module is used for forwarding and reflowing the first test message information according to a preset application-specific integrated circuit to obtain second test message information corresponding to the first test message information, wherein a transmitting pin and a receiving pin of the application-specific integrated circuit are connected;
and the test result generation module is used for performing switch performance test according to the first information of the test message and the second information of the test message to obtain a switch test result.
In a third aspect, the present application further provides a switch testing system, including:
the field programmable gate array end is used for acquiring the first information of the test message, sending the first information of the test message to the application-specific integrated circuit end, receiving the second information of the test message sent by the application-specific integrated circuit end, and performing the performance test of the switch according to the first information of the test message and the second information of the test message to obtain a test result of the switch;
the application-specific integrated circuit end is used for receiving the first information of the test message sent by the field programmable gate array end, forwarding and reflowing the first information of the test message to obtain second information of the test message corresponding to the first information of the test message, and sending the second information of the test message to the field programmable gate array.
In a fourth aspect, the present application also provides an electronic device comprising a processor and a memory storing a program or instructions executable on the processor, which when executed by the processor, implement the steps of the switch testing method according to the first aspect.
In a fifth aspect, embodiments of the present application provide a readable storage medium having stored thereon a program or instructions which, when executed by a processor, implement the steps of the switch testing method according to the first aspect.
In the technical scheme provided by the application specific integrated circuit, the sending pin and the receiving pin of the application specific integrated circuit are connected, the first information of the test message is obtained, forwarding and reflow processing is carried out to obtain the second information of the test message, and the first information of the test message is compared with the second information of the test message to obtain the test result of the switch. Because the switch body is used as the carrier, the performance index of the switch can be calculated and obtained according to the receiving and transmitting test message without an Ethernet tester, the test cost and the test instrument requirement of the switch are reduced, the test period of the switch is shortened, and the test efficiency of the switch is improved.
The foregoing description is merely an overview of the technical solutions provided in the present application, and may be implemented according to the content of the specification in order to make the technical means of the present application more clearly understood, and in order to make the above-mentioned and other objects, features and advantages of the present application more clearly understood, the following detailed description of the present application is given.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.
FIG. 1 is an example of an existing switch test apparatus provided herein;
FIG. 2 is an example of a switch test apparatus provided herein;
FIG. 3 is a schematic diagram of a switch testing method according to an embodiment of the present disclosure;
FIG. 4 is a second schematic diagram of a switch testing method according to an embodiment of the present disclosure;
FIG. 5 is a third exemplary embodiment of a method for testing a switch;
FIG. 6 is a schematic diagram of a switch testing method according to an embodiment of the present disclosure;
FIG. 7 is a fifth exemplary embodiment of a method for testing a switch;
FIG. 8 is a schematic diagram of a switch testing method according to an embodiment of the present disclosure;
FIG. 9 is a schematic diagram of a switch test method according to an embodiment of the present disclosure;
FIG. 10 is a schematic diagram eighth embodiment of a switch testing method;
FIG. 11 is a diagram illustrating a switch test method according to an embodiment of the present disclosure;
FIG. 12 is a schematic diagram of a switch test method according to an embodiment of the present disclosure;
FIG. 13 is a diagram of an eleventh embodiment of a method for testing a switch;
FIG. 14 is an example of switch test traffic transmission provided herein;
fig. 15 is a schematic diagram of a switch testing apparatus provided in an embodiment of the present application;
fig. 16 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
Exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type and not limited to the number of objects, e.g., the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.
First, the RFC2544 test and standards mentioned in this application will be briefly described: the RFC2544 standard defines a series of test methods and test indicators for testing the performance of devices, such as switches, as specified by the internet engineering task force for measuring the performance of devices, such as switches, under different load conditions. The standardized performance evaluation method is convenient for users to know the performance of the switch, and compares and eliminates faults among products of different switch manufacturers, so that the main stream operators of the switch and the switch equipment manufacturer are approved, and the method becomes a necessary test of the switch.
Along with the continuous expansion of the global network, the market scale of the switch is gradually expanded, so that the port forms of the switch are more and more rich to meet different demands of different users, and the requirements on the number of tester devices are gradually increased according to the scene that multiple projects are performed simultaneously. In particular, in the testing of network forwarding devices such as switches and routers, an ethernet traffic analysis tester is usually adopted to perform auxiliary testing, for example, an IXIA ethernet traffic analysis tester and a thread ethernet traffic analysis tester, but these ethernet traffic analysis testers have high price and are limited by testing cost, so that tester device resources are short-circuited. When multiple project parallel tests are required, a reservation scheduling process is required, impeding project progress.
In addition, the performance test of the switch, such as RFC2544 test, often requires complex configuration and identification to perform connection and parameter setting between the tested device and the tester, and for non-professional users or beginners, the test result is inaccurate due to the fact that the professional knowledge and experience are insufficient, and the test configuration is wrong. When the performance test of the switch is carried out by adopting the test tools such as the iporf, ttcp and the like, the test tools are limited by the test tools, and the switch can be simply tested, so that the accuracy and the comprehensiveness of the test result are poor.
For example, as shown in fig. 1, RFC2544 general modes are divided into two types, a stand-alone configuration and a dual-machine configuration. In a stand-alone architecture, a device under test (Device Under Test, DUT) and a test device (TestCenter) having both high performance transmit/receive ports perform a transmit/receive test, the test device transmits test data to the receive port of the DUT and forwards the test data from the transmit port of the DUT back to the receive port of the test device, and the test method has strict requirements on the port configuration of the test device, i.e., the test device must support the port configuration of the device under test. In the dual structure, a new test device is added to assist, test data is sent from the test device 1 (TestCenter 1) to the DUT, and the DUT sends the test data to the test device 2 (TestCenter 2), so that the performance of the tested device is judged according to the difference between the test data sent by the test device 1 and the test data received by the test device 2. However, in such a dual-machine structure, the introduction of the newly added test device 2 is liable to interfere with the transmission of test data due to its own instantaneous jitter and time delay, and the accuracy of the test results is poor.
According to the switch testing method, the RFC2544 protocol and the standard are taken as examples, on the premise that an Ethernet tester is not needed, a switch body to be tested is taken as a carrier, on the basis of the existing hardware design, a set of software testing flow and system are developed based on the RFC2544 protocol, testing items specified in the RFC2544 standard can be completed, testing results are output, compared with a traditional testing method, an expensive special testing instrument is not needed, extra configuration is not needed, an RFC2544 testing report can be accurately obtained, and the testing period is greatly shortened.
Specifically, as shown in fig. 2, the switch test system provided in the present Application includes a central processing unit (Central Processing Unit, CPU), a Field programmable gate array (Field-Programmable Gate Array, FPGA), and an Application-specific integrated circuit (ASIC).
The CPU is respectively connected with the FPGA and the ASIC through a high-speed serial computer expansion bus standard (PCI-Express, PCIE) bus to exchange data and receive and dispatch control signals, control the ASIC to configure forwarding rules, control the FPGA to send test messages of RFC2544 standard frames to the ASIC, and generate a test report according to test results obtained by calculation of the FPGA. Specifically, the CPU side has rich software environment, processes complex control logic and data flow, can easily realize configuration issuing through SDK and driving, and rapidly derives a test result by virtue of a python library to generate a test report.
The FPGA is connected with the ASIC through a communication bus interface, such as a KR interface, and according to CPU configuration, eight standard frames of 32 bytes, 64 bytes, 128 bytes, 256 bytes, 512 bytes, 1024 bytes, 1280 bytes and 1518 bytes are supported, and meanwhile, a random byte is supported, so that a test message can be sent to the ASIC, and according to RFC2544 standard, performance data such as packet loss rate, time delay, instantaneous jitter and throughput of a switch to be tested are obtained through calculation. Specifically, the network protocol of the FPGA accelerates and the parallelism of hardware at the data layer, the FPGA and the CPU are divided into boundaries at the protocol processing layer, the protocol processing and other intensive computation parallel processing are realized, the line speed transmission of all packet length messages and the multi-port flow processing are realized, the low time delay and the high throughput are provided, and the programmability of the FPGA enables the tester to be flexibly configured and customized according to different test requirements. By modifying the logic and algorithm of the FPGA, the FPGA can be optimized for specific test scenes and requirements, and more accurate and precise test results are provided. This flexibility allows the heterogeneous tester to accommodate different types of network devices and application scenarios.
The ASIC is an exchange chip, and can be responsible for forwarding the two-layer traffic according to the rule issued by the CPU, and is a tested main body. Specifically, a forwarding rule is configured according to a CPU instruction, VLAN/IP is configured according to a test requirement, for example, the port number requirement, an electric loop (Electrical Loopback, eloop) jig is used on a port, a self-loop is formed by a transmitting pin (tx) and a receiving pin (rx) of a port (port) connected by a path (Lane), and flow is looped in a VLAN configuration mode, so that the dependence on an external tester or a configuration switch is removed. When testing of a plurality of ports is needed, a self-loop of each tx and rx is formed for a plurality of ports, such as a plurality of ports port1, port2, port3, port x and the like through an Eloop jig, so that the test requirement of the port number is met.
The switch testing method, device, system, electronic equipment and non-volatile readable storage medium provided by the application are described in detail below with reference to the accompanying drawings by means of specific embodiments and application scenes thereof.
A first embodiment of the present application relates to a switch testing method, as shown in fig. 3, including:
step 101, acquiring first information of a test message;
Step 102, forwarding and reflowing the first information of the test message according to a preset application-specific integrated circuit to obtain second information of the test message corresponding to the first information of the test message, wherein a transmitting pin and a receiving pin of the application-specific integrated circuit are connected;
and step 103, performing switch performance test according to the first information of the test message and the second information of the test message to obtain a switch test result.
Specifically, in the switch testing method provided by the application, after the switch to be tested is powered on, the initialization of the ASIC is performed, the port of the panel is inserted into the ELoop, the port is ensured to be in the linking up state, and the configuration of the AIC VLAN is performed on the CPU side. First, a test message is sent to the ASIC by the CPU, where the test message may be marked as a first message of the test message and distinguished from a last received test message returned from the ASIC. And then, the ASIC carries out forwarding and reflow processing on the first information of the test message sent by the CPU, and as the sending pin and the receiving pin of the ASIC are connected, the first information is transmitted from the port to the ELoop through tx and returned to the port through rx, and finally, the second information of the test message is returned to the CPU. Because the content of the first information of the test message and the second information of the test message does not change substantially, the change of the test message transmitted in the ASIC is obtained according to the comparison of the first information of the test message and the second information of the test message, so that the test result of the switch is obtained.
In the technical scheme provided by the application specific integrated circuit, the sending pin and the receiving pin of the application specific integrated circuit are connected, the first information of the test message is obtained, forwarding and reflow processing is carried out to obtain the second information of the test message, and the first information of the test message is compared with the second information of the test message to obtain the test result of the switch. Because the switch body is used as the carrier, the performance index of the switch can be calculated and obtained according to the receiving and transmitting test message without an Ethernet tester, the test cost and the test instrument requirement of the switch are reduced, the test period of the switch is shortened, and the test efficiency of the switch is improved.
On the basis of the above embodiment, as shown in fig. 4, the method is applied to a switch test system, where the switch test system includes an application specific integrated circuit and a field programmable gate array, and step 101 includes:
and step 111, sending the first information of the test message to the application specific integrated circuit through the field programmable gate array.
Specifically, in the switch test method provided by the application, the switch test system not only comprises a CPU and an ASIC, but also comprises an FPGA, and after the switch to be tested is powered on, the initialization of the ASIC and the initialization of the FPGA are required. At this time, the CPU controls the FPGA to send the first information of the test message to the ASIC, and the FPGA receives the second information of the test message transmitted back by the ASIC', and the FPGA calculates the performance data and generates the test result of the switch. And the CPU outputs and displays the switch test result calculated by the FPGA, for example, generates a corresponding test report.
On the basis of the embodiment, as the CPU and FPGA heterogeneous switch test method is adopted, compared with a method which simply relies on the CPU to carry out data receiving and transmitting and data processing, the method has higher accuracy and reliability, can process a large number of data streams and high-speed data packet processing requirements, and improves the switch test quality and application range.
On the basis of the above embodiment, as shown in fig. 5, the switch test system further includes a central processor, the first information of the test message includes RFC2544 first standard frame information, and in the switch test method provided in the present application, step 111 includes:
112, determining, by the central processing unit, the RFC2544 first standard frame information from a plurality of RFC2544 standard frames with different frame lengths;
step 113, sending the first standard frame information of the RFC2544 to the application specific integrated circuit through the field programmable gate array.
Specifically, in the switch testing method provided by the application, the frame length of the first information of the test message can be adjusted according to the switch testing requirement, and the switch is comprehensively tested through the first information of the test messages with different frame lengths. For example, test messages corresponding to a plurality of RFC2544 standard frames with different frame lengths are pre-stored in a switch test system, when a switch test is required, a CPU determines RFC2544 first standard frame information from the RFC2544 standard frames with different frame lengths as first information of the test message, and sends the RFC2544 first standard frame information to an ASIC through an FPGA to perform the switch test.
The first standard frame information of RFC2544 is mainly selected from test messages corresponding to multiple RFC2544 standard frames according to frame lengths, the frame lengths can be determined according to switch test requirements set by users, one frame length can also be randomly selected from 7 different frame lengths, and the test message corresponding to the relevant RFC2544 standard frame is used as the first information of the test message.
On the basis of the above embodiment, as shown in fig. 6, the application specific integrated circuit is connected to the electrical loop fixture, and in the switch testing method provided in the present application, step 102 includes:
step 121, transmitting the first information of the test message to the electrical loop fixture through the transmitting pin;
step 122, receiving the second information of the test message returned by the electrical loop fixture through the receiving pin.
Specifically, in the switch test method provided by the application, the effect that the test message is sent from tx and received from r can be achieved through the Eloop connected with the ASIC, that is, the ASIC forwards and returns the first information of the test message sent by the CPU.
On the basis of the above embodiment, as shown in fig. 7, the transmitting pin includes a second transmitting pin, the receiving pin includes a first receiving pin and a second receiving pin, the electrical loop fixture includes a first fixture and a second fixture, and in the switch testing method provided in the present application, step 122 includes:
step 123, receiving the test message intermediate information returned by the first jig through the first receiving pin;
step 124, transmitting the intermediate information in the test message to the second fixture through the second transmitting pin;
step 125, receiving second information of the test message returned by the second fixture through the second receiving pin.
Specifically, in the switch testing method provided by the application, testing of multiple ports of the ASIC can be performed according to the number of ports in the switch testing requirements. In the ASIC VLAN configuration stage of the CPU before testing, the CPU marks KR1 and Port1 as VLAN10, port1 and Port2 as VLAN11, port2 and Port3 as VLAN12, and so on, port55 and Port56 as VLAN65 and Port56 and KR2 as VLAN67. After the ASIC receives the first information of the test message transmitted by the FPGA through the CHIP2CHIP connection, the first information of the test message is transmitted to the first jig through the tx of the port1 (port 1), the intermediate information of the test message transmitted by the first jig is received through the rx, then the intermediate information of the test message is transmitted to the second jig through the tx of the port2 (port 2), and the second information of the test message returned by the second jig is received through the rx, so that the flow looping of the ASIC is realized. When the number of the switch test pairs and the ports is greater than 2, the data transmission modes of the other ports are the same as the above modes, and the application is not repeated.
On the basis of the foregoing embodiment, as shown in fig. 8, in the switch testing method provided in the present application, before step 121, the method further includes:
and 126, connecting the transmitting pin and the receiving pin of the application-specific integrated circuit through the electric loop jig to obtain the application-specific integrated circuit with the flow looped.
Specifically, in the switch testing method provided by the application, before the switch test is performed, tx and rx of each port in the ASIC are connected through the ELoop, so that the effect that a test message can be sent to the ELoop through tx and returned to the original port through rx is ensured.
On the basis of the embodiment, the tx and the rx of the ASIC port are connected through the elop, so that the ASIC can realize the backflow of the test message, the smooth proceeding of the switch test is ensured on the premise of not adding a test instrument, and the universality of the switch test method provided by the application is improved.
On the basis of the above embodiment, as shown in fig. 9, the switch performance test includes a switch throughput test, and the switch test result includes a switch throughput test result.
Step 131, comparing the number of the receiving and transmitting packets of the first information of the test message and the second information of the test message to obtain a comparison result of the number of the first receiving and transmitting packets;
step 132, when the comparison result of the number of the first receiving and transmitting packets is that the number of data packets corresponding to the first information of the test message is the same as the number of data packets corresponding to the second information of the test message, obtaining third information of the test message, wherein the packet sending rate of the third information of the test message is greater than the packet sending rate of the first information of the test message;
step 133, forwarding and reflowing the third information of the test message according to a preset application specific integrated circuit to obtain fourth information of the test message corresponding to the third information of the test message;
step 134, comparing the number of the receiving and transmitting packets of the third information of the test message with the fourth information of the test message to obtain a second receiving and transmitting packet number comparison result;
and 135, when the comparison result of the second transceiving packet number is that the number of data packets corresponding to the third information of the test message is different from the number of data packets corresponding to the fourth information of the test message, generating the throughput test result according to the packet sending rate of the third information of the test message.
Specifically, in the switch testing method provided by the application, the throughput of the switch can be tested. After the FPGA acquires the second information of the test message transmitted by the ASIC, comparing the number of data packets of the first information of the test message with the number of data packets of the second information of the test message, when the number of data packets of the first information of the test message is the same as the number of data packets of the second information of the test message, increasing the packet sending rate, sending the third information of the test message to the ASIC, receiving the fourth information of the test message returned by the ASIC, and when the number of data packets of the third information of the test message and the fourth information of the test message is different, indicating that the throughput upper limit of the switch is reached, and taking the packet sending rate of the third information of the test message as the throughput test result of the switch test. When the number of the data packets of the third information of the test message and the fourth information of the test message is the same, the packet sending rate is continuously increased, the number of the data packets is compared, and the throughput test result is determined until the number of the data packets is inconsistent.
In order to improve the test efficiency, the continuous data flow can be sent to the ASIC through the FPGA, the number of data packets returned by the ASIC is continuously recorded, when the number of the received packets is consistent, the packet sending rate is continuously increased until the number of the received packets is different, and the throughput test result is determined according to the packet sending rate at the moment.
On the basis of the embodiment, the switch test method can test the throughput of the switch, and the switch test result carries the throughput performance index of the switch, so that the application range of the switch test method is expanded, and the comprehensiveness of the switch test is ensured.
On the basis of the above embodiment, as shown in fig. 10, the switch performance test includes a switch delay test, and the switch test result includes a switch delay test result.
136, acquiring the round trip time of the test message according to the sending time of the first information of the test message and the receiving time of the second information of the test message;
and 137, generating the switch time delay test result according to the round trip time of the test message.
Specifically, in the switch testing method provided by the application, the time delay of the switch can be tested. And acquiring the round trip time of the test message according to the sending time of the first information of the test message and the receiving time of the second information of the test message, and determining the time delay of the switch according to the round trip time of the test message. For example, the sending rate of the first information of the album number message is set to be a fixed value, and the ASIC is continuously expected to send test messages, the arrival time of each test message returned to the FPGA is recorded, and the round trip time of each data packet is determined according to the arrival time and the sending time, so as to obtain the time delay of a single data packet. In order to avoid data fluctuation, the method and the device can also obtain the average value according to the plurality of time delays to obtain the average time delay of the switch, and the average time delay is used as a switch time delay test result.
On the basis of the embodiment, the switch testing method can test the time delay of the switch, and the switch testing result carries the time delay performance index of the switch, so that the application range of the switch testing method is expanded, and the comprehensiveness of switch testing is ensured.
On the basis of the above embodiment, as shown in fig. 11, the switch performance test includes a switch packet loss rate test, and the switch test result includes a switch packet loss rate test result.
Step 138, determining the number of lost messages according to the number of messages of the first information of the test message and the number of messages of the second information of the test message;
and 139, generating a packet loss rate test result of the switch according to the number of messages of the second information of the test messages and the number of the lost messages.
Specifically, the switch testing method provided by the application can test the packet loss rate of the switch. Determining the number of messages lost in the transmission process of the test messages according to the number of messages of the first information of the test messages and the number of messages of the second information of the test messages, and determining the packet loss rate of the switch according to the number of messages to be found and the total number of messages corresponding to the first information of the test messages, thereby obtaining the packet loss rate test result of the switch.
In order to avoid errors and improve test accuracy, the sending rate of the first information of the test message can be set to be a fixed value, the first information of the test message is continuously sent to the ASIC, a plurality of packet loss rates are obtained through calculation, then an average value is obtained according to the plurality of packet loss rates, and therefore the average packet loss rate of the switch is obtained, and finally the switch packet loss rate test result is obtained.
On the basis of the embodiment, the switch testing method can test the packet loss rate of the switch, and the switch testing result carries the packet loss rate performance index of the switch, so that the application range of the switch testing method is expanded, and the comprehensiveness of switch testing is ensured.
On the basis of the above embodiment, as shown in fig. 12, the switch performance test includes a switch instantaneous jitter test, and the switch test result includes a switch instantaneous jitter test result.
Step 141, determining a first round trip time according to the sending time of the first information of the test message and the receiving time of the second information of the test message;
step 142, obtaining the fifth information of the test message, and forwarding and reflowing the fifth information of the test message according to a preset application specific integrated circuit to obtain the sixth information of the test message corresponding to the fifth information of the test message;
Step 143, determining a second round trip time according to the sending time of the fifth information of the test message and the receiving time of the sixth information of the test message;
and 144, generating the switch instantaneous jitter test result according to the time difference corresponding to the first round trip time and the second round trip time.
Specifically, the switch testing method provided by the application can test the instantaneous jitter of the switch. And after the second information of the test message is acquired, acquiring the first round trip time according to the transmission time of the first information of the test message and the second information of the test message. And then sending the fifth information of the test message to the ASIC through the FPGA, receiving the sixth information of the test message returned by the ASIC, and obtaining the second round trip time according to the sending time of the fifth information of the test message and the sixth information of the test message. And then, acquiring a time difference according to the first round trip time and the second round trip time, and determining a test result of the instantaneous jitter of the switch according to the time difference.
For example, when the FPGA continuously sends test messages to the ASIC at a fixed sending rate, the round trip time of each test message is obtained, the time difference between two adjacent messages is determined according to the round trip times, and 1, finally, the standard deviation is calculated according to the time differences, and is used as the instantaneous jitter parameter of the switch.
Because the rate of sending the test message to the ASIC by the FPGA is a fixed value, only the arrival time of the test message is required to be monitored, and the difference value of a plurality of round trip times is determined according to the difference value between a plurality of arrival times, thereby reducing the calculated amount of the time difference and improving the test efficiency of the switch.
On the basis of the embodiment, the switch test method can test the instantaneous jitter of the switch, and the switch test result carries the instantaneous jitter performance index of the switch, so that the application range of the switch test method is expanded, and the comprehensiveness of the switch test is ensured.
On the basis of the foregoing embodiment, as shown in fig. 13, in the switch testing method provided in the present application, after step 103, the method further includes:
step 104, comparing the switch test result with a preset RFC2544 standard to obtain a standard comparison result;
and 105, outputting and displaying the standard comparison result.
Specifically, in the switch test method provided by the application, after the FPGA calculates the switch test result according to the first information of the test message and the second information of the test message, the CPU reads the test result from the FPGA, compares the test result according to the preset RFC2544 standard to obtain a standard comparison result, and outputs and displays the test result and the standard comparison result containing various performance indexes for a user to evaluate the performance of the equipment.
On the basis of the embodiment, the switch test method provided by the application can also compare the switch test result with the preset RFC2544 standard and output and display the standard comparison result, so that the visibility of the switch test result is improved, and the user experience is improved.
On the basis of the above embodiment, as shown in fig. 14, the present application further provides a switch test example:
first, the FPGA sends test messages to the ASIC via ports of the communication bus 1, e.g. KR1, under the control of the CPU, where tx and rx in multiple ports in the ASIC have been pre-connected to form a loop. The ASIC sends the test message to Port1 (Port 1) through tx and to the first Eloop through tx, after which the Eloop sends the test message back to Port1 through rx and back to the ASIC through rx. The ASIC then continues to send the returned test message through tx to Port2 (Port 2) and through tx to the second elop, which then returns the test message through rx to Port2 and through rx to the ASIC. The ASIC then continues to send the returned test message through tx to Port3 (Port 3) and through tx to the third elop, which then returns the test message through rx to Port3 and through rx to the ASIC. And continuously transmitting and receiving until the ASIC continuously transmits the returned test message to a port x (Portx) through tx, transmitting the test message to an xth elop through tx, then, transmitting the test message to the Portx through rx by the elop, transmitting the test message to the ASIC through rx, and returning the test message to the FPGA through a communication bus 2, such as a port of KR2, by the ASIC, so that the FPGA can perform switch performance test according to the transmitted test message and the received test message. The duration of each test can be limited according to the requirements of a user, for example, the duration is controlled within 60 seconds, and the average value of the test results is obtained so as to ensure the accuracy of the test.
It should be emphasized that the value of x may be determined according to the user requirement or the requirement of the number of ports in the switch test requirement, which is not limited in this application.
A second embodiment of the present application relates to a switch testing apparatus, as shown in fig. 15, including:
a first test message obtaining module 201, configured to obtain first information of a test message;
a second test message obtaining module 202, configured to forward and reflux the first test message information according to a preset application specific integrated circuit to obtain second test message information corresponding to the first test message information, where a transmitting pin and a receiving pin of the application specific integrated circuit are connected;
and the test result generating module 203 is configured to perform a performance test on the switch according to the first information of the test message and the second information of the test message, so as to obtain a test result of the switch.
On the basis of the foregoing embodiment, in the switch testing device provided in the present application, the switch testing device is applied to a switch testing system, where the switch testing system includes an application specific integrated circuit and a field programmable gate array, and the first test packet acquisition module 201 includes:
And the field programmable gate array sending unit is used for sending the first information of the test message to the application-specific integrated circuit through the field programmable gate array.
Based on the above embodiment, in the switch testing device provided in the present application, the switch testing system further includes a central processing unit, the first information of the test message includes RFC2544 first standard frame information, and the field programmable gate array transmitting unit includes:
a standard frame length determining subunit, configured to determine, by the central processing unit, the RFC2544 first standard frame information from RFC2544 standard frames with different frame lengths;
and the standard frame transmitting subunit is used for transmitting the first standard frame information of the RFC2544 to the application-specific integrated circuit through the field programmable gate array.
Based on the foregoing embodiment, in the switch testing device provided in the present application, the application specific integrated circuit is connected to the electrical loop fixture, and the second test packet obtaining module 202 includes:
the pin sending unit is used for sending the first information of the test message to the electric loop jig through the sending pin;
and the pin receiving unit is used for receiving the second information of the test message returned by the electric loop jig through the receiving pin.
On the basis of the above-mentioned embodiment, in the switch testing device provided by the application, the sending pin includes the second sending pin, the receiving pin includes first receiving pin and second receiving pin, the electrical circuit tool includes first tool and second tool, the pin receiving unit includes:
an intermediate receiving subunit, configured to receive intermediate information of the test packet returned by the first jig through the first receiving pin;
the intermediate transmitting subunit is used for transmitting the intermediate information of the test message to the second jig through the second transmitting pin;
and the second receiving subunit is used for receiving the second information of the test message returned by the second jig through the second receiving pin.
On the basis of the above embodiment, the switch testing device provided in the present application further includes:
and the pre-connection processing module is used for connecting the transmitting pin and the receiving pin of the application-specific integrated circuit through the electric loop jig to obtain the application-specific integrated circuit with the flow looped.
On the basis of the foregoing embodiment, in the switch test device provided by the present application, the switch performance test includes a switch throughput test, the switch test result includes a switch throughput test result, and the test result generating module 203 includes:
The first packet sending quantity comparison unit is used for comparing the quantity of the sending and receiving packets of the first information of the test message and the second information of the test message to obtain a first sending and receiving packet quantity comparison result;
a third message obtaining unit, configured to obtain third information of a test message when the number of data packets corresponding to the first information of the test message is the same as the number of data packets corresponding to the second information of the test message as a result of comparing the number of the first transmit-receive packets, where a packet sending rate of the third information of the test message is greater than a packet sending rate of the first information of the test message;
a fourth message obtaining unit, configured to forward and reflux the third information of the test message according to a preset application specific integrated circuit, to obtain fourth information of the test message corresponding to the third information of the test message;
the second packet sending quantity comparison unit is used for comparing the number of the sending and receiving packets of the third information of the test message and the fourth information of the test message to obtain a second sending and receiving packet number comparison result;
and the throughput result generating unit is used for generating the throughput test result according to the packet sending rate of the third information of the test message when the second receiving and transmitting packet number comparison result is that the number of data packets corresponding to the third information of the test message is different from the number of data packets corresponding to the fourth information of the test message.
On the basis of the foregoing embodiment, in the switch test device provided by the present application, the switch performance test includes a switch delay test, the switch test result includes a switch delay test result, and the test result generating module 203 includes:
the round trip time calculation unit is used for obtaining the round trip time of the test message according to the sending time of the first information of the test message and the receiving time of the second information of the test message;
and the delay result generating unit is used for generating the switch delay test result according to the round trip time of the test message.
On the basis of the foregoing embodiment, in the switch test device provided by the present application, the switch performance test includes a switch packet loss rate test, the switch test result includes a switch packet loss rate test result, and the test result generating module 203 includes:
the packet loss rate calculation unit is used for determining the number of lost messages according to the number of messages of the first information of the test messages and the number of messages of the second information of the test messages;
and the packet loss result generating unit is used for generating the packet loss rate test result of the switch according to the message quantity of the second information of the test message and the lost message quantity.
On the basis of the foregoing embodiment, in the switch test device provided in the present application, the switch performance test includes a switch instantaneous jitter test, the switch test result includes a switch instantaneous jitter test result, and the test result generating module 203 includes:
the first time difference calculation unit is used for determining a first round trip time according to the sending time of the first information of the test message and the receiving time of the second information of the test message;
a fifth message obtaining unit, configured to obtain fifth information of a test message, and forward and reflux the fifth information of the test message according to a preset application specific integrated circuit, so as to obtain sixth information of the test message corresponding to the fifth information of the test message;
a second time difference calculation unit, configured to determine a second round trip time according to a sending time of the fifth information of the test packet and a receiving time of the sixth information of the test packet;
and the instantaneous jitter result generating unit is used for generating the switch instantaneous jitter test result according to the time difference corresponding to the first round trip time and the second round trip time.
On the basis of the above embodiment, the switch testing device provided in the present application further includes:
The standard comparison module is used for comparing the switch test result with a preset RFC2544 standard to obtain a standard comparison result;
and the output display module is used for outputting and displaying the standard comparison result.
A third embodiment of the present application relates to a switch testing system, comprising:
the field programmable gate array end is used for acquiring the first information of the test message, sending the first information of the test message to the application-specific integrated circuit end, receiving the second information of the test message sent by the application-specific integrated circuit end, and performing the performance test of the switch according to the first information of the test message and the second information of the test message to obtain a test result of the switch;
the application-specific integrated circuit end is used for receiving the first information of the test message sent by the field programmable gate array end, forwarding and reflowing the first information of the test message to obtain second information of the test message corresponding to the first information of the test message, and sending the second information of the test message to the field programmable gate array.
A fourth embodiment of the present application relates to an electronic device, as shown in fig. 16, including:
At least one processor 301;
and a memory 302 communicatively coupled to the at least one processor 301;
the memory 302 stores instructions executable by the at least one processor 301 to enable the at least one processor 301 to implement the switch testing method according to the first embodiment of the present application.
Where the memory and the processor are connected by a bus, the bus may comprise any number of interconnected buses and bridges, the buses connecting the various circuits of the one or more processors and the memory together. The bus may also connect various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, will not be described any further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver may be one element or may be a plurality of elements, such as a plurality of receivers and transmitters, providing a means for communicating with various other apparatus over a transmission medium. The data processed by the processor is transmitted over the wireless medium via the antenna, which further receives the data and transmits the data to the processor.
The processor is responsible for managing the bus and general processing and may also provide various functions including timing, peripheral interfaces, voltage regulation, power management, and other control functions. And memory may be used to store data used by the processor in performing operations.
A fifth embodiment of the present application relates to a non-transitory computer readable storage medium storing a computer program. The computer program, when executed by the processor, implements the switch testing method described in the first embodiment of the present application.
That is, it will be understood by those skilled in the art that all or part of the steps in implementing the methods of the embodiments described above may be implemented by a program stored in a storage medium, where the program includes several instructions for causing a device (which may be a single-chip microcomputer, a chip or the like) or a processor (processor) to perform all or part of the steps in the methods of the embodiments described herein. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-only memory (ROM), a random access memory (RAM, randomAccessMemory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It is to be understood that the present application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (15)
1. A method of testing a switch, the method comprising:
acquiring first information of a test message;
forwarding and reflowing the first information of the test message according to a preset application-specific integrated circuit to obtain second information of the test message corresponding to the first information of the test message, wherein a transmitting pin and a receiving pin of the application-specific integrated circuit are connected;
And performing switch performance test according to the first information of the test message and the second information of the test message to obtain a switch test result.
2. The method of claim 1, applied to a switch test system, the switch test system comprising the application specific integrated circuit and a field programmable gate array, the obtaining the first information of the test message comprising:
and sending the first information of the test message to the application specific integrated circuit through the field programmable gate array.
3. The method of claim 2, wherein the switch test system further comprises a central processor, wherein the test message first information comprises RFC2544 first standard frame information, and wherein the sending the test message first information to the application specific integrated circuit through the field programmable gate array comprises:
determining, by the central processor, the RFC2544 first standard frame information from a plurality of RFC2544 standard frames of different frame lengths;
and sending the RFC2544 first standard frame information to the application specific integrated circuit through the field programmable gate array.
4. The method of claim 1, wherein the application specific integrated circuit is connected to an electrical loop fixture, and the forwarding and reflowing the first information of the test message according to the preset application specific integrated circuit to obtain second information of the test message corresponding to the first information of the test message comprises:
Transmitting the first information of the test message to the electrical loop jig through the transmitting pin;
and receiving the second information of the test message returned by the electric loop jig through the receiving pin.
5. The method of claim 4, wherein the transmit pin comprises a second transmit pin, the receive pin comprises a first receive pin and a second receive pin, the electrical circuit fixture comprises a first fixture and a second fixture, and receiving the test message second information returned by the electrical circuit fixture through the receive pin comprises:
receiving the intermediate information of the test message returned by the first jig through the first receiving pin;
transmitting the intermediate information of the test message to the second jig through the second transmitting pin;
and receiving second information of the test message returned by the second jig through the second receiving pin.
6. The method of claim 4, wherein before the transmitting the first information of the test message to the electrical circuit fixture via the transmitting pin, further comprises:
and connecting the transmitting pin and the receiving pin of the application-specific integrated circuit through the electric loop jig to obtain the application-specific integrated circuit with the flow looped.
7. The method of claim 1, wherein the switch performance test comprises a switch throughput test, the switch test result comprises a switch throughput test result, and the performing the switch performance test according to the first information of the test message and the second information of the test message to obtain the switch test result comprises:
comparing the number of the receiving and transmitting packets of the first information of the test message with the number of the second information of the test message to obtain a comparison result of the number of the first receiving and transmitting packets;
when the comparison result of the first receiving and transmitting packet number is that the number of data packets corresponding to the first information of the test message is the same as the number of data packets corresponding to the second information of the test message, obtaining third information of the test message, wherein the packet sending rate of the third information of the test message is greater than that of the first information of the test message;
forwarding and reflowing the third information of the test message according to a preset application-specific integrated circuit to obtain fourth information of the test message corresponding to the third information of the test message;
carrying out receiving and transmitting packet number comparison on the third information of the test message and the fourth information of the test message to obtain a second receiving and transmitting packet number comparison result;
And when the comparison result of the second receiving and transmitting packet number is that the number of data packets corresponding to the third information of the test message is different from the number of data packets corresponding to the fourth information of the test message, generating the throughput test result according to the packet sending rate of the third information of the test message.
8. The method of claim 1, wherein the switch performance test comprises a switch latency test, the switch test result comprises a switch latency test result, and the performing the switch performance test according to the first information of the test message and the second information of the test message to obtain the switch test result comprises:
acquiring the round trip time of the test message according to the sending time of the first information of the test message and the receiving time of the second information of the test message;
and generating the switch time delay test result according to the round trip time of the test message.
9. The method of claim 1, wherein the switch performance test comprises a switch packet loss rate test, the switch test result comprises a switch packet loss rate test result, and the performing the switch performance test according to the first information of the test message and the second information of the test message to obtain the switch test result comprises:
Determining the number of lost messages according to the number of messages of the first information of the test messages and the number of messages of the second information of the test messages;
and generating the switch packet loss rate test result according to the message number of the second information of the test message and the lost message number.
10. The method of claim 1, wherein the switch performance test comprises a switch transient jitter test, the switch test result comprises a switch transient jitter test result, and the performing the switch performance test according to the first information of the test message and the second information of the test message to obtain the switch test result comprises:
determining a first round trip time according to the sending time of the first information of the test message and the receiving time of the second information of the test message;
obtaining fifth information of a test message, and forwarding and reflowing the fifth information of the test message according to a preset application-specific integrated circuit to obtain sixth information of the test message corresponding to the fifth information of the test message;
determining a second round trip time according to the sending time of the fifth information of the test message and the receiving time of the sixth information of the test message;
And generating the switch instantaneous jitter test result according to the time difference corresponding to the first round trip time and the second round trip time.
11. The method of claim 1, wherein the performing the switch performance test according to the first information of the test message and the second information of the test message, after obtaining the switch test result, further comprises:
comparing the switch test result with a preset RFC2544 standard to obtain a standard comparison result;
and outputting and displaying the standard comparison result.
12. A switch testing apparatus, comprising:
the first test message acquisition module is used for acquiring first information of the test message;
the second test message acquisition module is used for forwarding and reflowing the first test message information according to a preset application-specific integrated circuit to obtain second test message information corresponding to the first test message information, wherein a transmitting pin and a receiving pin of the application-specific integrated circuit are connected;
and the test result generation module is used for performing switch performance test according to the first information of the test message and the second information of the test message to obtain a switch test result.
13. A switch testing system, comprising:
the field programmable gate array end is used for acquiring the first information of the test message, sending the first information of the test message to the application-specific integrated circuit end, receiving the second information of the test message sent by the application-specific integrated circuit end, and performing the performance test of the switch according to the first information of the test message and the second information of the test message to obtain a test result of the switch;
the application-specific integrated circuit end is used for receiving the first information of the test message sent by the field programmable gate array end, forwarding and reflowing the first information of the test message to obtain second information of the test message corresponding to the first information of the test message, and sending the second information of the test message to the field programmable gate array.
14. An electronic device comprising a processor and a memory storing a program or instructions executable on the processor, which when executed by the processor, implement the steps of the switch testing method of any of claims 1-11.
15. A readable storage medium storing a computer program, which when executed by a processor implements the switch testing method according to any of claims 1-11.
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| CN202311595063.1A CN117319278A (en) | 2023-11-27 | 2023-11-27 | Switch testing method and device, electronic equipment and storage medium |
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