CN115766526A - Test method and device for switch physical layer chip and electronic equipment - Google Patents
Test method and device for switch physical layer chip and electronic equipment Download PDFInfo
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Abstract
The invention provides a method and a device for testing a physical layer chip of a switch and electronic equipment, wherein the method comprises the following steps: configuring each PHY port of a physical layer PHY chip to be in a loopback state through a management data clock MDC interface and a management data input/output MDIO interface; and obtaining a port test result of each PHY port by carrying out linear speed flow test on each PHY port, wherein the port test result is used for indicating whether the PHY port passes the test or not. According to the invention, each PHY port of the PHY chip can be configured to be in a loopback state through the MDC interface and the MDIO interface, so that linear speed flow test can be carried out on each PHY port, test case data sent to each PHY port of the PHY chip in the test process can be analyzed through loopback of the PHY chip, the port test result of each PHY port can be obtained, an external jig is not required in the test process, and the test efficiency can be improved.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a method and a device for testing a physical layer chip of a switch and electronic equipment.
Background
The Physical Layer (PHY) of the switch processes data of a Media Access Control (MAC) Layer, converts parallel data into serial data, codes the serial data according to the rules of the Physical Layer, and converts the serial data into analog signals to send the data out, and can realize a part of Carrier Sense Multiple Access/Collision Detection (CSMA/CD) functions with Collision Detection, which is an important component of the switch. With the development of network technology, the PHY chip is used on the switch in an increasingly large scale.
In the PHY port test technique in the related art, external jigs (e.g., optical module, eload, etc.) are mostly used, a transmit (tx) port and a receive (rx) port of each lane are connected through a blocking capacitor, and then a flow test is performed, so that the test efficiency is low.
Disclosure of Invention
Aiming at the problems in the prior art, the embodiment of the invention provides a method and a device for testing a switch physical layer chip and electronic equipment.
In a first aspect, the present invention provides a method for testing a physical layer chip of a switch, including: configuring each PHY port of a physical layer PHY chip to be in a loopback state through a management data clock MDC interface and a management data input/output MDIO interface;
and obtaining a port test result of each PHY port by carrying out linear speed flow test on each PHY port, wherein the port test result is used for indicating whether the PHY port passes the test or not.
Optionally, according to the method for testing a physical layer chip of a switch provided by the present invention, the obtaining a port test result of each PHY port by performing a line speed traffic test on each PHY port includes:
acquiring the connection state of each PHY port;
if the connection state of each PHY port is determined to be a connection establishment state, transmitting test case data to each PHY port through a transmission TX port of a Media Access Control (MAC) layer;
receiving loopback data of each PHY port through a receiving RX port of the MAC;
and acquiring a port test result of each PHY port based on the test case data, the loopback data of each PHY port and the connection state monitoring data of each PHY port.
Optionally, according to the method for testing a physical layer chip of an exchange provided by the present invention, the obtaining a port test result of each PHY port based on the test case data, the loopback data of each PHY port, and the connection state monitoring data of each PHY port includes:
determining the quantity difference information of the receiving and transmitting packets of each PHY port and the error packet information of each PHY port based on the test case data and the loopback data of each PHY port;
and judging whether each PHY port passes the test or not based on the connection state monitoring data, the quantity difference information of the receiving and sending packets and the error packet information of each PHY port, and acquiring the port test result of each PHY port.
Optionally, according to the testing method for a switch physical layer chip provided by the present invention, after the obtaining the port test result of each PHY port by performing the line speed traffic test on each PHY port, the method further includes:
determining a target fault keyword based on connection state monitoring data, transmitted/received packet quantity difference information and error packet information of a target PHY port under the condition that a port test result of the target PHY port indicates that the target PHY port fails in testing;
acquiring a target fault diagnosis instruction based on the target fault keyword and a fault table, wherein the fault table is used for representing a mapping relation between the fault keyword and the fault diagnosis instruction, and the fault diagnosis instruction is used for assisting in diagnosing the PHY port;
acquiring fault diagnosis information of the target PHY port by executing the target fault diagnosis instruction;
the target PHY port is any PHY port of the PHY chip.
Optionally, according to the method for testing a switch physical layer chip provided by the present invention, after the obtaining the fault diagnosis information of the target PHY port, the method further includes:
determining fault reporting information of the target PHY port based on the connection state monitoring data, the quantity difference information of the receiving and transmitting packets, the error packet information and the fault diagnosis information of the target PHY port;
and sending the fault report information of the target PHY port to a server.
Optionally, the method for testing a physical layer chip of a switch according to the present invention further includes:
polling a plurality of registers of the PHY chip through an MDC interface and an MDIO interface to acquire storage values of the plurality of registers, wherein the plurality of registers comprise an interrupt register, a control register and a status register;
and determining the operation state information of the PHY chip based on the reference value of each register and the storage value of each register, wherein the operation state information is used for representing whether the PHY chip has a fault.
Optionally, according to the method for testing a switch physical layer chip provided by the present invention, after the determining the operating state information of the PHY chip, the method further includes:
and under the condition that the running state information represents that the PHY chip has faults, configuring the storage value of each register as the reference value of each register.
In a second aspect, the present invention further provides a device for testing a physical layer chip of a switch, including:
the first configuration module is used for configuring each PHY port of the physical layer PHY chip into a loopback state through a Management Data Clock (MDC) interface and a management data input/output (MDIO) interface;
and the test module is used for obtaining a port test result of each PHY port by carrying out linear speed flow test on each PHY port, and the port test result is used for indicating whether the PHY port passes the test or not.
In a third aspect, the present invention further provides an electronic device, which includes a memory, a processor, and a computer program stored in the memory and executable on the processor, where the processor executes the computer program to implement the method for testing the switch physical layer chip according to any one of the above methods.
In a fourth aspect, the present invention also provides a non-transitory computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, implements a method for testing a switch physical layer chip as described in any one of the above.
According to the testing method, the testing device and the electronic equipment of the switch physical layer chip, provided by the invention, each PHY port of the PHY chip can be configured to be in a loopback state through the MDC interface and the MDIO interface, so that the linear speed flow test can be carried out on each PHY port, the test case data sent to each PHY port of the PHY chip in the testing process can be looped back through the PHY chip, so that the loopback data of each PHY port can be analyzed, the port testing result of each PHY port can be obtained, the port testing result can indicate whether the PHY port passes the test, an external jig is not needed in the testing process, and the testing efficiency can be improved.
Drawings
In order to more clearly illustrate the technical solutions of the present invention or the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and those skilled in the art can also obtain other drawings according to the drawings without creative efforts.
FIG. 1 is a schematic flow chart of a testing method of a switch physical layer chip provided by the present invention;
FIG. 2 is a schematic diagram of a hardware connection structure for a linear speed flow test provided by the present invention;
FIG. 3 is a schematic structural diagram of a testing apparatus for a switch physical layer chip provided in the present invention;
fig. 4 is a schematic structural diagram of an electronic device provided in the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 1 is a schematic flow chart of a testing method for a switch physical layer chip provided by the present invention, and as shown in fig. 1, an execution main body of the testing method for the switch physical layer chip may be an electronic device. The method comprises the following steps:
specifically, in order to improve the test efficiency, each PHY port of the PHY chip may be configured to be in a loopback state through a Management Data Clock (MDC) interface and a Management Data Input Output (MDIO) interface, and then the test case Data sent to each PHY port of the PHY chip may be looped back through the PHY chip.
It can be understood that, through the MDC interface and the MDIO interface, each port of the PHY chip can be configured as a Line internal loop, so that the traffic can be sent out from the MAC port tx, and then looped back through the PHY chip to the MAC port rx, thereby implementing the test without depending on an external fixture.
Specifically, after configuring each PHY port of the PHY chip to be in a loopback state, the PHY port may be subjected to a linear speed traffic test, test case data may be sent to each PHY port of the PHY chip during the test, the test case data is used to test each PHY port, the loopback data of each PHY port may be analyzed through loopback of the PHY chip, a port test result of each PHY port may be obtained, and the port test result may indicate whether the PHY port passes the test.
For example, the PHY chip may include 3 PHY ports, which are a port a, a port B, and a port C, and may configure the port a, the port B, and the port C to be in a loopback state through an MDC interface and an MDIO interface, and may send test case data to the port a, the port B, and the port C in the test process, and may analyze loopback data of the port a, the port B, and the port C through the PHY chip loopback, and may obtain a port test result of each PHY port.
According to the testing method of the switch physical layer chip, provided by the invention, each PHY port of the PHY chip can be configured to be in a loopback state through the MDC interface and the MDIO interface, so that the linear speed flow test can be carried out on each PHY port, the test case data sent to each PHY port of the PHY chip in the testing process can be looped back through the PHY chip, so that the loopback data of each PHY port can be analyzed, the port testing result of each PHY port can be obtained, the port testing result can indicate whether the PHY port passes the test, an external jig is not required in the testing process, and the testing efficiency can be improved.
Optionally, the present invention provides a method for testing a physical layer chip of a switch, where the method for obtaining a port test result of each PHY port by performing a line speed traffic test on each PHY port includes:
acquiring the connection state of each PHY port;
if the connection state of each PHY port is determined to be a connection establishment state, transmitting test case data to each PHY port through a transmission TX port of a Media Access Control (MAC) layer;
receiving loopback data of each PHY port through a receiving RX port of the MAC;
and acquiring a port test result of each PHY port based on the test case data, the loopback data of each PHY port and the connection state monitoring data of each PHY port.
Specifically, after configuring each PHY port of the PHY chip to be in a loopback state, a connection (Link) state of each PHY port may be obtained, and it is determined whether the connection state of each PHY port is in a connection establishment state (Link up), and if it is determined that the connection state of each PHY port is the connection establishment state, test case data may be transmitted to each PHY port through a TX transmitting port of the MAC, where the test case data is used to test each PHY port, and then the loopback data of each PHY port may be received through an RX receiving port of the MAC, and then based on the test case data, the loopback data of each PHY port, and the connection state monitoring data of each PHY port, the test condition of the PHY port may be analyzed, and a port test result of each PHY port may be obtained.
For example, the PHY chip may include two PHY ports, which are a port a and a port B, and may configure the port a and the port B to be in a loopback state through an MDC interface and an MDIO interface, and further may determine whether the port a and the port B are both in a Link up, and if it is determined that the port a and the port B are both in a Link up, send test case data to the port a and the port B through a TX port of the MAC, and further may receive the loopback data of the port a and the port B through an RX port of the MAC, and further may analyze test conditions of the port a and the port B based on the test case data, the loopback data of the port a and the port B, and connection state monitoring data of the port a and the port B, and obtain a port test result of each PHY port.
Optionally, fig. 2 is a schematic diagram of a hardware connection structure for a wire-speed traffic test provided by the present invention, and as shown in fig. 2, the PHY chip may be connected to a Central Processing Unit (CPU) through a KR bus of the CPU, and the PHY chip may include a Physical Media Attachment (PMA) Sublayer, a Physical Media Dependent (PMD) Sublayer, a Physical Coding Sublayer (PCS), a Serializer (Serializer), and a deserializer (De-Serializer). As shown in fig. 2, each PHY port of the PHY chip may be configured to be in a loopback state, and then a Lanconf tool may be combined to perform a line-speed packet transceiving test on each PHY port, and count the transceiving packet number and the error packet number of each port in real time.
Therefore, after configuring each PHY port of the PHY chip to be in a loopback state, the test case data is sent to each PHY port through the TX port of the MAC, and the loopback data of each PHY port is received through the RX port of the MAC, so that the automatic test of each PHY port can be realized, an external jig is not required in the test process, and the test efficiency can be improved.
Optionally, the present invention provides a method for testing a physical layer chip of a switch, where the obtaining of a port test result of each PHY port based on the test case data, the loopback data of each PHY port, and the connection state monitoring data of each PHY port includes:
determining the quantity difference information of the receiving and transmitting packets of each PHY port and the error packet information of each PHY port based on the test case data and the loopback data of each PHY port;
and judging whether each PHY port passes the test or not based on the connection state monitoring data, the quantity difference information of the receiving and transmitting packets and the error packet information of each PHY port, and acquiring the port test result of each PHY port.
Specifically, by comparing the packet number of the test case data with the packet number of the loopback data, the difference information of the number of the transmission and reception packets can be determined, error packet information can be obtained by checking the loopback data (for example, cyclic Redundancy Check (CRC)), and then whether each PHY port passes the test or not can be determined based on the connection state monitoring data of each PHY port, the difference information of the number of the transmission and reception packets, and the error packet information, and further the port test result of each PHY port can be obtained.
Alternatively, for a certain PHY port, if the connection status monitoring data indicates that the connection status of the PHY port changes to a connection-down status (Link down) during the test, it may be determined that the PHY port fails the test.
Optionally, for a certain PHY port, if the transmit-receive packet number difference information indicates that the packet number of the test case data is different from the packet number of the loopback data, it may be determined that the PHY port fails the test.
Optionally, for a certain PHY port, if the error packet information indicates that one or more data packets in the loopback data do not pass the check, it may be determined that the PHY port fails the test.
Alternatively, for a certain PHY port, it may be determined that the PHY port fails the test if the following three conditions are satisfied simultaneously:
the connection state monitoring data indicates that the connection states of the PHY port are connection establishment states in the test process;
the second condition is that the receiving and sending packet quantity difference information shows that the packet quantity of the test case data is the same as the packet quantity of the loopback data;
and under the third condition, the error packet information indicates that all data packets in the loopback data pass the inspection in the process of verifying the loopback data.
Therefore, whether each PHY port passes the test or not is judged based on the connection state monitoring data, the quantity difference information of the receiving and sending packets and the error packet information of each PHY port, so that the automatic test of each PHY port can be realized, an external jig is not required in the test process, and the test efficiency can be improved.
Optionally, the present invention provides a method for testing a physical layer chip of a switch, where after the line speed traffic test is performed on each PHY port to obtain a port test result of each PHY port, the method further includes:
determining a target fault keyword based on connection state monitoring data, transmitted/received packet quantity difference information and error packet information of a target PHY port under the condition that a port test result of the target PHY port indicates that the target PHY port fails in testing;
acquiring a target fault diagnosis instruction based on the target fault keyword and a fault table, wherein the fault table is used for representing a mapping relation between the fault keyword and the fault diagnosis instruction, and the fault diagnosis instruction is used for assisting in diagnosing the PHY port;
acquiring fault diagnosis information of the target PHY port by executing the target fault diagnosis instruction;
the target PHY port is any PHY port of the PHY chip.
Specifically, in order to obtain the failure cause of the PHY port, the port test result of each PHY port may be analyzed, and if the port test result of the target PHY port of the PHY chip indicates that the target PHY port fails to pass the test, the fault keyword may be extracted based on the connection state monitoring data, the difference information between the numbers of the transmitted and received packets, and the error packet information, so as to obtain a target fault keyword used for characterizing the failure condition of the target PHY port, and then, based on the target fault keyword, a fault table may be queried, so as to obtain a target fault diagnosis instruction matched with the target fault keyword, and then, the target fault diagnosis instruction may be executed, the target PHY port may be diagnosed, and the fault diagnosis information of the target PHY port may be obtained.
It can be understood that the fault table may represent a mapping relationship between the fault keyword and the fault diagnosis instruction, and based on the target fault keyword, the target fault diagnosis instruction matching the target fault keyword may be obtained by querying in the fault table. Keywords can be extracted aiming at various fault scenes of the PHY port by analyzing historical test data, fault keywords can be obtained, and the fault keywords can represent the fault scenes of the PHY port. For various fault scenes of the PHY port, various fault diagnosis instructions may be preconfigured, and one fault diagnosis instruction may perform fault diagnosis for one type of fault scenes to assist in diagnosing the PHY port.
For example, the connection status monitoring data indicates that the connection status of the target PHY port is changed from Link up to Link down during the test, and the target fault keyword may include "connection status exception", and further, based on the keyword, a fault table may be queried to obtain a target fault diagnosis instruction matching the keyword ("connection status exception").
For example, for the target PHY port, if the difference information of the number of send-receive packets indicates that the number of packets of the test case data is not the same as the number of packets of the loopback data, the target fault keyword may include "the number of send-receive packets is inconsistent", and then, based on the target fault keyword, the fault table may be queried, and a target fault diagnosis instruction matching the target keyword ("the number of send-receive packets is inconsistent") may be obtained.
For example, for the target PHY port, if the error packet information indicates that one or more data packets in the looped-back data fail to check, the target failure key may include "CRC error occurred", and then, based on the key, a query may be made in the failure table, and a target failure diagnosis instruction matching the key ("CRC error occurred") may be obtained.
For example, the target failure keyword may include "CRC error occurrence", the target failure diagnosis instruction matching the keyword may be to perform failure diagnosis for a CRC error scenario, the target failure diagnosis instruction may obtain an eye diagram, a bathtub curve, a CTLE parameter, and a Decision Feedback Equalizer (DFE) parameter for the target PHY port, and further may determine whether the eye diagram, the bathtub curve, a Continuous-time linear equalizer (CTLE) parameter, and the DFE parameter are within a preset range based on a preset range value, and may obtain failure diagnosis information of the target PHY port.
Therefore, under the condition that the PHY port fails to pass the test, the target fault diagnosis instruction can be obtained by inquiring the fault table, the fault diagnosis information can be obtained by operating the target fault diagnosis instruction, the fault of the PHY port can be automatically diagnosed, an external jig is not needed in the test process, and the test efficiency can be improved.
Optionally, the present invention provides a method for testing a switch physical layer chip, where after the obtaining of the fault diagnosis information of the target PHY port, the method further includes:
determining fault reporting information of the target PHY port based on the connection state monitoring data, the quantity difference information of the receiving and transmitting packets, the error packet information and the fault diagnosis information of the target PHY port;
and sending the fault report information of the target PHY port to a server.
Specifically, after the fault diagnosis information of the target PHY port is obtained, the information of the target PHY port may be collected, and the connection state monitoring data, the difference information of the number of transmit/receive packets, the error packet information, and the fault diagnosis information may be packaged into the fault report information, so that the fault report information of the target PHY port may be sent to the server.
Therefore, the fault reporting information of the PHY port is sent to the server, so that the server can collect and comprehensively analyze the fault information of each PHY chip.
Optionally, the present invention provides a method for testing a physical layer chip of a switch, further comprising:
polling a plurality of registers of the PHY chip through an MDC interface and an MDIO interface to acquire storage values of the plurality of registers, wherein the plurality of registers comprise an interrupt register, a control register and a status register;
and determining the operation state information of the PHY chip based on the reference value of each register and the storage value of each register, wherein the operation state information is used for representing whether the PHY chip has faults or not.
Specifically, in order to monitor the operating state of the PHY chip in real time, a plurality of registers of the PHY chip may be polled through the MDC interface and the MDIO interface to obtain stored values of the plurality of registers, and then the reference value of each register may be compared with the stored value of each register to determine the operating state information of the PHY chip.
It can be understood that, in the related art, detection of the PHY chip runtime state is generally detected by sending a code stream in a link idle stage, and the real-time performance is low. The invention polls a plurality of registers of the PHY chip through the MDC interface and the MDIO interface, and can realize real-time monitoring of the running state of the PHY chip.
For example, the stored value of the interrupt register (e.g., the servers interrupt register) may be compared to the reference value of the interrupt register, and if it is determined that the stored value of the interrupt register and the reference value of the interrupt register are not the same, it may be determined that the PHY chip is malfunctioning.
For example, the stored value of the control register may be compared with the reference value of the control register, and if it is determined that the stored value of the control register and the reference value of the control register are not the same, it may be determined that the PHY chip has failed.
For example, the stored value of the status register may be compared with the reference value of the status register, and if it is determined that the stored value of the status register is not the same as the reference value of the status register, it may be determined that the PHY chip has failed.
Therefore, the operating state of the PHY chip can be monitored in real time by polling the plurality of registers of the PHY chip through the MDC interface and the MDIO interface, an external jig is not needed in the testing process, and the testing efficiency can be improved.
Optionally, the present invention provides a method for testing a physical layer chip of a switch, where after the operating state information of the PHY chip is determined, the method further includes:
and under the condition that the running state information represents that the PHY chip has faults, configuring the storage value of each register as the reference value of each register.
Specifically, after the operating state information of the PHY chip is determined, whether the PHY chip has a fault may be determined, and if the PHY chip has a fault, the PHY chip may be reset by configuring the stored value of each register as the reference value of each register, so that the PHY chip may be restored to the normal operating state.
Optionally, a PHY chip debug tool running in the background of the switch may enable a thread, poll the PHY chip Serdes interrupt register, control register, or status register via the MDC interface and the MDIO interface, and automatically intervene to reconfigure the values of the rewrite registers if an exception occurs.
Therefore, when the PHY chip has a fault, the storage value of each register is configured as the reference value of each register, so that automatic intervention can be realized, the real-time performance is high, and the influence of the fault on the service is reduced.
According to the testing method of the switch physical layer chip, provided by the invention, each PHY port of the PHY chip can be configured to be in a loopback state through the MDC interface and the MDIO interface, so that the linear speed flow test can be carried out on each PHY port, the test case data sent to each PHY port of the PHY chip in the testing process can be looped back through the PHY chip, so that the loopback data of each PHY port can be analyzed, the port testing result of each PHY port can be obtained, the port testing result can indicate whether the PHY port passes the test, an external jig is not required in the testing process, and the testing efficiency can be improved.
The following is an alternative example of the present invention, but is not intended to limit the present invention.
The CPU 10GBASE-KR is used as a QSFP port through a PHY chip, configures the port as 4x10G, and records as port1, port2, port3, and port4, and executes an automated test at a high temperature (about 45 ℃), which may include the following steps 401 to 403:
step 401, configuring all the 4 ports of the PHY chip with internal loopback.
Step 402, detecting that the port can normally Link up after the loopback configuration, calling a Lanconf tool to perform transmit and receive (transmit and receive) test, and counting port counts in real time.
Optionally, in the test process, the real-time detection program running in the background finds, by polling, that the register value LIVELNKSTAT — 0 0x20028 is abnormal and is 0xFF0F, compares the value with the normal value, and writes the value back to 0xFF87.
Step 403, according to the statistical information in step 402, determining that Port1 has CRC error during the test process, the test program finds out the fault diagnosis instruction "TRAFFIC _ CRC" through the log (log) keyword "CRC error occurred in flow" (TRAFFIC CRC error), looking up the fault table, according to the fault diagnosis instruction, first, obtaining the Port1 eye diagram through the MDC interface and MDIO interface dump register (dump register refers to exporting and storing the data of the register into a file or static form), determining that the eye height is small, analyzing that the bathtub curve has large deterministic jitter, further analyzing the training parameters such as the Port CTLE or DFE, determining that the difference with the normal Port is large, further determining that the initial value of CTLE is unreasonable, and returning the result and the collected information to the server.
According to the invention, the PHY chip is provided with the internal loop, and the Lanconf tool is combined, so that the PHY port is automatically tested without depending on other tool fixtures, and the test program can automatically collect information and automatically analyze the reason of the test failure by checking the fault table. Compared with the traditional test method, the method can reduce the tooling cost, reduce the labor power and avoid the condition that the analysis environment is damaged without time. The PHY chip register is polled in real time through a background program, the running state of the PHY chip can be detected in real time, automatic intervention can be realized, a user has no sense, and normal service is not influenced.
The following describes the testing apparatus of the switch physical layer chip provided by the present invention, and the testing apparatus of the switch physical layer chip described below and the testing method of the switch physical layer chip described above can be referred to correspondingly.
Fig. 3 is a schematic structural diagram of a testing apparatus for a switch physical layer chip provided in the present invention, as shown in fig. 3, the apparatus includes: a first configuration module 301 and a test module 302, wherein:
a first configuration module 301, configured to configure each PHY port of the PHY chip of the physical layer to be in a loopback state through a management data clock MDC interface and a management data input/output MDIO interface;
the testing module 302 is configured to obtain a port testing result of each PHY port by performing a linear speed traffic test on each PHY port, where the port testing result is used to indicate whether the PHY port passes the test.
The testing device of the switch physical layer chip provided by the invention can configure each PHY port of the PHY chip to be in a loopback state through the MDC interface and the MDIO interface, so that the each PHY port can be subjected to linear speed flow test, test case data sent to each PHY port of the PHY chip in the testing process can be looped back through the PHY chip, so that loopback data of each PHY port can be analyzed, a port testing result of each PHY port can be obtained, the port testing result can indicate whether the PHY port passes the testing, an external jig is not required in the testing process, and the testing efficiency can be improved.
Optionally, the test module is specifically configured to:
acquiring the connection state of each PHY port;
if the connection state of each PHY port is determined to be a connection establishment state, transmitting test case data to each PHY port through a transmission TX port of a Media Access Control (MAC) layer;
receiving loopback data of each PHY port through a receiving RX port of the MAC;
and acquiring a port test result of each PHY port based on the test case data, the loopback data of each PHY port and the connection state monitoring data of each PHY port.
Optionally, the test module is specifically configured to:
determining the quantity difference information of the receiving and transmitting packets of each PHY port and the error packet information of each PHY port based on the test case data and the loopback data of each PHY port;
and judging whether each PHY port passes the test or not based on the connection state monitoring data, the quantity difference information of the receiving and transmitting packets and the error packet information of each PHY port, and acquiring the port test result of each PHY port.
Optionally, the apparatus further includes a fault diagnosis module, and after the port test result of each PHY port is obtained by performing the line speed traffic test on each PHY port, the fault diagnosis module is configured to:
determining a target fault keyword based on connection state monitoring data, transmitted/received packet quantity difference information and error packet information of a target PHY port under the condition that a port test result of the target PHY port indicates that the target PHY port fails in testing;
acquiring a target fault diagnosis instruction based on the target fault keyword and a fault table, wherein the fault table is used for representing a mapping relation between the fault keyword and the fault diagnosis instruction, and the fault diagnosis instruction is used for assisting in diagnosing the PHY port;
acquiring fault diagnosis information of the target PHY port by executing the target fault diagnosis instruction;
the target PHY port is any one PHY port of the PHY chip.
Optionally, the apparatus further includes a sending module, after the obtaining the fault diagnosis information of the target PHY port, the sending module is configured to:
determining fault reporting information of the target PHY port based on the connection state monitoring data, the quantity difference information of the receiving and transmitting packets, the error packet information and the fault diagnosis information of the target PHY port;
and sending the fault report information of the target PHY port to a server.
Optionally, the apparatus further includes an operating condition monitoring module, where the operating condition monitoring module is configured to:
polling a plurality of registers of the PHY chip through an MDC interface and an MDIO interface to acquire the storage values of the registers, wherein the registers comprise an interrupt register, a control register and a state register;
and determining the operation state information of the PHY chip based on the reference value of each register and the storage value of each register, wherein the operation state information is used for representing whether the PHY chip has faults or not.
Optionally, the apparatus further includes a second configuration module, and after the determining the operating state information of the PHY chip, the second configuration module is configured to:
and under the condition that the running state information represents that the PHY chip has faults, configuring the storage value of each register as the reference value of each register.
The testing device of the switch physical layer chip provided by the invention can configure each PHY port of the PHY chip to be in a loopback state through the MDC interface and the MDIO interface, so that the each PHY port can be subjected to linear speed flow test, test case data sent to each PHY port of the PHY chip in the testing process can be looped back through the PHY chip, so that loopback data of each PHY port can be analyzed, a port testing result of each PHY port can be obtained, the port testing result can indicate whether the PHY port passes the testing, an external jig is not required in the testing process, and the testing efficiency can be improved.
Fig. 4 is a schematic structural diagram of an electronic device provided in the present invention, and as shown in fig. 4, the electronic device may include: a processor (processor) 410, a communication Interface 420, a memory (memory) 430 and a communication bus 440, wherein the processor 410, the communication Interface 420 and the memory 430 are communicated with each other via the communication bus 440. The processor 410 may invoke logic instructions in the memory 430 to perform a method of testing a switch physical layer chip, for example, the method comprising:
configuring each PHY port of a physical layer PHY chip to be in a loopback state through a management data clock MDC interface and a management data input/output MDIO interface;
and obtaining a port test result of each PHY port by carrying out a linear speed flow test on each PHY port, wherein the port test result is used for indicating whether the PHY port passes the test or not.
In addition, the logic instructions in the memory 430 may be implemented in the form of software functional units and stored in a computer readable storage medium when the software functional units are sold or used as independent products. Based on such understanding, the technical solution of the present invention may be embodied in the form of a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In another aspect, the present invention also provides a computer program product, the computer program product includes a computer program, the computer program can be stored on a non-transitory computer readable storage medium, when the computer program is executed by a processor, a computer can execute the method for testing a switch physical layer chip provided by the above methods, for example, the method includes:
configuring each PHY port of a physical layer PHY chip to be in a loopback state through a management data clock MDC interface and a management data input/output MDIO interface;
and obtaining a port test result of each PHY port by carrying out a linear speed flow test on each PHY port, wherein the port test result is used for indicating whether the PHY port passes the test or not.
In yet another aspect, the present invention also provides a non-transitory computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method for testing a switch physical layer chip provided by the above methods, for example, the method comprising:
configuring each PHY port of a physical layer PHY chip to be in a loopback state through a management data clock MDC interface and a management data input/output MDIO interface;
and obtaining a port test result of each PHY port by carrying out a linear speed flow test on each PHY port, wherein the port test result is used for indicating whether the PHY port passes the test or not.
The above-described embodiments of the apparatus are merely illustrative, and the units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment. One of ordinary skill in the art can understand and implement it without inventive effort.
Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware. With this understanding in mind, the above-described technical solutions may be embodied in the form of a software product, which can be stored in a computer-readable storage medium such as ROM/RAM, magnetic disk, optical disk, etc., and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the methods described in the embodiments or some parts of the embodiments.
Finally, it should be noted that: the above examples are only intended to illustrate the technical solution of the present invention, and not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.
Claims (10)
1. A method for testing a switch physical layer chip is characterized by comprising the following steps:
configuring each PHY port of a physical layer PHY chip to be in a loopback state through a management data clock MDC interface and a management data input/output MDIO interface;
and obtaining a port test result of each PHY port by carrying out a linear speed flow test on each PHY port, wherein the port test result is used for indicating whether the PHY port passes the test or not.
2. The method for testing the switch physical layer chip according to claim 1, wherein the obtaining the port test result of each PHY port by performing a line speed traffic test on each PHY port comprises:
acquiring the connection state of each PHY port;
if the connection state of each PHY port is determined to be a connection establishment state, transmitting test case data to each PHY port through a transmission TX port of a Media Access Control (MAC) layer;
receiving loopback data of each PHY port through a receiving RX port of the MAC;
and acquiring a port test result of each PHY port based on the test case data, the loopback data of each PHY port and the connection state monitoring data of each PHY port.
3. The method for testing the switch physical layer chip according to claim 2, wherein the obtaining the port test result of each PHY port based on the test case data, the loopback data of each PHY port, and the connection state monitoring data of each PHY port comprises:
determining the quantity difference information of the receiving and transmitting packets of each PHY port and the error packet information of each PHY port based on the test case data and the loopback data of each PHY port;
and judging whether each PHY port passes the test or not based on the connection state monitoring data, the quantity difference information of the receiving and transmitting packets and the error packet information of each PHY port, and acquiring the port test result of each PHY port.
4. The method for testing the switch physical layer chip according to any one of claims 1 to 3, wherein after the obtaining the port test result of each PHY port by performing the wire speed traffic test on each PHY port, the method further comprises:
determining a target fault keyword based on connection state monitoring data, transmitted/received packet quantity difference information and error packet information of a target PHY port under the condition that a port test result of the target PHY port indicates that the target PHY port fails in testing;
acquiring a target fault diagnosis instruction based on the target fault keyword and a fault table, wherein the fault table is used for representing a mapping relation between the fault keyword and the fault diagnosis instruction, and the fault diagnosis instruction is used for assisting in diagnosing the PHY port;
acquiring fault diagnosis information of the target PHY port by executing the target fault diagnosis instruction;
the target PHY port is any PHY port of the PHY chip.
5. The method for testing the switch physical layer chip according to claim 4, further comprising, after the obtaining the failure diagnosis information of the target PHY port:
determining fault reporting information of the target PHY port based on the connection state monitoring data, the quantity difference information of the receiving and transmitting packets, the error packet information and the fault diagnosis information of the target PHY port;
and sending the fault report information of the target PHY port to a server.
6. The method for testing the switch physical layer chip according to any one of claims 1 to 3, further comprising:
polling a plurality of registers of the PHY chip through an MDC interface and an MDIO interface to acquire the storage values of the registers, wherein the registers comprise an interrupt register, a control register and a state register;
and determining the operation state information of the PHY chip based on the reference value of each register and the storage value of each register, wherein the operation state information is used for representing whether the PHY chip has a fault.
7. The method for testing the switch physical layer chip according to claim 6, further comprising, after the determining the operating status information of the PHY chip:
and under the condition that the running state information represents that the PHY chip has faults, configuring the storage value of each register as the reference value of each register.
8. A testing device for a switch physical layer chip is characterized by comprising:
the first configuration module is used for configuring each PHY port of the physical layer PHY chip into a loopback state through a Management Data Clock (MDC) interface and a management data input/output (MDIO) interface;
and the test module is used for obtaining a port test result of each PHY port by carrying out linear speed flow test on each PHY port, and the port test result is used for indicating whether the PHY port passes the test or not.
9. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor implements a method of testing the switch physical layer chip according to any one of claims 1 to 7 when executing the program.
10. A non-transitory computer readable storage medium, on which a computer program is stored, wherein the computer program, when executed by a processor, implements a method for testing a switch physical layer chip according to any one of claims 1 to 7.
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