CN117318715A - Resistor voltage division type digital-to-analog converter - Google Patents
Resistor voltage division type digital-to-analog converter Download PDFInfo
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- CN117318715A CN117318715A CN202311259105.4A CN202311259105A CN117318715A CN 117318715 A CN117318715 A CN 117318715A CN 202311259105 A CN202311259105 A CN 202311259105A CN 117318715 A CN117318715 A CN 117318715A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
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- H03M1/66—Digital/analogue converters
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Abstract
The invention provides a resistor voltage division type digital-to-analog converter, which comprises: the first stage circuit is used for segmenting the input reference voltage according to an external high-order signal and selecting one segment; and the second stage circuit is used for carrying out secondary segmentation on the first stage voltage selected by the first stage circuit according to the external low-order signal, and selecting a section of output after the secondary segmentation. The first stage circuit comprises 2 M First resistors and 2 1/2 resistors which are connected in series between the reference power sources Vref and gnd and have the same resistance value M A path data selector outputting a reference voltage 1 and a reference voltage 2; the second stage circuit comprises 2 N A second resistor and 1/2 of the resistors which are connected in series between the reference voltage 1 and the reference voltage 2 and have the same resistance value N And a way data selector. The invention can greatly reduce the number of required resistors and layout area, and can easily improve the output precision.
Description
Technical Field
The invention belongs to the circuit technology, and particularly relates to a resistor voltage division type digital-to-analog converter.
Background
A DAC is an abbreviation of Digital-to-Analog Converter (DAC), which is an electronic device for converting a Digital signal into an Analog signal. The functionality of a DAC is very important in many fields, such as audio signal processing, video display, communication systems, etc. The DAC functions to convert digital signals to analog signals so that the digital device can connect and communicate with the analog device. The method realizes interconnection between a digital system and an analog system by converting discrete digital data into continuous analog signals.
DACs are typically composed of digital and analog circuits. The digital circuit is responsible for converting an input digital signal into binary data and passing it to the analog circuit. The analog circuit generates a corresponding analog signal based on the binary data. The output of the DAC may be a voltage, current, or resistance change to meet the needs of different application areas.
In the prior art, the DAC constructed in a resistor series connection mode has nonlinear errors, the output precision is not ideal enough, and when the multi-bit DAC is realized, the number of resistors is large, the occupied area is large, and the requirements of high integration and miniaturization cannot be met.
Disclosure of Invention
In order to solve the defects of the related prior art, the invention provides the resistor voltage division type digital-to-analog converter, which greatly reduces the number of required resistors and the layout area and can easily improve the output precision.
In order to achieve the object of the invention, the following scheme is adopted:
a resistive voltage division digital to analog converter comprising:
the first stage circuit is used for segmenting the input reference voltage according to an external high-order signal and selecting one segment;
and the second stage circuit is used for carrying out secondary segmentation on the first stage voltage selected by the first stage circuit according to the external low-order signal, and selecting a section of output after the secondary segmentation.
Further, the first stage circuit includes 2 M First resistors and 2 1/2 resistors which are connected in series between the reference power sources Vref and gnd and have the same resistance value M A way data selector, wherein M is a positive integer greater than 2, gnd is denoted as node NET (0), and reference power Vref is denoted as node NET (2 M ) From gnd to the reference power Vref, the nodes between two adjacent first resistors are sequentially denoted as node NET (1), …, node NET (2 M -1), one 1/2 M 2 of way data selector M The input data pins are sequentially connected with a node NET (0), a node NET (1), a node NET (…) and a node NET (2) M -1) selecting one output according to the external high-order signal and taking the output as a reference voltage 1, and the other 1/2 M 2 of way data selector M The input data pins are sequentially connected with the nodes NET (1), …, the nodes NET (2 M -1), node NET (2 M ) And selecting one path output by sharing the external high-order signal as a reference voltage 2, wherein the reference voltage 1 and the reference voltage 2 are connected to a second-stage circuit.
Further, the second stage circuit includes 2 N A second resistor and 1/2 of the resistors which are connected in series between the reference voltage 1 and the reference voltage 2 and have the same resistance value N A path data selector, wherein n=m-1, the reference voltage 2 is denoted as node net (0), and two adjacent paths are arranged from the reference voltage 2 to the reference voltage 1The nodes between the second resistors are sequentially denoted as nodes net (1), …, nodes net (2 N -1)，1/2 N 2 of way data selector N The input data pins are sequentially connected with a node net (0), a node net (1), a node … and a node net (2) N -1) for selecting one of the outputs based on an external low signal.
Further, 1/2 M The way data selector comprises 2 M -1 high-order two-out-of-one data selector, 1/2 M 2 of way data selector M Of the input data pins, two adjacent input data pins are a group of 2 M-1 A group; along the direction from signal input to signal output, 2 M The 1 high-order one-out-of-two data selector is divided into M stages, the M-th stage comprising 2 M-m The high-order two-out-of-one data selectors, m=1, …, M, belong to the same level high-order two-out-of-one data selectors share one external high-order signal; two input data pins of each group are connected with the input of a 1 st-level high-order two-out-of-one data selector; when N is greater than 1, the output of the adjacent 2 m-th high-order two-out-of-one data selector is connected with the input of the next 1 high-order two-out-of-one data selector.
Further, 1/2 N The way data selector comprises 2 N -1 low order one-out-of-two data selector, 1/2 N 2 of way data selector N Of the input data pins, two adjacent input data pins are a group of 2 N-1 A group; along the direction from signal input to signal output, 2 N The 1 low-order one-out-of-two data selector is divided into N stages, the nth stage comprising 2 N-n A low-order two-out-of-one data selector, n=1, …, N, the low-order two-out-of-one data selectors belonging to the same level share an external low-order signal; two input data pins of each group are connected with the input of a low-order two-out-of-one data selector of the 1 st level; when N is greater than 1, the output of the adjacent 2N-th low-order two-out-of-one data selector is connected with the input of the next 1 low-order two-out-of-one data selector.
The invention has the beneficial effects that:
1. compared with the resistor string type DAC in the prior art, the resistor string type DAC has higher precision, each section can provide higher precision, higher overall precision is realized, nonlinear errors and temperature drift can be reduced, and accurate output is provided;
2. compared with the resistor string type DAC in the prior art, the number of resistors is greatly reduced: taking resistor strings into account to realize a 9-bit DAC needs 2 9 A resistance of only 2 5 +2 4 The number of resistors is greatly reduced, and the layout area is further reduced.
Drawings
Fig. 1 shows a block diagram of an embodiment of the present application and signal paths.
Fig. 2 shows an internal block diagram of an embodiment of the present application.
Fig. 3 shows a two-stage circuit connection relationship diagram of an embodiment of the present application.
Fig. 4 shows the 1/32 way data selector internal structure of an embodiment of the present application.
Fig. 5 shows the internal structure of the 1/16-way data selector according to the embodiment of the present application.
Fig. 6 shows a schematic diagram of the working principle of an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the following detailed description of the embodiments of the present invention will be given with reference to the accompanying drawings, but the described embodiments of the present invention are some, but not all embodiments of the present invention.
The embodiment of the application provides a resistor voltage division type digital-to-analog converter, which is shown in fig. 1 and comprises a first-stage circuit and a second-stage circuit.
The first stage circuit segments the input reference voltage according to an external high-order signal, and selects one segment to output to the second stage circuit; the second stage circuit performs secondary segmentation on the first stage circuit selected section of voltage according to the external low-order signal, and selects a section of voltage for output after the secondary segmentation.
Specifically, as shown in FIGS. 2-3, the first stage circuit includes 2 M First resistors and 2 1/2 resistors which are connected in series between the reference power sources Vref and gnd and have the same resistance value M Way data selector, wherein M is greater than 2A positive integer. The second stage circuit comprises 2 N A second resistor and 1/2 of the resistors which are connected in series between the reference voltage 1 and the reference voltage 2 and have the same resistance value N And a way data selector, wherein n=m-1.
In this example, the case where M is taken as 5 is exemplified, and in other cases where M is greater than 2, the same principle can be used for the analogization.
When m=5, the first stage circuit includes 32 first resistors and 2 1/32 data selectors, which are sequentially connected in series between the reference power Vref and gnd and have the same resistance value, and gnd is denoted as a node NET (0); the reference power Vref is denoted as node NET (2 M ) I.e. node NET (32); from gnd to the reference power Vref, the node between two adjacent first resistors is sequentially denoted as node NET (1), …, and node NET (31). The above-mentioned node NET (0), node NET (1), …, node NET (31), and node NET (32) correspond to NET0, NET1, … NET31, NET32, respectively, in fig. 3.
The 32 input data pins W0-W31 of the upper 1/32-way data selector are sequentially connected with a node NET (0), a node NET (1), … and a node NET (31), one-way output is selected according to an external high-order signal and is used as a reference voltage 1, the 32 input data pins W0-W31 of the lower 1/32-way data selector are sequentially connected with the node NET (1), … and the node NET (31), the node NET (32) and the external high-order signal is shared with the upper 1/32-way data selector to select one-way output and is used as a reference voltage 2, and the reference voltage 1 and the reference voltage 2 are connected to the second-stage circuit.
When m=5, n=4, the second stage circuit includes 16 second resistors and 1 16 data selectors, the second resistors are sequentially connected in series between the reference voltage 1 and the reference voltage 2 and have the same resistance value, the reference voltage 2 is denoted as a node net (0), nodes between two adjacent second resistors are sequentially denoted as nodes net (1), …, the node net (15), and 16 input data pins w 0-w 15 of the 16 data selectors are sequentially connected with the node net (0), the nodes net (1), … and the node net (15) for selecting one path of output according to an external low-order signal.
Specifically, as shown in fig. 4, the 32-way data selector includes 31 high-order two-way data selectors, and the 32-way data selectorAmong the 32 input data pins W0-W31 of the selector, two adjacent input data pins are in one group, for example, W0 and W1 are in one group, W2 and W3 are in one group, … …, and 16 groups are all provided. In the direction from the signal input to the signal output, the 16 high-order one-out-of-two data selectors are divided into 5 stages, each stage corresponding to one column in FIG. 4, the mth stage including 2 5-m The two high-order two-way data selectors, m=1, …,5, are sequentially 16, 8, 4, 2 and 1 along the direction of signal input to output, and belong to the same level/same column, share one external high-order signal, and are connected with 5 high-order control signals in total, such as D [8:4 ]]D8]、D[7]、D[6]、D[5]、D[5]Each bit controls all the high-order one-out-of-two data selectors of one stage, respectively, as shown in fig. 3 and 4.
Referring to fig. 4, wherein two input data pin connections of each group are connected to the input of a high-order one-out-of-two data selector of level 1; the output of the adjacent 2 m-th high-order two-out-of-one data selector is connected with the input of the next 1 high-order two-out-of-one data selector, and is connected step by step and backward, and the last high-order two-out-of-one data selector outputs the reference voltage 1 and/or the reference voltage 2. Specifically in the example of fig. 4, W0 and W1 are connected to the input of the high-order one-out-of-two data selector MUX1, W2 and W3 are connected to the input of the high-order one-out-of-two data selector MUX2, W4 and W5 are connected to the input of the high-order one-out-of-two data selector MUX3, … …, W30 and W31 are connected to the input of the high-order one-out-of-two data selector MUX 16; the high-order one-out data selectors MUX 1-MUX 16 are at stage 1. The high-order one-out-of-two data selectors MUX1 and MUX2 are connected to the input of the high-order one-out-of-two data selector MUX17, the high-order one-out-of-two data selectors MUX3 and MUX4 are connected to the input of the high-order one-out-of-two data selector MUX18, … …, and the high-order one-out-of-two data selectors MUX15 and MUX16 are connected to the input of the high-order one-out-of-two data selector MUX24, where the high-order one-out-of-two data selectors MUX 17-MUX 24 are at stage 2. The high-order one-out-of-two data selectors MUX17 and MUX18 are connected to the input of the high-order one-out-of-two data selector MUX25, the high-order one-out-of-two data selectors MUX19 and MUX20 are connected to the input of the high-order one-out-of-two data selector MUX26, … …, and the high-order one-out-of-two data selectors MUX23 and MUX24 are connected to the input of the high-order one-out-of-two data selector MUX28, where the high-order one-out-of-two data selectors MUX 25-MUX 28 are at stage 3. The high-order one-out-of-two data selectors MUX25 and MUX26 are connected to the input of the high-order one-out-of-two data selector MUX29, and the high-order one-out-of-two data selectors MUX27 and MUX28 are connected to the input of the high-order one-out-of-two data selector MUX30, where the high-order one-out-of-two data selectors MUX29 and MUX30 are at stage 4. The high-order one-out-of-two data selector MUX29 and MUX30 are connected to the input of the high-order one-out-of-two data selector MUX31, where the high-order one-out-of-two data selector MUX31 is at stage 5 and the output of the last stage is either reference voltage 1 or reference voltage 2.
Specifically, as shown in fig. 5, the 16-way data selector includes 15 low-order one-out-of-two data selectors, and among 16 input data pins w0 to w15 of the 16-way data selector, two adjacent input data pins are in a group, for example, w0 and w1 are in a group, w2 and w3 are in a group, … …, and 8 groups are all included. Along the direction from signal input to output, the 15 low-order alternative data selectors are divided into 4 stages, each stage is correspondingly a column, and the nth stage comprises 2 4-n The number of the low-order two-out-of-one data selectors is 8, 4, 2 and 1 in sequence, and the low-order two-out-of-one data selectors belonging to the same level/same column share one external low-order signal, and are totally connected with 4 low-order control signals, such as D [3:0 ]]D3 is]、D[2]、D[1]、D[0]Each bit controls all the low order one-out-of-two data selectors of one stage, respectively, as shown in fig. 3 and 5.
Referring to fig. 5, two input data pins of each group are connected to the input of a low-order one-out-of-two data selector of level 1; the output of the adjacent 2 n-th low-order two-way data selector is connected with the input of the next 1 low-order two-way data selector, and is connected step by step and backward, and the last low-order two-way data selector outputs a final voltage signal value. Specifically, in the example shown in fig. 5, the connection relationship principle is derived in a similar manner to that of the 32-way data selector, and will not be described herein.
The working principle is shown in fig. 6, the first stage circuit controls two 1/32 paths of data selectors through the high 5 bits of an external control signal to determine the interval where the output voltage is located, and transmits the end point value of the interval to the second stage circuit. The resistor string of the second stage circuit is divided and then passes through a 1/16 path data selector, and the output voltage value is determined by the low 4 bits of an external control signal.
The foregoing description of the preferred embodiments of the invention is merely exemplary and is not intended to be exhaustive or limiting of the invention. It will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention.
Claims (6)
1. A resistor divider digital-to-analog converter, comprising:
the first stage circuit is used for segmenting the input reference voltage according to an external high-order signal and selecting one segment;
and the second stage circuit is used for carrying out secondary segmentation on the first stage voltage selected by the first stage circuit according to the external low-order signal, and selecting a section of output after the secondary segmentation.
2. The resistive voltage-dividing digital-to-analog converter of claim 1, wherein the first stage circuit comprises 2 M First resistors and 2 1/2 resistors which are connected in series between the reference power sources Vref and gnd and have the same resistance value M A way data selector, wherein M is a positive integer greater than 2, gnd is denoted as node NET (0), and reference power Vref is denoted as node NET (2 M ) From gnd to the reference power Vref, the nodes between two adjacent first resistors are sequentially denoted as node NET (1), …, node NET (2 M -1), one 1/2 M 2 of way data selector M The input data pins are sequentially connected with a node NET (0), a node NET (1), a node NET (…) and a node NET (2) M -1) selecting one output according to the external high-order signal and taking the output as a reference voltage 1, and the other 1/2 M 2 of way data selector M The input data pins are sequentially connected with the nodes NET (1), …, the nodes NET (2 M -1), node NET (2 M ) The external high-order signal is shared to select one path output and is used as a reference voltage 2, and the reference voltage 1 and the reference voltage 2 are connected to the second-stage electric circuitAnd (5) a road.
3. The resistive voltage-dividing digital-to-analog converter of claim 2, wherein the second stage circuit comprises 2 N A second resistor and 1/2 of the resistors which are connected in series between the reference voltage 1 and the reference voltage 2 and have the same resistance value N A path data selector, wherein n=m-1, the reference voltage 2 is denoted as node net (0), and the nodes between two adjacent second resistors are sequentially denoted as node net (1), …, node net (2 N -1)，1/2 N 2 of way data selector N The input data pins are sequentially connected with a node net (0), a node net (1), a node … and a node net (2) N -1) for selecting one of the outputs based on an external low signal.
4. A resistive voltage-dividing digital-to-analog converter according to claim 3, characterized by 1/2 M The way data selector comprises 2 M -1 high-order two-out-of-one data selector, 1/2 M 2 of way data selector M Of the input data pins, two adjacent input data pins are a group of 2 M-1 A group;
along the direction from signal input to signal output, 2 M The 1 high-order one-out-of-two data selector is divided into M stages, the M-th stage comprising 2 M-m The high-order two-out-of-one data selectors, m=1, …, M, belong to the same level high-order two-out-of-one data selectors share one external high-order signal;
two input data pins of each group are connected with the input of a 1 st-level high-order two-out-of-one data selector; when N is greater than 1, the output of the adjacent 2 m-th high-order two-out-of-one data selector is connected with the input of the next 1 high-order two-out-of-one data selector.
5. A resistive voltage-dividing digital-to-analog converter according to claim 3, characterized by 1/2 N The way data selector comprises 2 N -1 low order one-out-of-two data selector, 1/2 N 2 of way data selector N Of the input data pins, two adjacent input data pinsIs a group of 2 N-1 A group;
along the direction from signal input to signal output, 2 N The 1 low-order one-out-of-two data selector is divided into N stages, the nth stage comprising 2 N-n A low-order two-out-of-one data selector, n=1, …, N, the low-order two-out-of-one data selectors belonging to the same level share an external low-order signal;
two input data pins of each group are connected with the input of a low-order two-out-of-one data selector of the 1 st level; when N is greater than 1, the output of the adjacent 2N-th low-order two-out-of-one data selector is connected with the input of the next 1 low-order two-out-of-one data selector.
6. The resistor divider digital-to-analog converter of claim 4, wherein m= 5,N =4, the first stage circuit comprises 32 first resistors and 2 1/32 data selectors, and the second stage circuit comprises 16 second resistors and 1/16 data selectors.
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| CN202311259105.4A CN117318715A (en) | 2023-09-27 | 2023-09-27 | Resistor voltage division type digital-to-analog converter |
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| CN202311259105.4A CN117318715A (en) | 2023-09-27 | 2023-09-27 | Resistor voltage division type digital-to-analog converter |
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