CN117313883A - Quantum circuit processing method and device and electronic equipment - Google Patents

Abstract

The disclosure provides a quantum circuit processing method, a quantum circuit processing device and electronic equipment, relates to the technical field of quantum computing, and particularly relates to the technical field of quantum circuits. The specific implementation scheme is as follows: acquiring a first instruction list of a first quantum circuit comprising N quantum bits, wherein the first quantum circuit is a quantum circuit with a star structure or a sub-circuit of the quantum circuit with the star structure, and in the star structure, a double-quantum bit gate acts between each first quantum bit and a target quantum bit according to the sequence of the quantum bits from small to large; based on the first instruction list, performing equivalent compiling on the first quantum circuit to obtain a second instruction list of the second quantum circuit; equivalent compilation includes: adding a first reset operation instruction after the first measurement operation instruction in the first instruction list; each target operating instruction in the first instruction list is remapped to the qubit of the qubit i, and the target operating instruction acts on the qubit i+1.

Description

Quantum circuit processing methods, devices and electronic equipment

Technical field

The present disclosure relates to the field of quantum computing technology, in particular to the field of quantum circuit technology, and specifically to a quantum circuit processing method, device and electronic equipment.

Background technique

Quantum computing uses the unique operating laws of the quantum world to provide a new and very promising way of processing information. Quantum algorithms can bring advantages over classical algorithms on many specific problems. For example, the Shor algorithm can be used to efficiently decompose large integers, and the Grover algorithm can be used to search for data faster. With the development of quantum theory, new quantum algorithms are constantly being proposed. How to efficiently simulate these algorithms or run them on real quantum hardware is always an important issue.

Classical simulation or real machine operation of quantum algorithms is mainly limited by the number of qubits. In classical simulations, since the length of the column vector describing the quantum state grows exponentially with the number of corresponding bits (for example, the column vector length of an n-bit quantum state is 2 ⁿ ), it is difficult for classical computers to simulate large-scale quantum algorithms. Limited by computer memory and processor capabilities, existing quantum circuit simulation methods can support algorithms that simulate dozens of qubits at most.

At present, heuristic algorithms are usually used to perform equivalent compilation of quantum circuits to obtain dynamic quantum circuits that are equivalent to quantum circuits.

Contents of the invention

The present disclosure provides a quantum circuit processing method, device and electronic equipment.

According to a first aspect of the present disclosure, a quantum circuit processing method is provided, including:

Obtaining a first instruction list of a first quantum circuit including N qubits, the first quantum circuit being: a star-structured quantum circuit or a sub-circuit of a star-structured quantum circuit, the star-structured quantum circuit The N qubits in the qubit are arranged in order from the qubit of qubit 0 to the qubit of qubit N-1. In the star structure, each first qubit and the qubit are arranged in order from small to large. A two-qubit gate acts between target qubits, the target qubit is any qubit among the N qubits, and the first qubit is any of the N qubits except the target qubit. Other qubits, the sub-circuit is a quantum circuit obtained by deleting some operation instructions from the instruction list of a star-structured quantum circuit, and N is an integer greater than 2;

Based on the first instruction list, perform equivalent compilation on the first quantum circuit to obtain a second instruction list of the second quantum circuit equivalent to the first quantum circuit;

Wherein, the number of qubits of the second quantum circuit is less than the number of qubits of the first quantum circuit, and the equivalent compilation includes: adding a first reset after the first measurement operation instruction in the first instruction list Operation instructions; and remap each target operation instruction in the first instruction list to the qubit of qubit i, and the first measurement operation instruction and the first reset operation instruction both act on qubit i On, the target operation instruction acts on qubit i+1, and the value range of i is [0, N-3].

According to a second aspect of the present disclosure, a quantum circuit processing device is provided, including:

An acquisition module, configured to acquire a first instruction list of a first quantum circuit including N qubits, where the first quantum circuit is: a star-structured quantum circuit or a sub-circuit of a star-structured quantum circuit, where the star The N qubits in the quantum circuit of the star-shaped structure are arranged in an orderly manner from the qubits of qubit 0 to the qubits of qubit N-1. In the star-shaped structure, each qubit is arranged in order from small to large. A two-qubit gate operates between the first qubit and the target qubit. The target qubit is any qubit among the N qubits. The first qubit is any one of the N qubits. For other qubits of the target qubit, the sub-circuit is a quantum circuit obtained by deleting some operation instructions from the instruction list of the star-structured quantum circuit, and N is an integer greater than 2;

An equivalent compilation module, configured to perform equivalent compilation on the first quantum circuit based on the first instruction list to obtain a second instruction list of the second quantum circuit equivalent to the first quantum circuit;

Wherein, the number of qubits of the second quantum circuit is less than the number of qubits of the first quantum circuit, and the equivalent compilation includes: adding a first reset after the first measurement operation instruction in the first instruction list Operation instructions; and remap each target operation instruction in the first instruction list to the qubit of qubit i, and the first measurement operation instruction and the first reset operation instruction both act on qubit i On, the target operation instruction acts on qubit i+1, and the value range of i is [0, N-3].

According to a third aspect of the present disclosure, an electronic device is provided, including:

at least one processor; and

A memory communicatively connected to at least one processor; wherein,

The memory stores instructions executable by at least one processor, and the instructions are executed by at least one processor, so that at least one processor can perform any method in the first aspect.

According to a fourth aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform any one of the methods of the first aspect.

According to a fifth aspect of the present disclosure, a computer program product is provided, including a computer program that implements any method in the first aspect when executed by a processor.

The technology according to the present disclosure solves the problem in the related art that the classical simulation and real machine operation of the star-structured quantum circuit and the sub-circuit of the star-structured quantum circuit are difficult, and can realize the star-structured quantum circuit, as well as the star-shaped quantum circuit. The optimal compilation of the sub-circuits of the structured quantum circuit enables the width of the compiled quantum circuit to be minimized, that is, a star-structured quantum circuit or the sub-circuit of a star-structured quantum circuit can be compiled into its equivalent A dynamic quantum circuit with the minimum number of qubits required can simplify the classical simulation and real-machine operation of star-structured quantum circuits and sub-circuits of star-structured quantum circuits.

It should be understood that what is described in this section is not intended to identify key or important features of the embodiments of the disclosure, nor is it intended to limit the scope of the disclosure. Other features of the present disclosure will become readily understood from the following description.

Description of the drawings

The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure. in:

Figure 1 is a schematic flowchart of a quantum circuit processing method according to the first embodiment of the present disclosure;

Figure 2 is a schematic structural diagram of an example static quantum circuit;

Figure 3 is a schematic structural diagram of another example of a static quantum circuit;

Figure 4 is a schematic structural diagram of a dynamic quantum circuit obtained by compiling the quantum circuit shown in Figure 3;

Figure 5 is a schematic structural diagram of an example of a star-structured quantum circuit;

Figure 6 is a schematic structural diagram of another example of a star-structured quantum circuit;

Figure 7 is a schematic structural diagram of a sub-circuit of a star-structured quantum circuit;

Figure 8 is a schematic structural diagram of a dynamic quantum circuit obtained by compiling the quantum circuit shown in Figure 6;

Figure 9 is a schematic structural diagram of a quantum circuit processing device according to a second embodiment of the present disclosure;

Figure 10 is a schematic block diagram of an example electronic device used to implement embodiments of the present disclosure.

Detailed ways

Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, in which various details of the embodiments of the present disclosure are included to facilitate understanding and should be considered to be exemplary only. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the disclosure. Also, descriptions of well-known functions and constructions are omitted from the following description for clarity and conciseness.

First embodiment

As shown in Figure 1, the present disclosure provides a quantum circuit processing method, which includes the following steps:

Step S101: Obtain the first instruction list of the first quantum circuit including N qubits. The first quantum circuit is: a star-structured quantum circuit or a sub-circuit of a star-structured quantum circuit. The star-shaped structure The N qubits in the quantum circuit are arranged in order from the qubits of qubit 0 to the qubits of qubit N-1. In the star structure, each first qubit is placed in the order of qubits from small to large. A two-qubit gate acts between a qubit and a target qubit, the target qubit is any qubit among the N qubits, and the first qubit is any one of the N qubits. Other qubits of the target qubit, the sub-circuit is a quantum circuit obtained by deleting some operation instructions from the instruction list of the star-structured quantum circuit, and N is an integer greater than 2.

In this embodiment, the quantum circuit processing method relates to the field of quantum computing technology, especially to the field of quantum circuit technology. It can be widely used in the classical simulation and real machine of star-structured quantum circuits, as well as the sub-circuits of star-structured quantum circuits. operating scenario. The quantum circuit processing method of the embodiment of the present disclosure can be executed by the quantum circuit processing device of the embodiment of the present disclosure. The quantum circuit processing device according to the embodiment of the present disclosure can be configured in any electronic device to execute the quantum circuit processing method according to the embodiment of the present disclosure.

Currently, the more mainstream implementation of quantum computing is based on the quantum circuit model, which uses a series of quantum gates on qubits to complete the evolution of the quantum state, and performs quantum measurements at the end of the circuit to obtain the calculation results. The currently commonly used quantum circuits in the industry are static quantum circuits, that is, quantum circuits that only contain measurement operations at the end of the circuit.

With the recent rapid development of hardware (mainly the significant improvement of qubit coherence time and the realization of high-fidelity intermediate state measurement and reset operations), dynamic quantum circuits including quantum circuit intermediate measurements and reset operations are becoming more and more popular. Attracted by the industry. Due to the introduction of intermediate measurements in the circuit, dynamic quantum circuits can effectively combine quantum computing and real-time classical computing and communication within the coherence time of the qubit. This property greatly increases the diversity of computational tasks that can be achieved through quantum circuit models. For example, using intermediate measurements of dynamic quantum circuits, forward feedback operations can be implemented during circuit operation, that is, deciding which quantum gates to operate next based on the results obtained from intermediate measurements, or discarding the current calculation results and restarting the calculation task. Such functions are very important in quantum error correction and error-tolerant quantum computing. Therefore, it is foreseeable that dynamic quantum circuits will become an important part of various quantum algorithms and quantum applications in the future.

Because qubits in dynamic quantum circuits can be reset and continue to be used during subsequent calculations, dynamic quantum circuits can effectively reduce the computational tasks required to run the same quantum algorithm compared to static quantum circuits. The required number of qubits, and theoretically the computing power will not be affected in any way. For example, the Berstein-Vazirani algorithm that requires n qubits in a static circuit can be implemented with only 2 qubits in a dynamic quantum circuit.

Limited by computer memory and processor capabilities, existing quantum circuit simulation methods can support algorithms that simulate dozens of qubits at most. For example, a laptop can simulate about 20-30 qubits, and large supercomputers and clusters can simulate up to about 30-40 qubits. In terms of real machine operation, due to the unresolved scalability problem of current quantum chips, the number of qubits that quantum computers can provide is very limited. Therefore, quantum circuit optimization is a fundamental problem in the field of quantum computing.

Quantum circuit optimization uses certain technical means to equivalently compile a given quantum circuit into a dynamic quantum circuit to reduce the number of qubits. This can reduce the requirements for its classical simulation and real machine operation, and accelerate the research of quantum algorithms. and the implementation of quantum computing in practical scenarios.

In this embodiment, by compiling the star-structured quantum circuit or the sub-circuits of the star-structured quantum circuit, the original quantum circuit can be greatly simplified in terms of the number of qubits. On the one hand, it can further increase the scale of classical simulations of quantum algorithms and strengthen the ability of classical computers to verify quantum algorithms. On the other hand, it can also reduce the number of bits required for quantum algorithms to run on real machines and make up for the scalability issues of current quantum chips. shortcomings. Star-structured quantum circuits and sub-circuits of star-structured quantum circuits are very important in the use scenarios of quantum algorithms such as the Deutsch-Jozsa algorithm and the Bernstein-Vazirani algorithm.

The quantum circuit model is described in detail below.

At present, the implementation of quantum computing can be based on the quantum circuit model, that is, by applying a series of quantum gates on qubits to complete the evolution of the quantum state, and perform quantum measurements at the end of the circuit to obtain the calculation results. The quantum circuit diagram can represent the entire process of quantum circuit model calculation.

Figure 2 is a schematic structural diagram of an example quantum circuit. As shown in Figure 2, a horizontal line can be used to represent a qubit system, and the qubits of the qubit are numbered from top to bottom. Among them, the qubits are often numbered. Start from scratch.

The direction of time evolution in the quantum circuit diagram is from left to right, with the initial quantum state at the far left end. Usually each qubit is initialized to the zero state, and then different quantum gate operations are applied to the initial state in sequence to complete the evolution of the quantum state. At the same time, quantum measurements can be performed on certain qubits to obtain measurement results.

If a quantum circuit does not include operations such as reset and intermediate quantum measurement, and all measurement operations are located at the end of the quantum circuit, then this type of quantum circuit is called a static quantum circuit. The quantum circuit shown in Figure 2 is static. Quantum circuits.

The operations in a quantum circuit diagram can usually be represented by an ordered instruction list in the order of action, with each element in the instruction list representing an operation instruction.

Each quantum state preparation (or initialization) operation is expressed as an instruction containing four elements [Reset, qubit, None, None]. For example, [Reset,2,None,None] means initializing the qubit of qubit 2 to the zero state.

Each single-bit quantum gate (such as H, The name of the quantum gate, qubit is the qubit that the quantum gate acts on, parameter is the parameter of the quantum gate (if there is no parameter, the default is None), condition indicates which qubit measurement result controls the quantum gate operation (in standard quantum circuits This parameter defaults to None). For example, [Rx, 2, pi, None] means applying an Rx rotating gate to the qubit on qubit 2, and the rotation angle is pi.

Each two-bit quantum gate (such as the controlled NOT gate CNOT, SWAP gate) is represented by an instruction containing four elements [name, qubit, parameter, condition]. Among them, name is the name of the quantum gate, qubit is a list of control bits and controlled bits, parameter is the parameter of the quantum gate (if there is no parameter, it defaults to None), and the condition parameter in a standard quantum circuit defaults to None. For example, [SWAP, [1,2], None, None] means operating the SWAP gate between qubit 1 and 2; [CNOT, [1,3], None, None] means operating the SWAP gate between qubit 1 and qubit 3. The action controls the NOT gate, where qubit 1 is the control bit and qubit 3 is the controlled bit.

More generally, each multi-qubit gate (such as a CCX gate) is represented as an instruction containing four elements [name, qubit, parameter, condition]. Among them, name is the name of the quantum gate, qubit is a list of qubits acted on by the multi-qubit gate, parameter is the parameter of the quantum gate (if there is no parameter, the default is None), and condition indicates which quantum gate the quantum gate operation is affected by. Control of the bit measurement result (defaults to None if there are no parameters).

Each measurement under the calculation basis is represented as an instruction containing four elements [measure, qubit, None, None]. For example, [measure, 2, None, None] represents the measurement of the computational basis for qubit 2.

According to the above instruction representation rules, the static quantum circuit in Figure 2 can be represented as the following ordered instruction list: static_circuit=[[Reset,0,None,None],[Reset,1,None,None],[Reset, 2,None,None],[H,0,None,None],[H,1,None,None],[H,2,None,None],[CNOT,[0,1],None,None] ,[SWAP,[1,2],None,None],[Rx,0,α,None],[Ry,1,β,None],[Rz,2,γ,None],[Measure,0, None,None],[Measure,1,None,None],[Measure,2,None,None]].

In some application scenarios, it is possible to measure certain qubits in the middle of a quantum circuit, and after the measurement results are obtained, these qubits are reset to the |0> state for continued use in subsequent calculations. Quantum circuits that include intermediate measurement and reset operations in the circuit are called dynamic quantum circuits.

Static quantum circuits can be compiled into dynamic quantum circuits through quantum circuit optimization. For example, the static quantum circuit shown in Figure 3 can be equivalently compiled into the dynamic quantum circuit shown in Figure 4. It can be seen that this dynamic quantum circuit is better than the original quantum circuit. For static quantum circuits, the number of qubits is reduced by one, but the operating effects of the two quantum circuits are equivalent.

The instruction list of the original static quantum circuit is: static_circuit=[[Reset,0,None,None],[Reset,1,None,None],[Reset,2,None,None],[H,0,None,None ],[H,1,None,None],[H,2,None,None],[CNOT,[0,1],None,None],[CNOT,[1,2],None,None], [Measure,0,None,None],[Measure,1,None,None],[Measure,2,None,None]]. The instruction list of the compiled dynamic quantum circuit is: dynamic_circuit=[[Reset,0,None,None],[Reset,1,None,None],[H,0,None,None],[H,1,None ,None],[CNOT,[0,1],None,None],[Measure,0,None,None],[Reset,0,None,None],[H,0,None,None],[CNOT ,[1,0],None,None],[Measure,0,None,None],[Measure,1,None,None]].

The purpose of this embodiment is to compile a given static quantum circuit into its equivalent dynamic quantum circuit, and to minimize the number of qubits required for the compiled quantum circuit.

In step S101, the first quantum circuit may be a static quantum circuit, and the first quantum circuit may be a star-structured quantum circuit or a sub-circuit of a star-structured quantum circuit. The star-structured quantum circuit is a type of quantum circuit widely used in quantum algorithms such as the Deutsch-Jozsa algorithm and the Bernstein-Vazirani algorithm.

The connectivity of the star-structured quantum circuit has a unified common qubit, which is the target qubit. For example, the qubit of qubit N-1 is the last qubit, and all the other qubits are arranged in order from small to large qubits. A two-qubit gate acts on the target qubit, and its corresponding topological structure is a star-shaped structure, which is called a star structure. Among them, the double qubit gate can be a CNOT gate, a SWAP gate, or other double qubit gates.

Figure 5 is a schematic structural diagram of an example of a star-structured quantum circuit. As shown in Figure 5, the star-structured quantum circuit contains 4 qubits. The last qubit is used as the target qubit, and qubit 0 is The qubits, the qubits of qubit 1 and the qubits of qubit 2, in turn interact with the qubit of qubit 3 through double qubit gates.

The pre-stored first instruction list of the first quantum circuit may be obtained, the first instruction list of the first quantum circuit input by the user may be obtained, or the instruction list of the third quantum circuit equivalent to the first quantum circuit may be obtained, Obtain the first instruction list of the first quantum circuit, which is not specifically limited here.

The instruction list of the quantum circuit in Figure 5 is: static_circuit=[[Reset,0,None,None],[Reset,1,None,None],[Reset,2,None,None],[Reset,3,None ,None],[CNOT,[0,3],None,None],[CNOT,[1,3],None,None],[CNOT,[2,3],None,None],[Measure,0 ,None,None],[Measure,1,None,None],[Measure,2,None,None],[Measure,3,None,None].

In addition, when the first quantum circuit is a sub-circuit of a star-structured quantum circuit, the first instruction list of the first quantum circuit can also be determined based on the instruction list of the star-structured quantum circuit, which is a star-structured An ordered subset of the quantum circuit, that is, deleting some operation instructions from the instruction list of the star-structured quantum circuit to obtain the first instruction list.

Step S102: Based on the first instruction list, equivalently compile the first quantum circuit to obtain a second instruction list of the second quantum circuit that is equivalent to the first quantum circuit; wherein, the second The number of qubits of the quantum circuit is less than the number of qubits of the first quantum circuit, and the equivalent compilation includes: adding a first reset operation instruction after the first measurement operation instruction in the first instruction list; and Each target operation instruction in the first instruction list is remapped to a qubit of qubit i. The first measurement operation instruction and the first reset operation instruction both act on qubit i. The target operation The instruction acts on qubit i+1, and the value range of i is [0, N-3].

In this step, the second quantum circuit may be a dynamic quantum circuit.

When performing equivalent compilation, the first measurement operation instructions in the first instruction list can be obtained in sequence, and for each first measurement operation instruction, based on the qubit i acted on by the first measurement operation instruction, in the first measurement operation After the instruction, add the first reset operation instruction on the qubit i, and remap each target operation instruction in the first instruction list to the qubit of the qubit i. The first measurement operation instructions are measurement operation instructions acting on qubit 0, qubit 1..., and qubit N-3 respectively.

If N is 3, the first measurement operation instruction is a measurement operation instruction acting on qubit 0. That is, during equivalent compilation, add the reset operation instruction on qubit 0 after the measurement operation instruction on qubit 0, and remap the target operation instruction acting on qubit 1 in the first instruction list to Map to the qubit of qubit 0, thereby obtaining the second instruction list of the second quantum circuit that is equivalent to the first quantum circuit.

If N is 4, the first measurement operation instructions are measurement operation instructions acting on qubit 0 and qubit 1 respectively. That is to say, during equivalent compilation, first target the measurement operation instruction on qubit 0, add the reset operation instruction on qubit 0 after the measurement operation instruction on qubit 0, and apply the first instruction list to the qubit. The target operation instruction on qubit 1 is remapped to the qubit of qubit 0. Then, for the measurement operation instruction on qubit 1, add the reset operation instruction on qubit 1 after the measurement operation instruction on qubit 1, and reset the target operation instruction acting on qubit 2 in the first instruction list. Mapping, mapping it to the qubit of qubit 1, so that the second instruction list of the second quantum circuit equivalent to the first quantum circuit can be obtained.

In this way, after equivalent compilation of the operation instructions of the quantum measurement operation, the operation instructions of the reset operation can be added after the operation instructions of the quantum measurement operation. Through the reset operation instructions, the register unit allocated to qubit i can be recycled , for the qubit of qubit i+1 to continue to be used to reduce the number of qubits of the compiled second quantum circuit.

In an optional implementation, equivalent compilation of the first quantum circuit can be directly performed based on the first instruction list, that is, by traversing the first instruction list, the first measurement operation instruction and the target operation instruction are respectively obtained, and the first measurement operation instruction and the target operation instruction are executed. An equivalent compilation of a quantum circuit. In another optional implementation, a directed acyclic graph can be constructed based on the first instruction list, and equivalent compilation of the first quantum circuit can be performed based on the directed acyclic graph.

In related technologies, heuristic algorithms are usually used for quantum circuit compilation, which cannot guarantee the optimality of circuit compilation. If the optimal compilation solution is given through mathematical modeling of circuit compilation, however, the complexity of the algorithm increases exponentially with the number of qubits. , the compilation efficiency for larger-scale circuits is very low. In this embodiment, due to the structural particularity of the star-structured quantum circuit, the qubit of qubit i can be reset after measurement, and all operating instructions acting on the qubit of qubit i+1 can be remapped. To execute on the qubit of qubit i, this rule is proved theoretically based on the circuit structure.

In terms of time complexity, this embodiment does not require the construction of a complex mathematical model, so the compilation process is simple, and the running time can grow linearly with N, making the compilation very efficient. In terms of compilation effect, the compiled dynamic quantum circuit will only require 2 qubits. It can be theoretically proven that the compilation scheme in this embodiment is the optimal compilation scheme, which means that there is no compilation scheme that makes the compiled circuit width less than 2. In this way, this embodiment provides an optimal compilation method for a star-structured quantum circuit and the sub-circuits of a star-structured quantum circuit, which can be directly applied to corresponding scenarios without the need for complex calculations and optimizations.

Moreover, quantum computers designed based on different architectures also have different numbers of qubits and capabilities in realizing various operations. Through equivalent compilation, the operation scheme of quantum circuits on real quantum computers can be made more flexible, and one can flexibly choose between dynamic quantum circuits and static quantum circuits according to actual hardware conditions. For example, superconducting quantum computers with short coherence time but easy expansion of the number of qubits are more suitable for running static quantum circuits with larger width and smaller depth; while for superconducting quantum computers with long coherence time but relatively poor scalability, they are more suitable for running static quantum circuits with larger width and smaller depth. Quantum computers with ion trap architecture are more suitable for running dynamic quantum circuits with smaller width and larger depth.

Optionally, the first quantum circuit also includes at least one single qubit gate, and the single qubit gate is located at any position of the first quantum circuit.

The equivalent compilation process in this embodiment has nothing to do with the number, type, specific execution position and other information of single qubit gates. Therefore, the first quantum circuit in this embodiment ensures that it is a star structure, or that it is a star structure. In the case of a sub-circuit of a quantum circuit with a type structure, a single qubit gate may also be included.

Figure 6 is a schematic structural diagram of another example of a star-structured quantum circuit. As shown in Figure 6, a single qubit gate can be added at any position of the quantum circuit shown in Figure 5, or the CNOT gate can be replaced with another double qubit gate. Qubit gate. As long as the two-qubit gate of a quantum circuit satisfies the star structure, the quantum circuit is a star-structured quantum circuit.

For the star structure quantum circuit shown in Figure 6, the instruction list is static_circuit=[[Reset,0,None,None],[Reset,1,None,None],[Reset,2,None,None], [Reset,3,None,None],[H,0,None,None],[S,1,None,None],[T,2,None,None],[H,3,None,None], [CNOT,[0,3],None,None],[Z,1,None,None],[CNOT,[1,3],None,None],[CNOT,[2,3],None,None ],[Rx,0,0.5,None],[Rz,1,0.1,None],[Measure,0,None,None],[Measure,1,None,None],[Measure,2,None,None ],[Measure,3,None,None]].

FIG. 7 is a schematic structural diagram of a sub-circuit of an example star-structured quantum circuit. As shown in FIG. 7 , it is a quantum circuit obtained by deleting some operating instructions of a two-qubit gate on the basis of FIG. 6 .

In this way, the applicable scope of original quantum circuits processed by quantum circuits can be expanded.

Optionally, step S102 specifically includes:

Based on the first instruction list, a first directed acyclic graph is determined, the first directed acyclic graph includes nodes corresponding to the operation instructions in the first instruction list and first directed edges, and the first directed acyclic graph Directed edges are used to characterize the timing relationship between different operation instructions in the first instruction list;

Add a second directed edge to the first directed acyclic graph to obtain a directed edge list composed of the second directed acyclic graph and the second directed edge, where the second directed edge includes all The first measurement operation instruction corresponds to the directed edge from the output node to the second reset operation instruction corresponding to the input node, and the second reset operation instruction is a reset operation instruction acting on qubit i+1;

Based on the second directed acyclic graph and the directed edge list, the first quantum circuit is equivalently compiled to obtain a second instruction list of the second quantum circuit equivalent to the first quantum circuit. .

In an optional implementation, the first instruction list can be traversed in the order of instructions from left to right, and the nearest neighbor of the intersection between the qubit acted on and the qubit acted upon by the currently traversed operation instruction is searched. Operate instructions to construct the first directed acyclic graph.

In another optional implementation, optionally, determining the first directed acyclic graph based on the first instruction list includes:

Traverse the first instruction list in the order in which the operation instructions are arranged;

Use the currently traversed operation instruction as a node, and if the target list is not an empty list, add the operation instruction corresponding node at the end of the target list to the first directed edge of the currently traversed operation instruction corresponding node; so The target list is a list corresponding to the qubits acted upon by the currently traversed operation instruction;

The currently traversed operation instructions are added to the end of the target list, and when the traversal of the first instruction list is completed, the first directed acyclic graph is obtained.

That is, by constructing N target lists with one-to-one correspondence of N qubits, the preceding operation instructions of the currently traversed operation instructions are stored. Based on the qubit acted upon by the currently traversed operation instruction, a target list corresponding to the qubit is obtained. The qubits acted upon by the operation instructions in the target list all intersect with the qubits acted upon by the currently traversed operation instruction. Select its nearest neighbor operation instruction, that is, the operation instruction at the end of the target list, to construct the first directed edge. In this way, the construction process of the first directed acyclic graph can be simplified and the efficient construction of the first directed acyclic graph can be achieved.

Further, a second directed edge is added to the first directed acyclic graph to obtain a directed edge list composed of the second directed acyclic graph and the second directed edge. The second directed edge is The edge includes a directed edge from an output node corresponding to the first measurement operation instruction to an input node corresponding to the second reset operation instruction. The second reset operation instruction is a reset operation instruction acting on qubit i+1. For example, if N is 3, the second directed edge is the directed edge from the output node corresponding to the measurement operation instruction acting on qubit 0 to the input node corresponding to the reset operation instruction acting on qubit 1. For another example, if N is 4, the second directed edge includes: the directed edge from the output node corresponding to the measurement operation instruction acting on qubit 0 to the input node corresponding to the reset operation instruction acting on qubit 1, and The directed edge from the measurement operation instruction acting on qubit 1 corresponds to the output node to the reset operation instruction acting on qubit 2 corresponds to the input node.

Then, based on the second directed acyclic graph and the directed edge list, the first quantum circuit is equivalently compiled to obtain a second instruction list of the second quantum circuit that is equivalent to the first quantum circuit. Optionally, the first quantum circuit is equivalently compiled based on the second directed acyclic graph and the directed edge list to obtain a second quantum circuit equivalent to the first quantum circuit. The second instruction list of the circuit includes:

Obtain the topological sorting of the operation instructions corresponding to the second directed acyclic graph and obtain a third instruction list;

For each second directed edge in the directed edge list, remap each target operation instruction corresponding to the qubit acted on by the input node of the second directed edge in the third instruction list to The output node of the second directed edge acts on the qubit to obtain the second instruction list.

The optimal compilation process of the first quantum circuit is as follows:

Input: circuit_list, the first instruction list of the first quantum circuit, circuit width N (N>2);

Output: The compiled second instruction list of the dynamic quantum circuit.

Step 1: Initialize an empty directed acyclic graph digraph;

Step 2: Initialize a target list causal_lists of length N, where each element is an empty list;

Step 3: Loop circuit_list, assuming the currently looped element is instruction:

Step 3.1: Take out the qubit value in the instruction instruction and perform a loop. Let the element being looped be q. Use instruction as a node and add it to the directed acyclic graph digraph; find the last element of the target list causal_lists[q] and record it. is preinstruction; if preinstruction is not an empty element, add the first directed edge to the directed acyclic graph digraph, pointing from preinstruction to instruction; add instruction to the end of the list causal_lists[q];

Step 4: Initialize an empty list added_edges (i.e. directed edge list);

Step 5: Loop over the variables i∈{0,···,N-3}:

Step 5.1: Add a second directed edge to the directed acyclic graph digraph, from the measurement operation instruction acting on qubit i to the reset operation instruction acting on qubit i+1, and add a directed edge at the same time to the added_edges list;

Step 6: Obtain the topological sorting of all circuit instructions based on the directed acyclic graph digraph, and record it in circuit_list;

Step 7: Loop through the added_edges list, assuming the variable of the current loop is edge:

Step 7.1: Let preinstruction and postinstruction represent the output node and input node of the directed edge respectively;

Step 7.2: Note that the qubits acted upon by the two operation instructions preinstruction and postinstruction are prequbit and postqubit respectively; loop through the circuit_list list and update all target operation instructions acting on the qubit postqubit to those acting on the qubit prequbit;

Step 8: Return circuit_list as output.

In this way, equivalent compilation of star-structured quantum circuits and sub-circuits of star-structured quantum circuits can be achieved with the help of directed acyclic graphs, and the implementation process is very simple.

For the quantum circuit in Figure 6, the dynamic quantum circuit obtained after compiling the solution in this embodiment is shown in Figure 8, and its corresponding circuit instruction list is: dynamic_circuit=[[Reset,0,None,None],[Reset ,1,None,None],[H,0,None,None],[H,1,None,None],[CNOT,[0,1],None,None],[Rx,0,0.5,None ],[Measure,0,None,None],[Reset,0,None,None],[S,0,None,None],[Z,0,None,None],[CNOT,[0,1] ,None,None],[Rz,0,0.1,None],[Measure,0,None,None],[Reset,0,None,None],[T,0,None,None],[CNOT,[ 0,1],None,None],[Measure,0,None,None],[Measure,1,None,None]]. The number of qubits in its dynamic quantum circuit is 2, which is the optimal compilation solution.

Optionally, in the case where the first quantum circuit is a star-structured quantum circuit, step S101 specifically includes:

Add a reset operation instruction for each qubit in the first quantum circuit to the circuit list;

Determine the first qubit of the target qubit, and compare the qubits of other qubits in the first quantum circuit except the first qubit with the target in order of qubits from small to large. The operating instructions for each two-qubit gate between qubits are added to the circuit list;

Add the quantum measurement operation instructions of each qubit in the first quantum circuit to the circuit list to obtain the first instruction list.

The specific process of obtaining the circuit instruction list of a quantum circuit with a star structure containing N qubits is as follows. Among them, the target qubit can be the qubit of qubit N-1, which is the last qubit in the quantum circuit.

Input: quantum circuit width N;

Output: A list of instructions for a star-structured quantum circuit.

Step 1: Initialize an empty list circuit_list;

Step 2: Loop over the variable i∈{0,1,···,N-1}:

Step 2.1: Add the reset operation command [Reset,i,None,None] to the end of the circuit_list list;

Step 3: Loop over the variables i∈{0,1,···,N-2}:

Step 3.1: Add the operation instructions of the double qubit gate such as [CNOT, [i, N-1], None, None] to the end of the list circuit_list;

Step 4: Loop over the variable i∈{0,1,···,N-1}:

Step 4.1: Add the circuit command [Measure,i,None,None] to the end of the list circuit_list;

Step 5: Return circuit_list as output.

In this way, the first instruction list of the star-structured quantum circuit can be obtained by inputting the structural information of the star-structured quantum circuit, and the process is simple.

In the case where the first quantum circuit is a star-structured quantum circuit, optionally, before step S101, the method further includes:

Perform permutation mapping on a third quantum circuit including N qubits, so that the N qubits in the third quantum circuit are ordered in order from the qubits of qubit 0 to the qubits of qubit N-1;

In the case where the third quantum circuit after replacement mapping is a quantum circuit with a star structure, it is determined that the third quantum circuit is equivalent to the first quantum circuit.

For the third quantum circuit that is not a standard quantum circuit, it can be converted into a standard quantum circuit. If the standard quantum circuit obtained after conversion is a star-structured quantum circuit, it means that the third quantum circuit is equivalent to the first quantum circuit. of. Among them, in a standard quantum circuit, N qubits are arranged in order from the qubits of qubit 0 to the qubits of qubit N-1.

In this way, the applicable scope of original quantum circuits processed by quantum circuits can be expanded.

Optionally, in the case where the third quantum circuit after replacement mapping is a quantum circuit with a star structure, step S101 specifically includes:

Obtain the fourth instruction list of the third quantum circuit;

The first numbered list of N qubits in the third quantum circuit is replaced to obtain a second numbered list. The second numbered list is sequentially from qubits of qubit 0 to qubits of qubit N-1. arranged in order;

Based on the mapping relationship between the first numbered list and the second numbered list, the qubits acted upon by the operation instructions in the fourth instruction list are transformed to obtain the first instruction list.

Wherein, the first numbered list of N qubits in the third quantum circuit can be permuted based on a permutation matrix to obtain a second numbered list. The permutation matrix can be input by the user or preset. Afterwards, based on the mapping relationship between the first numbered list and the second numbered list, for example, qubit 2 in the third quantum circuit is mapped to qubit 0 in the first quantum circuit, the operation instructions in the fourth instruction list act on The qubits are transformed, for example, the operation instructions acting on qubit 2 in the fourth instruction list are remapped to qubit 0 to obtain the first instruction list of the first quantum circuit.

In this way, the instruction list of the first quantum circuit can be obtained based on the instruction list of the third quantum circuit that is equivalent to the first quantum circuit.

Second embodiment

As shown in Figure 9, the present disclosure provides a quantum circuit processing device 900, including:

The acquisition module 901 is used to acquire the first instruction list of a first quantum circuit including N qubits. The first quantum circuit is: a star-structured quantum circuit or a sub-circuit of a star-structured quantum circuit. The N qubits in the star-shaped quantum circuit are arranged in an orderly manner from the qubits of qubit 0 to the qubits of qubit N-1. In the star-shaped structure, the qubits are placed in each qubit in order from small to large. A two-qubit gate is used between the first qubit and the target qubit. The target qubit is any qubit among the N qubits. The first qubit is one of the N qubits. In addition to other qubits of the target qubit, the sub-circuit is a quantum circuit obtained by deleting some operation instructions from the instruction list of the star-structured quantum circuit, and N is an integer greater than 2;

The equivalent compilation module 902 is configured to perform equivalent compilation on the first quantum circuit based on the first instruction list to obtain a second instruction list of the second quantum circuit equivalent to the first quantum circuit;

Wherein, the number of qubits of the second quantum circuit is less than the number of qubits of the first quantum circuit, and the equivalent compilation includes: adding a first reset after the first measurement operation instruction in the first instruction list Operation instructions; and remap each target operation instruction in the first instruction list to the qubit of qubit i, and the first measurement operation instruction and the first reset operation instruction both act on qubit i On, the target operation instruction acts on qubit i+1, and the value range of i is [0, N-3].

Optionally, the equivalent compilation module 902 includes:

A determination unit configured to determine a first directed acyclic graph based on the first instruction list, where the first directed acyclic graph includes nodes corresponding to the operation instructions in the first instruction list and first directed edges. , the first directed edge is used to characterize the timing relationship between different operation instructions in the first instruction list;

Adding a unit for adding a second directed edge to the first directed acyclic graph to obtain a directed edge list composed of the second directed acyclic graph and the second directed edge, the second The directed edge includes the directed edge from the output node corresponding to the first measurement operation instruction to the input node corresponding to the second reset operation instruction. The second reset operation instruction is a reset operation acting on qubit i+1. instruction;

An equivalent compilation unit is configured to perform equivalent compilation on the first quantum circuit based on the second directed acyclic graph and the directed edge list to obtain a second quantum circuit equivalent to the first quantum circuit. Second instruction list for quantum circuits.

Optionally, the determination unit is specifically used for:

Traverse the first instruction list in the order in which the operation instructions are arranged;

Use the currently traversed operation instruction as a node, and if the target list is not an empty list, add the operation instruction corresponding node at the end of the target list to the first directed edge of the currently traversed operation instruction corresponding node; so The target list is a list corresponding to the qubits acted upon by the currently traversed operation instruction;

The currently traversed operation instructions are added to the end of the target list, and when the traversal of the first instruction list is completed, the first directed acyclic graph is obtained.

Optional, the equivalent compilation unit is specifically used for:

Obtain the topological sorting of the operation instructions corresponding to the second directed acyclic graph and obtain a third instruction list;

For each second directed edge in the directed edge list, remap each target operation instruction corresponding to the qubit acted on by the input node of the second directed edge in the third instruction list to The output node of the second directed edge acts on the qubit to obtain the second instruction list.

Optionally, in the case where the first quantum circuit is a star-structured quantum circuit, the acquisition module 901 is specifically used to:

Add a reset operation instruction for each qubit in the first quantum circuit to the circuit list;

Determine the first qubit of the target qubit, and compare the qubits of other qubits in the first quantum circuit except the first qubit with the target in order of qubits from small to large. The operating instructions for each two-qubit gate between qubits are added to the circuit list;

Add the quantum measurement operation instructions of each qubit in the first quantum circuit to the circuit list to obtain the first instruction list.

Optionally, the device also includes:

A permutation mapping module, used to perform permutation mapping on a third quantum circuit including N qubits, so as to sequentially map the N qubits in the third quantum circuit from qubits of qubit 0 to qubits of qubit N-1. Bits are arranged in an orderly manner;

A determination module configured to determine that the third quantum circuit is equivalent to the first quantum circuit when the third quantum circuit after replacement mapping is a quantum circuit with a star structure.

Optionally, when the third quantum circuit after replacement mapping is a quantum circuit with a star structure, the acquisition module 901 is specifically used to:

Obtain the fourth instruction list of the third quantum circuit;

The first numbered list of N qubits in the third quantum circuit is replaced to obtain a second numbered list. The second numbered list is sequentially from qubits of qubit 0 to qubits of qubit N-1. arranged in order;

Based on the mapping relationship between the first numbered list and the second numbered list, the qubits acted upon by the operation instructions in the fourth instruction list are transformed to obtain the first instruction list.

Optionally, the first quantum circuit also includes at least one single qubit gate, and the single qubit gate is located at any position of the first quantum circuit.

The quantum circuit processing device 900 provided by the present disclosure can implement various processes implemented by the embodiments of the quantum circuit processing method, and can achieve the same beneficial effects. To avoid duplication, they will not be described again here.

In the technical solution of this disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information are in compliance with relevant laws and regulations and do not violate public order and good customs.

According to embodiments of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

Figure 10 shows a schematic block diagram of an example electronic device that may be used to implement embodiments of the present disclosure. Electronic devices are intended to refer to various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. Electronic devices may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are examples only and are not intended to limit implementations of the disclosure described and/or claimed herein.

As shown in FIG. 10 , the device 1000 includes a computing unit 1001 that can execute according to a computer program stored in a read-only memory (ROM) 1002 or loaded from a storage unit 1008 into a random access memory (RAM) 1003 Various appropriate actions and treatments. In the RAM 1003, various programs and data required for the operation of the device 1000 can also be stored. Computing unit 1001, ROM 1002 and RAM 1003 are connected to each other via bus 1004. An input/output (I/O) interface 1005 is also connected to bus 1004.

Multiple components in the device 1000 are connected to the I/O interface 1005, including: input unit 1006, such as a keyboard, mouse, etc.; output unit 1007, such as various types of displays, speakers, etc.; storage unit 1008, such as a magnetic disk, optical disk, etc. ; and communication unit 1009, such as a network card, modem, wireless communication transceiver, etc. The communication unit 1009 allows the device 1000 to exchange information/data with other devices through computer networks such as the Internet and/or various telecommunications networks.

Computing unit 1001 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of the computing unit 1001 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processing processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 1001 performs various methods and processes described above, such as quantum circuit processing methods. For example, in some embodiments, the quantum circuit processing method may be implemented as a computer software program that is tangibly embodied in a machine-readable medium, such as storage unit 1008. In some embodiments, part or all of the computer program may be loaded and/or installed onto device 1000 via ROM 1002 and/or communication unit 1009 . When the computer program is loaded into RAM 1003 and executed by computing unit 1001, one or more steps of the quantum circuit processing method described above may be performed. Alternatively, in other embodiments, the computing unit 1001 may be configured to perform quantum circuit processing methods in any other suitable manner (eg, by means of firmware).

Various implementations of the systems and techniques described above may be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on a chip implemented in a system (SOC), load programmable logic device (CPLD), computer hardware, firmware, software, and/or a combination thereof. These various embodiments may include implementation in one or more computer programs executable and/or interpreted on a programmable system including at least one programmable processor, the programmable processor The processor, which may be a special purpose or general purpose programmable processor, may receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device. An output device.

Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that the program codes, when executed by the processor or controller, cause the functions specified in the flowcharts and/or block diagrams/ The operation is implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media may include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media would include one or more wire-based electrical connections, laptop disks, hard drives, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination of the above.

To provide interaction with a user, the systems and techniques described herein may be implemented on a computer having a display device (eg, a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user ); and a keyboard and pointing device (eg, a mouse or a trackball) through which a user can provide input to the computer. Other kinds of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and may be provided in any form, including Acoustic input, voice input or tactile input) to receive input from the user.

The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., A user's computer having a graphical user interface or web browser through which the user can interact with implementations of the systems and technologies described herein), or including such backend components, middleware components, or any combination of front-end components in a computing system. The components of the system may be interconnected by any form or medium of digital data communication (eg, a communications network). Examples of communication networks include: local area network (LAN), wide area network (WAN), and the Internet.

Computer systems may include clients and servers. Clients and servers are generally remote from each other and typically interact over a communications network. The relationship of client and server is created by computer programs running on corresponding computers and having a client-server relationship with each other. The server can be a cloud server, a distributed system server, or a server combined with a blockchain.

It should be understood that various forms of the process shown above may be used, with steps reordered, added or deleted. For example, each step described in the present disclosure can be executed in parallel, sequentially, or in a different order. As long as the desired results of the technical solutions disclosed in the present disclosure can be achieved, there is no limitation here.

The above-mentioned specific embodiments do not constitute a limitation on the scope of the present disclosure. It will be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions are possible depending on design requirements and other factors. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this disclosure shall be included in the protection scope of this disclosure.

Claims (19)

1. A quantum circuit processing method, including: Obtaining a first instruction list of a first quantum circuit including N qubits, the first quantum circuit being: a star-structured quantum circuit or a sub-circuit of a star-structured quantum circuit, the star-structured quantum circuit The N qubits in the qubit are arranged in order from the qubit of qubit 0 to the qubit of qubit N-1. In the star structure, each first qubit and the qubit are arranged in order from small to large. A two-qubit gate acts between target qubits, the target qubit is any qubit among the N qubits, and the first qubit is any of the N qubits except the target qubit. Other qubits, the sub-circuit is a quantum circuit obtained by deleting some operation instructions from the instruction list of a star-structured quantum circuit, and N is an integer greater than 2; Based on the first instruction list, perform equivalent compilation on the first quantum circuit to obtain a second instruction list of the second quantum circuit equivalent to the first quantum circuit; Wherein, the number of qubits of the second quantum circuit is less than the number of qubits of the first quantum circuit, and the equivalent compilation includes: adding a first reset after the first measurement operation instruction in the first instruction list Operation instructions; and remap each target operation instruction in the first instruction list to the qubit of qubit i, and the first measurement operation instruction and the first reset operation instruction both act on qubit i On, the target operation instruction acts on qubit i+1, and the value range of i is [0, N-3]. 2. The method according to claim 1, wherein the first quantum circuit is equivalently compiled based on the first instruction list to obtain a second quantum circuit equivalent to the first quantum circuit. The second instruction list includes: Based on the first instruction list, a first directed acyclic graph is determined, the first directed acyclic graph includes nodes corresponding to the operation instructions in the first instruction list and first directed edges, and the first directed acyclic graph Directed edges are used to characterize the timing relationship between different operation instructions in the first instruction list; Add a second directed edge to the first directed acyclic graph to obtain a directed edge list composed of the second directed acyclic graph and the second directed edge, where the second directed edge includes all The first measurement operation instruction corresponds to the directed edge from the output node to the second reset operation instruction corresponding to the input node, and the second reset operation instruction is a reset operation instruction acting on qubit i+1; Based on the second directed acyclic graph and the directed edge list, the first quantum circuit is equivalently compiled to obtain a second instruction list of the second quantum circuit equivalent to the first quantum circuit. . 3. The method of claim 2, wherein determining the first directed acyclic graph based on the first instruction list includes: Traverse the first instruction list in the order in which the operation instructions are arranged; Use the currently traversed operation instruction as a node, and if the target list is not an empty list, add the operation instruction corresponding node at the end of the target list to the first directed edge of the currently traversed operation instruction corresponding node; so The target list is a list corresponding to the qubits acted upon by the currently traversed operation instruction; The currently traversed operation instructions are added to the end of the target list, and when the traversal of the first instruction list is completed, the first directed acyclic graph is obtained. 4. The method according to claim 2, wherein the first quantum circuit is equivalently compiled based on the second directed acyclic graph and the directed edge list to obtain the same as the first quantum circuit. The second instruction list of a second quantum circuit equivalent to one quantum circuit includes: Obtain the topological sorting of the operation instructions corresponding to the second directed acyclic graph and obtain a third instruction list; For each second directed edge in the directed edge list, remap each target operation instruction corresponding to the qubit acted on by the input node of the second directed edge in the third instruction list to The output node of the second directed edge acts on the qubit to obtain the second instruction list. 5. The method according to claim 1, wherein, in the case where the first quantum circuit is a quantum circuit with a star structure, the obtaining the first instruction list of the first quantum circuit including N qubits, include: Add a reset operation instruction for each qubit in the first quantum circuit to the circuit list; Determine the first qubit of the target qubit, and compare the qubits of other qubits in the first quantum circuit except the first qubit with the target in order of qubits from small to large. The operating instructions for each two-qubit gate between qubits are added to the circuit list; Add the quantum measurement operation instructions of each qubit in the first quantum circuit to the circuit list to obtain the first instruction list. 6. The method according to claim 1, before obtaining the first instruction list of the first quantum circuit including N qubits, further comprising: Perform permutation mapping on a third quantum circuit including N qubits, so that the N qubits in the third quantum circuit are ordered in order from the qubits of qubit 0 to the qubits of qubit N-1; In the case where the third quantum circuit after replacement mapping is a quantum circuit with a star structure, it is determined that the third quantum circuit is equivalent to the first quantum circuit. 7. The method according to claim 6, wherein, in the case where the third quantum circuit after replacement mapping is a quantum circuit with a star structure, the acquisition of the first quantum circuit including N qubits is A list of instructions, including: Obtain the fourth instruction list of the third quantum circuit; The first numbered list of N qubits in the third quantum circuit is replaced to obtain a second numbered list. The second numbered list is sequentially from qubits of qubit 0 to qubits of qubit N-1. arranged in order; Based on the mapping relationship between the first numbered list and the second numbered list, the qubits acted upon by the operation instructions in the fourth instruction list are transformed to obtain the first instruction list. 8. The method according to claim 1, wherein the first quantum circuit further includes at least one single qubit gate, and the single qubit gate is located at any position of the first quantum circuit. 9. A quantum circuit processing device, including: An acquisition module, configured to acquire a first instruction list of a first quantum circuit including N qubits, where the first quantum circuit is: a star-structured quantum circuit or a sub-circuit of a star-structured quantum circuit, where the star The N qubits in the quantum circuit of the star-shaped structure are arranged in an orderly manner from the qubits of qubit 0 to the qubits of qubit N-1. In the star-shaped structure, each qubit is arranged in order from small to large. A two-qubit gate operates between the first qubit and the target qubit. The target qubit is any qubit among the N qubits. The first qubit is any one of the N qubits. For other qubits of the target qubit, the sub-circuit is a quantum circuit obtained by deleting some operation instructions from the instruction list of the star-structured quantum circuit, and N is an integer greater than 2; An equivalent compilation module, configured to perform equivalent compilation on the first quantum circuit based on the first instruction list to obtain a second instruction list of the second quantum circuit equivalent to the first quantum circuit; Wherein, the number of qubits of the second quantum circuit is less than the number of qubits of the first quantum circuit, and the equivalent compilation includes: adding a first reset after the first measurement operation instruction in the first instruction list Operation instructions; and remap each target operation instruction in the first instruction list to the qubit of qubit i, and the first measurement operation instruction and the first reset operation instruction both act on qubit i On, the target operation instruction acts on qubit i+1, and the value range of i is [0, N-3]. 10. The apparatus of claim 9, wherein the equivalent compilation module includes: A determination unit configured to determine a first directed acyclic graph based on the first instruction list, where the first directed acyclic graph includes nodes corresponding to the operation instructions in the first instruction list and first directed edges. , the first directed edge is used to characterize the timing relationship between different operation instructions in the first instruction list; Adding a unit for adding a second directed edge to the first directed acyclic graph to obtain a directed edge list composed of the second directed acyclic graph and the second directed edge, the second The directed edge includes the directed edge from the output node corresponding to the first measurement operation instruction to the input node corresponding to the second reset operation instruction. The second reset operation instruction is a reset operation acting on qubit i+1. instruction; An equivalent compilation unit is configured to perform equivalent compilation on the first quantum circuit based on the second directed acyclic graph and the directed edge list to obtain a second quantum circuit equivalent to the first quantum circuit. Second instruction list for quantum circuits. 11. The device according to claim 10, wherein the determining unit is specifically used to: Traverse the first instruction list in the order in which the operation instructions are arranged; Use the currently traversed operation instruction as a node, and if the target list is not an empty list, add the operation instruction corresponding node at the end of the target list to the first directed edge of the currently traversed operation instruction corresponding node; so The target list is a list corresponding to the qubits acted upon by the currently traversed operation instruction; The currently traversed operation instructions are added to the end of the target list, and when the traversal of the first instruction list is completed, the first directed acyclic graph is obtained. 12. The device according to claim 10, wherein the equivalent compilation unit is specifically used for: Obtain the topological sorting of the operation instructions corresponding to the second directed acyclic graph and obtain a third instruction list; For each second directed edge in the directed edge list, remap each target operation instruction corresponding to the qubit acted on by the input node of the second directed edge in the third instruction list to The output node of the second directed edge acts on the qubit to obtain the second instruction list. 13. The device according to claim 9, wherein, when the first quantum circuit is a quantum circuit with a star structure, the acquisition module is specifically configured to: Add a reset operation instruction for each qubit in the first quantum circuit to the circuit list; Determine the first qubit of the target qubit, and compare the qubits of other qubits in the first quantum circuit except the first qubit with the target in order of qubits from small to large. The operating instructions for each two-qubit gate between qubits are added to the circuit list; Add the quantum measurement operation instructions of each qubit in the first quantum circuit to the circuit list to obtain the first instruction list. 14. The device of claim 9, further comprising: A permutation mapping module, used to perform permutation mapping on a third quantum circuit including N qubits, so as to sequentially map the N qubits in the third quantum circuit from qubits of qubit 0 to qubits of qubit N-1. Bits are arranged in order; A determination module configured to determine that the third quantum circuit is equivalent to the first quantum circuit when the third quantum circuit after replacement mapping is a quantum circuit with a star structure. 15. The device according to claim 14, wherein when the third quantum circuit after replacement mapping is a quantum circuit with a star structure, the acquisition module is specifically configured to: Obtain the fourth instruction list of the third quantum circuit; The first numbered list of N qubits in the third quantum circuit is replaced to obtain a second numbered list. The second numbered list is sequentially from qubits of qubit 0 to qubits of qubit N-1. arranged in order; Based on the mapping relationship between the first numbered list and the second numbered list, the qubits acted upon by the operation instructions in the fourth instruction list are transformed to obtain the first instruction list. 16. The device according to claim 9, wherein the first quantum circuit further includes at least one single qubit gate, and the single qubit gate is located at any position of the first quantum circuit. 17. An electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform any one of claims 1-8. Methods. 18. A non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause the computer to perform the method according to any one of claims 1-8. 19. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any one of claims 1-8.