CN116611527B

CN116611527B - Quantum circuit processing method and device and electronic equipment

Info

Publication number: CN116611527B
Application number: CN202310579860.4A
Authority: CN
Inventors: 石如琪; 方堃
Original assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Current assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Priority date: 2023-05-22
Filing date: 2023-05-22
Publication date: 2023-11-21
Anticipated expiration: 2043-05-22
Also published as: CN116611527A

Abstract

The disclosure provides a quantum circuit processing method, a quantum circuit processing device and electronic equipment, relates to the technical field of quantum computing, and particularly relates to the technical field of quantum circuits. The specific implementation scheme is as follows: acquiring a first instruction list of a first quantum circuit; determining a first directed acyclic graph based on the first list of instructions; determining first connectable information; sequentially determining a second directed edge based on the first directed acyclic graph and the first connectable information, sequentially adding the second directed edge to obtain a second directed acyclic graph, wherein the second directed edge is a candidate directed edge with the largest scoring value among M candidate directed edges, the scoring value is used for representing the maximum value in the number of the directed edges from an output node to an input node in a third directed acyclic graph, and the third directed acyclic graph is obtained after adding the candidate directed edge in the first directed acyclic graph; and based on the second directed acyclic graph, the first target list and the first instruction list, performing equivalent compiling on the first quantum circuit to obtain a second instruction list of the second quantum circuit.

Description

Quantum circuit processing method and device and electronic equipment

Technical Field

The disclosure relates to the technical field of quantum computing, in particular to the technical field of quantum circuits, and specifically relates to a quantum circuit processing method, a quantum circuit processing device and electronic equipment.

Background

The quantum computing provides a brand new and very promising information processing mode by utilizing the specific operation rule in the quantum world. Quantum algorithms can offer advantages over classical algorithms over a number of specific problems. For example, large integers can be efficiently decomposed using the schiff (shell) algorithm, and data search can be performed faster using the Grover (Grover) algorithm. With the development of quantum theory, new quantum algorithms are continuously proposed, and how to efficiently simulate the algorithms or run the algorithms on real quantum hardware is always an important problem.

Currently, classical simulation or true operation of quantum algorithms is mainly limited by the number of qubits. In classical simulation, since the length of the column vector describing the quantum state grows exponentially with the corresponding number of bits (e.g., the length of the column vector of an n-bit quantum state is 2 ⁿ ) Classical computers have difficulty simulating large-scale quantum algorithms. Limited by computer memory and processor capacity, existing quantum circuit simulation methods can support algorithms simulating tens of qubits at most。

Disclosure of Invention

The disclosure provides a quantum circuit processing method, a quantum circuit processing device and electronic equipment.

According to a first aspect of the present disclosure, there is provided a quantum circuit processing method, comprising:

acquiring a first instruction list of a first quantum circuit;

determining a first directed acyclic graph based on the first instruction list, wherein the first directed acyclic graph comprises nodes corresponding to instructions in the first instruction list and first directed edges, and the first directed edges are used for representing time sequence relations among different instructions in the first instruction list;

determining first connectable information of the first directed acyclic graph, wherein the first connectable information is used for representing the connectivity from an output node to an input node, the input node is a node corresponding to a reset operation instruction in the first instruction list, and the output node is a node corresponding to a quantum measurement operation instruction in the first instruction list;

sequentially determining a second directed edge based on the first directed acyclic graph and the first connectable information, and sequentially adding the second directed edge to obtain a second directed acyclic graph, wherein the second directed acyclic graph comprises the second directed edge and the first directed edge, a path formed by the second directed edge and the first directed edge does not comprise a directed loop, each output node in the second directed acyclic graph has no connectable input node, the second directed edge is a candidate directed edge with the largest scoring value in M candidate directed edges which are connectable from the output node to the input node and determined based on the first connectable information, the scoring value is used for representing the maximum value in the number of the candidate directed edges which are connectable from the output node to the input node in a third directed acyclic graph, and M is a positive integer;

And performing equivalent compiling on the first quantum circuit based on the second directed acyclic graph, a first target list formed by the second directed edges and the first instruction list to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit.

According to a second aspect of the present disclosure, there is provided a quantum circuit processing apparatus comprising:

the acquisition module is used for acquiring a first instruction list of the first quantum circuit;

the first determining module is used for determining a first directed acyclic graph based on the first instruction list, wherein the first directed acyclic graph comprises nodes corresponding to instructions in the first instruction list and first directed edges, and the first directed edges are used for representing time sequence relations among different instructions in the first instruction list;

the second determining module is used for determining first connectable information of the first directed acyclic graph, wherein the first connectable information is used for representing the connectivity from an output node to an input node, the input node is a node corresponding to a reset operation instruction in the first instruction list, and the output node is a node corresponding to a quantum measurement operation instruction in the first instruction list;

A third determining module, configured to sequentially determine a second directed edge based on the first directed acyclic graph and the first connectable information, and sequentially add the second directed edge to obtain a second directed acyclic graph, where the second directed acyclic graph includes the second directed edge and the first directed edge, a path formed by the second directed edge and the first directed edge does not include a directed loop, each output node in the second directed acyclic graph has no connectable input node, the second directed edge is a candidate directed edge with a largest scoring value among M candidate directed edges connectable from the output node to the input node determined based on the first connectable information, the scoring value is used to characterize a maximum value among the number of the candidate directed edges connectable from the output node to the input node in a third directed acyclic graph, and M is a positive integer after adding the candidate directed edge in the first directed acyclic graph;

and the equivalent compiling module is used for carrying out equivalent compiling on the first quantum circuit based on the second directed acyclic graph, the first target list formed by the second directed edges and the first instruction list to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit.

According to a third aspect of the present disclosure, there is provided an electronic device comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform any one of the methods of the first aspect.

According to a fourth aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform any of the methods of the first aspect.

According to a fifth aspect of the present disclosure, there is provided a computer program product comprising a computer program which, when executed by a processor, implements any of the methods of the first aspect.

The technology solves the problem that classical simulation and true operation of a quantum circuit are difficult in the related technology, so that the classical simulation and true operation of the quantum circuit with large-scale quantum bits can be realized.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.

Drawings

The drawings are for a better understanding of the present solution and are not to be construed as limiting the present disclosure. Wherein:

fig. 1 is a flow diagram of a quantum circuit processing method according to a first embodiment of the present disclosure;

FIG. 2 is a schematic diagram of an exemplary quantum circuit diagram;

FIG. 3 is a schematic diagram of a first quantum circuit;

FIG. 4 is a schematic structural diagram of a first directed acyclic graph;

FIG. 5 is a flow diagram of a particular example quantum circuit processing method;

fig. 6 is a schematic structural view of a quantum circuit processing apparatus according to a second embodiment of the present disclosure;

fig. 7 is a schematic block diagram of an example electronic device used to implement embodiments of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

First embodiment

As shown in fig. 1, the present disclosure provides a quantum circuit processing method, including the steps of:

step S101: a first instruction list of a first quantum circuit is obtained.

In this embodiment, the quantum circuit processing method relates to the technical field of quantum computing, in particular to the technical field of quantum circuits, and can be widely applied to classical simulation and true operation scenes of quantum circuits. The quantum circuit processing method of the embodiment of the present disclosure may be performed by the quantum circuit processing apparatus of the embodiment of the present disclosure. The quantum circuit processing apparatus of the embodiments of the present disclosure may be configured in any electronic device to perform the quantum circuit processing method of the embodiments of the present disclosure.

The existing quantum circuit simulation mode can support an algorithm for simulating tens of quantum bits at most under the limitation of the memory and the processor capacity of a computer. For example, notebooks can simulate around 20-30 qubits, and large supercomputers and clusters can simulate up to around 30-40 qubits. On the true machine operation, the problem of scalability of the current quantum chip is not solved, so that the number of quantum bits which can be provided by a quantum computer is very limited. Quantum circuit optimization is therefore a fundamental problem in the field of quantum computing.

The quantum circuit optimization is realized by a certain technical means, and a given quantum circuit can be simplified to reduce the requirements of classical simulation and true operation of the quantum circuit, so that the research of a quantum algorithm and the landing of quantum calculation in an actual scene are accelerated.

The quantum circuit processing in this embodiment may be quantum circuit optimization processing, and the purpose of the quantum circuit processing in this embodiment is to make the quantum circuit obtained by compiling perform optimization compilation on the quantum circuit greatly simplify the original quantum circuit in terms of the number of quantum bits. On one hand, the scale of the classical simulation of the quantum algorithm can be further improved, the verification capability of a classical computer on the quantum algorithm is enhanced, on the other hand, the bit number requirement of the quantum algorithm on the true machine operation can be reduced, and the defect of expandability of the current quantum chip is overcome.

More specifically, the purpose of this embodiment is to equivalently compile a given quantum circuit into a dynamic quantum circuit, so as to reduce the number of qubits of the quantum circuit and reduce the requirements of classical simulation and true operation thereof.

Among other things, dynamic quantum circuits are able to integrate classical communication and computation into quantum circuits by introducing intermediate circuit measurements of the quantum bits and the ability to reset the quantum bits to their ground state in computation. This feature will greatly increase the diversity of circuits running on quantum hardware and is also critical to the development of error correction and fault tolerant quantum computing. Therefore, dynamic quantum circuits are expected to become an important component of many quantum applications in the future. In a mathematical sense and without experimental constraints, the static and dynamic quantum circuits have the same computational power, i.e. any problem that can be represented by a dynamic quantum circuit can also be represented as a static problem, so a dynamic quantum circuit offers the possibility to trade-off the depth and width of the circuit.

The quantum circuit model is described in detail below.

Quantum circuit models are one type of commonly used quantum computing model. And (3) completing the evolution of the quantum state by carrying out quantum gate operation on the initial quantum state, and extracting a calculation result by quantum measurement. The quantum circuit diagram shows the whole process of quantum circuit model calculation.

Fig. 2 is a schematic diagram of an exemplary quantum circuit diagram, and as shown in fig. 2, a qubit system may be represented by a horizontal line, where qubits are numbered sequentially from top to bottom, where the qubits are often numbered beginning with zero.

The time evolution direction in the quantum circuit diagram is from left to right, the leftmost end is an initial quantum state, wherein each quantum bit is initialized to be a zero state, and then different quantum gate operations are sequentially applied to the initial state to complete the evolution of the quantum state. Meanwhile, quantum measurement can be carried out on some qubits, and measurement results are obtained.

In some application scenarios, an operation in a quantum circuit may occur to perform quantum measurement on a part of the qubits, and regulate the evolution of the rest of the qubits according to the measurement result, and such an operation is called classical control quantum operation, such as classical control quantum gate 201 shown in fig. 2. The measured qubit may be reset, which may be referred to as a reset operation, such as reset operation 202 shown in FIG. 2, for continued use in subsequent computations. A quantum circuit comprising intermediate measurement, classical control quantum operations, and reset operations may be referred to as a dynamic quantum circuit, e.g. the quantum circuit shown in fig. 2 is a dynamic quantum circuit.

The remainder of the quantum circuit diagram, except for the initial state, may be generally represented by an ordered list of instructions in the order of action of the quantum gates, each element in the list representing a quantum gate, classical control quantum gate, quantum measurement or reset operation instruction. Specifically, it is possible to combine:

each single qubit gate (e.g., H, X, Y, Z, S, T, rx, ry, rz, etc.) is represented as an instruction containing four elements [ name, while_qubit, parameters, condition ]. Where name is the name of the quantum gate, while_qubit is the qubit that the quantum gate acts on, parameters are parameters of the quantum gate (no if there is no parameter), and condition indicates which of the qubits the quantum gate operation is controlled by (no if there is no parameter).

For example, [ Rx,2, pi, none ] represents acting an Rx rotation gate on the qubit on qubit 2, with a rotation angle pi. For another example, classical control quantum gate 201 in fig. 2 is a classical controlled quantum X gate, which may be denoted as [ X,2, none, 'a' ], i.e. the bery Pauli X gate acting on qubit 2, with the controlled condition that the measurement result with measurement identity ID 'a' acts as a quantum gate if the measurement result is 0 and not as a quantum gate if the measurement result is 1.

Each two-qubit gate (e.g., control not gate CNOT, CZ gate) is represented as an instruction containing four elements [ name, white_qubit, parameters, condition ]. Where name is the name of the quantum gate, while_qubit is a list of qubits that the two-qubit gate acts on (in particular, for a controlled quantum gate, a list of control bits and controlled bits), parameters is the parameter of the quantum gate (default to None if there is no parameter), and the condition indicates which quantum bit the quantum gate operation is controlled by (default to None if there is no parameter).

For example, [ CNOT, [1,3], none ] represents a control NOT acting on qubit 1 and qubit 3, where qubit 1 is the control bit and qubit 3 is the control bit. [ CZ, [1,2], none ] indicates that a CZ gate acts between qubit 1 and qubit 2.

Each single bit measurement is represented as an instruction containing four elements [ measure, white_qubit, basic, mid ]. The basic is determined by four parameters, including the measurement angle, the measurement plane, the field set s, the field set t, and mid is the identification ID identifying the current measurement.

For example, [ measure,2, [0, 'YZ', [1], [2] ], and 'a' ] indicate that the qubit 2 is measured, the measurement angle is 0, the measurement plane is the 'YZ' plane, the field set s is the qubit 1, the field set t is the qubit 2, and the identification ID of the current measurement instruction is 'a'.

Each reset operation instruction may be represented as an instruction containing four elements [ reset, while_qubit, matrix, none ]. The while_qubit is a quantum bit to be reset, the matrix is a quantum state matrix of the bit to be reset, and the quantum bit after the reset operation can be used for subsequent calculation.

In step S101, the first quantum circuit may be a dynamic quantum circuit, and the order of the quantum gates in the first quantum circuit is represented by an ordered instruction list, which is a first instruction list, where an operation instruction of the first quantum circuit may be included, and each element in the first instruction list represents a quantum gate, a classical control quantum gate, a quantum measurement or a reset operation instruction.

The first instruction list of the first quantum circuit stored in advance may be acquired, or the first instruction list of the first quantum circuit input by the user may be acquired, which is not particularly limited herein.

In addition, the first quantum circuit may be obtained based on an instruction list of a static quantum circuit (i.e., an original quantum circuit before quantum circuit optimization), and a reset operation instruction of each quantum bit is added in front of the instruction list of the static quantum circuit, so that a first instruction list of the first quantum circuit may be obtained. Wherein the static quantum circuit only comprises a quantum measurement operation and a quantum gate operation, and the quantum measurement operation is positioned after the quantum gate operation.

Step S102: and determining a first directed acyclic graph based on the first instruction list, wherein the first directed acyclic graph comprises nodes corresponding to instructions in the first instruction list and first directed edges, and the first directed edges are used for representing time sequence relations among different instructions in the first instruction list.

Wherein the path formed by the first directed edge does not include a directed loop. The first directed acyclic graph may include at least two first directed edges, and a path formed by the at least two first directed edges does not include a directed loop.

In this step, the first directed acyclic graph may include nodes and a first directed edge formed by the nodes, where each node represents one circuit instruction in the first quantum circuit, and the node identifier may be an instruction in the first instruction list or an identifier corresponding to an instruction in the first instruction list, which is not specifically limited herein.

The first directed edge refers to an edge with a direction (i.e., directionality) that indicates a timing relationship between different instructions in the first instruction list, e.g., an edge of node a that points to node B indicates that the corresponding instruction of node a needs to be executed before the corresponding instruction of node B.

In the first directed acyclic graph, any path formed by each first directed edge is not a directed loop, and the directed loop refers to a loop with directivity, such as a node a, a node B and a node C, and if the node a points to the node B, the node B points to the node C, and then the node C points to the node a, the node B and the node C form a directed loop.

Because the timing relationship of the instructions in the quantum circuit may be embodied based on the arrangement order of the instructions in the instruction list of the quantum circuit, the first directed acyclic graph may be constructed based on the arrangement order of the instructions in the first instruction list of the first quantum circuit.

In an alternative embodiment, a corresponding number of nodes may be constructed based on the number of instructions in the first instruction list, and a timing relationship between the instructions may be determined based on the order of the instructions in the first instruction list, and based on the timing relationship, directed edges may be connected between the constructed nodes, so that the first directed acyclic graph may be obtained.

In another alternative embodiment, the loop traversal of the instructions in the first instruction list may be performed, for the currently traversed instruction, other instructions having a timing relationship with the currently traversed instruction are searched before the currently traversed instruction, the node having the timing relationship is correspondingly constructed, a directed edge is constructed and added to the graph, and the first directed acyclic graph may be obtained under the condition that the loop traversal is completed.

For example, a first quantum circuit is shown in FIG. 3, where "H" represents an H gate, ". CNOT-X" represents a CNOT gate, and MEAS represents a measurement operation. Correspondingly, the first instruction list is [ reset,0, [ [1], [0] ], none ]; [ reset,1, [ [1], [0] ], none ]; [ reset,2, [ [1], [0] ], none ]; [ reset,3, [ [1], [0] ], none ]; [ H,0, none ]; [ H,1, none ]; [ H,2, none ]; [ H,3, none ]; [ CNOT, [0,2], none ]; [ CNOT, [1,0], none ]; [ CNOT, [3,2], none ]; [ measure,0, [0, 'YZ', [ (], [ ] ], (0, 1) ]; [ measure,1, [0, 'YZ', [ (], [ ] ], (1, 1) ]; [ measure,2, [0, 'YZ', [ (], [ ] ], (2, 1) ]; [ measure,3, [0, 'YZ', [ (] ], [ ] ], (3, 1) ].

Each instruction may be assigned an ID, in turn 0,1, …,14, and a first directed acyclic graph may be determined as shown in fig. 4. The number on each node is the ID of the corresponding instruction, the node 401 may be an input node, also referred to as a root node, the node 402 may be an output node, also referred to as an end node.

Step S103: and determining first connectable information of the first directed acyclic graph, wherein the first connectable information is used for representing the connectivity from an output node to an input node, the input node is a node corresponding to a reset operation instruction in the first instruction list, and the output node is a node corresponding to a quantum measurement operation instruction in the first instruction list.

Specifically, the first connectable information of the first directed acyclic graph may be determined based on the first directed acyclic graph, an input node list and an output node list, where the first connectable information is used to characterize the connectivity between each output node in the output node list and each input node in the input node list, the input node list includes all nodes corresponding to the reset operation instruction in the first instruction list, and the output node list includes all nodes corresponding to the quantum measurement operation instruction in the first instruction list.

Since the directed loop cannot be included in the directed acyclic graph (the direction of the directed edge in the graph indicates the timing relationship of the instruction, the ring structure will destroy the relationship), and the graph obtained after connecting the output node to the input node cannot also include the directed ring graph, the connectivity to the output node to the input node can be determined by whether the directed ring graph is included in the graph constructed after connecting the output node to the input node. I.e. connectivity may include two types, the first being: if the graph constructed after connecting the output node to the input node includes a directed ring graph, the output node to the input node may not be connected, and may be represented by a first target value, e.g., the first target value may be 0; the second is: if the graph constructed after connecting the output node to the input node does not include a directed ring graph, the output node may be connected to the input node, and may be represented by a second target value, e.g., the second target value may be 1.

The first connectable information may be represented by a two-dimensional matrix or by other information structures, such as data objects, which are not particularly limited herein.

For example, if the number of input nodes in the first directed acyclic graph is 4 and the number of output nodes in the first directed acyclic graph is 4, the first connectable information of the first directed acyclic graph may be represented by a 4×4 two-dimensional matrix, and each element in the matrix may represent connectivity from an output node to an input node. The row label of the two-dimensional matrix represents the identification of the input node, the column label represents the identification of the output node, and the corresponding element can represent the connectivity of the output node and the input node, namely whether a directed edge can be added between the output node and the input node corresponding to the coordinates.

For example, the elements in the second column of the first row in the matrix may represent the connectivity of the second output node (i.e., the node corresponding to the second quantum measurement operation instruction) to the first input node (i.e., the node corresponding to the first reset operation instruction) in the first directed acyclic graph, where the element value is 1 may represent that the output node is connectable to the input node, and where the element value is 0 may represent that the output node is not connectable to the input node.

The output node to input node connectivity is opposite to the input node to output node reachability indication, i.e. if the input node to output node is reachable, it means that there is a directed path between the input node and the output node, if the output node is connected to the input node, a directed loop will correspondingly occur in the graph, in which case the output node to the input node is not connectable. If the input node is not reachable to the output node, it means that there is no directional path between the input node and the output node, and if the output node is connected to the input node, the input node and the output node do not form a directional loop, in which case the output node is connectable to the input node. Thus, in an alternative embodiment, the first connectivity information of the first directed acyclic graph may be determined by obtaining reachability information of the first directed acyclic graph, based on the reachability information. The reachability information is used for representing reachability from each input node to the output node in the input node list aiming at each output node in the output node list, and the reachability indicates whether a path reaching the output node exists in the input node.

In another alternative embodiment, the connectivity of the output node to the input node may be determined by determining whether the resulting graph includes a directed ring graph after the output node and the input node are connected by simulation, so as to obtain the first connectable information.

Step S104: and sequentially determining a second directed edge based on the first directed acyclic graph and the first connectable information, and sequentially adding the second directed edge to obtain a second directed acyclic graph, wherein the second directed acyclic graph comprises the second directed edge and the at least two first directed edges, a path formed by the second directed edge and the at least two first directed edges does not comprise a directed loop, each output node in the second directed acyclic graph has no connectable input node, the second directed edge is a candidate directed edge with the largest scoring value among M candidate directed edges which are connectable from the output node to the input node and determined based on the first connectable information, the scoring value is used for representing the maximum value in the number of the directed edges which are connectable from the output node to the input node in a third directed acyclic graph, and the third directed acyclic graph is obtained after adding the candidate directed edges in the first directed acyclic graph.

Wherein M is a positive integer. M is used to characterize the total number of candidate directed edges before each determination of the second directed edge.

In this step, the problem of optimizing the quantum circuits can be translated into a solution to an equivalent graph-theory optimization problem, since one quantum circuit is compiled into another quantum circuit, essentially by resetting the measured qubits for use by subsequent instructions. Corresponding to the first directed acyclic graph, the directed edges pointing from the output node to the input node need to be added to the graph as much as possible, i.e. the second directed edges need to be added to the first directed acyclic graph as much as possible, so as to indicate that the measured bit reset is reused, and accordingly, the number of required qubits in the quantum circuit can be reduced.

In order to ensure the equivalence of the compiled quantum circuit and the original quantum circuit and to ensure the time sequence relation between instructions in the quantum circuit, the following constraint conditions need to be ensured when adding the output node to the directed edge of the input node:

1) In order to make the whole graph still conform to the time sequence relation of the circuit instruction, it needs to be ensured that the whole graph is still loop-free after adding more directed edges, and it needs to be noted that the direction of the directed edges in the graph represents the time sequence relation of the instruction, and the loop structure will break the relation, that is, after adding the directed edges, a path (called a directed loop) of the loop structure still cannot exist in the graph;

2) Each output node can only be connected with one input node at most, so that after the output node measures, the pointed input node continues to execute operation on the qubit;

3) Different output nodes cannot be connected to the same input node.

Accordingly, after adding a second directed edge meeting the above constraint in the first directed acyclic graph, a second directed acyclic graph can be obtained.

For the first directed acyclic graph, the second directed edges may be sequentially determined based on the first connectable information and sequentially added. In an alternative embodiment, the second directed edge may be determined from the M candidate directed edges determined by the first connectable information, and after the second directed edge is added to the first directed acyclic graph, the second directed edge may be determined from the candidate directed edges determined by the connectable information of the obtained directed acyclic graph, and the determined second directed edge may be continuously added to the graph. And determining a second directed edge from candidate directed edges which can be connected from output nodes to input nodes in the directed acyclic graph by taking the directed acyclic graph after adding the second directed edge as a starting point, and adding the second directed edge to the directed acyclic graph to obtain a new directed acyclic graph until the output nodes in the obtained directed acyclic graph have no connectable input nodes, thereby obtaining the second directed acyclic graph.

In another alternative embodiment, a second directed edge may be determined from the M candidate directed edges determined by the first connectable information, the first connectable information is updated after adding the second directed edge, and the affected candidate directed edge is determined to be affected after adding the second directed edge, which is not subsequently available for continued addition in the graph. And then, determining a second directed edge again from the remaining candidate directed edges in the M candidate directed edges based on the updated connectable information until the updated connectable information indicates that the output nodes in the obtained directed acyclic graph have no connectable input nodes.

In an alternative embodiment, in each determination of the second directed edge, the second directed edge may be determined from candidate directed edges that are connectable from the output node to the input node in the new directed acyclic graph (i.e., the directed acyclic graph obtained by adding the last determined second directed edge), that is, each time the second directed edge is determined, the number of candidate directed edges may be different, that is, M may be different.

That is, when the second directed edge is determined for the first time, the first directed acyclic graph is taken as a starting point, M candidate directed edges in the first directed acyclic graph are directly determined based on the first connectable information, a new directed acyclic graph can be obtained after the determined second directed edge is added, the corresponding first connectable information is updated, and on the basis of the new directed acyclic graph, the number of candidate directed edges (i.e., candidate directed edges determined based on the updated first connectable information) indirectly determined based on the first connectable information is reduced.

However, each time the second directed edge is determined, the rule is the same, and the candidate directed edge with the largest grading value is selected from the candidate directed edges to serve as the second directed edge, wherein the grading value is used for representing the maximum value in the number of the directed edges, which can be connected from the output node to the input node, in the third directed acyclic graph obtained after the candidate directed edge is added in the first directed acyclic graph. That is, the scoring criterion of the candidate directed edges is that after the candidate directed edges are connected, the theoretical maximum value of the number of the directed edges from the output node to the input node which can be connected is remained in the obtained directed acyclic graph, and the candidate directed edges with the highest scoring value are preferentially connected, so that a larger space exists for adding the subsequent second directed edges, so that the second directed edges newly added in the whole are as much as possible, and further, a compiling circuit close to the minimum quantum bit can be found under the condition of reduced time complexity.

In an alternative embodiment, the candidate directed edges may be scored based on the connectivity of the directed acyclic graph and the transitive nature of the directed edges, with the candidate directed edge having the highest scoring value being selected as the second directed edge added by the round.

The transfer property of the directed edge refers to that if the intermediate node is connected to another node, the other nodes connected to the intermediate node are all connected with the node in a directed way, the intermediate node is also connected with the other nodes connected with the node, and the other nodes connected to the intermediate node are also connected with the other nodes connected with the node.

For example, for the intermediate node B, the directional edge connecting the node B to the node C, according to the nature of the directional edge, other nodes (such as node a, node D, etc.) connected to the node B may be connected to the node C in a directional manner, and other nodes (such as node E) connected to the node B and the node C may also be connected in a directional manner, and further, other nodes (such as node a, node D, etc.) connected to the node B may be connected to other nodes (such as node E) connected to the node C.

In practical application, after each candidate directed edge is simulated to connect with the directed edge, nodes and directed paths in the directed acyclic graph, which are affected by connecting with the candidate directed edge, can be determined according to the transfer property of the directed edge, and the connectable information of the directed acyclic graph is updated according to the connectivity from the output node to the input node in the directed acyclic graph, so as to obtain the connectable information of the directed acyclic graph, which is obtained by simulating to connect with the candidate directed edge. For example, for a candidate directed edge from node B to node C, after the candidate directed edge is connected in the directed acyclic graph, a path exists between the input node a and the output node E according to the transfer property of the directed edge, and correspondingly, if the node E to the node a in the directed acyclic graph are connectable, the connectable information is updated correspondingly, so that after the candidate directed edge is added, the connectable information can indicate that the node E to the node a are not connectable.

A theoretical maximum in the number of directed edges that remain addable output nodes to input nodes in the directed acyclic graph after adding candidate directed edges may then be determined based on the updated connectible information.

In another alternative embodiment, after each candidate directed edge is simulated to be added, the directed edge from the output node to the input node is traversed, after all connection schemes are adopted, the number of the directed edges, which can be added, from the output node to the input node and remain in the directed acyclic graph after the candidate directed edge is added under each connection scheme is determined, and the maximum value in the number of the remaining available directed edges is selected to determine the grading value of the candidate directed edge.

Step S105: and performing equivalent compiling on the first quantum circuit based on the second directed acyclic graph, a first target list formed by the second directed edges and the first instruction list to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit.

In this step, after adding the output node to the directed edge of the input node, the timing relation between the nodes may be determined based on the second directed acyclic graph, and the first instruction list may be reordered based on the timing relation, then, the relation between the input node and the output node in the first target list may be used to equivalently compile the instruction that acts on other qubits (that is, the qubit acted on by the instruction corresponding to the input node that is connected with the output node in a directed manner) after the measurement instruction into the qubit acted on by the measurement instruction, so that equivalent compiling of the first quantum circuit may be implemented, and a second instruction list of the second quantum circuit equivalent to the first quantum circuit may be obtained, where the required qubit in the second quantum circuit is less than that in the first quantum circuit.

In this embodiment, the measurement bit reset is reused by translating the quantum circuit compilation into a directed acyclic graph and by adding the directed edges of the output node to the input node in the directed acyclic graph. And then, based on a directed acyclic graph added with directed edges from the output node to the input node, performing equivalent compiling on the first quantum circuit to obtain a second quantum circuit, so that the number of quantum bits required in the quantum circuit obtained by equivalent compiling can be effectively reduced, the optimization of the quantum circuit is realized, and classical simulation and true operation of the quantum circuit with large-scale quantum bits can be realized.

And the circuit is compiled and converted into the directed acyclic graph, and the scores of all candidate directed edges are calculated through a heuristic algorithm (wherein the score criterion of the candidate directed edges is the theoretical maximum value of the number of the directed edges from the connectable output node to the input node remained in the graph after the candidate directed edges are connected), and the candidate directed edges with the highest score value are preferentially connected, so that a larger space exists for adding the subsequent second directed edges, the second directed edges newly added in the whole are as much as possible, and further the compiling circuit which is close to the minimum quantum bit can be found under the condition of reduced time complexity.

Optionally, the determining, based on the first directed acyclic graph and the first connectable information, a second directed edge sequentially, and adding the second directed edge sequentially, to obtain a second directed acyclic graph, includes:

determining a second directed edge from the M candidate directed edges determined by the first connectable information;

adding one second directed edge in the first directed acyclic graph to obtain a fourth directed acyclic graph;

the second directed acyclic graph is determined based on the fourth directed acyclic graph and second connectable information of the fourth directed acyclic graph.

In this embodiment, the second directed edge may be determined from the M candidate directed edges determined by the first connectable information, and after the second directed edge is added to the first directed acyclic graph, a fourth directed acyclic graph may be obtained.

And determining second connectable information of the fourth directed acyclic graph, wherein the determination mode of the second connectable information is the same as that of the first connectable information, and details are not repeated here.

In the case where the second connectable information characterizes that there is no directional edge in the fourth directed acyclic graph where the output node is connectable to the input node, the fourth directed acyclic graph may be determined to be the second directed acyclic graph. In an alternative embodiment, the connectable information may be represented by a two-dimensional matrix, where an element value of 0 indicates that an output node to an input node in the directed acyclic graph are not connectable, and accordingly, in a case where no non-zero element is present in the two-dimensional matrix, a directed edge where the output node to the input node are connectable in the directed acyclic graph may be represented, and in a case where no non-zero element is present in the two-dimensional matrix, a directed edge where the output node to the input node are connectable in the directed acyclic graph may be represented.

Optionally, the determining the second directed acyclic graph based on the fourth directed acyclic graph and second connectable information of the fourth directed acyclic graph includes:

and under the condition that the second connectable information characterizes that a directional edge capable of connecting an output node to an input node exists in the fourth directional acyclic graph, sequentially determining a second directional edge based on the fourth directional acyclic graph and the second connectable information, and sequentially adding the second directional edge to obtain a second directional acyclic graph.

Specifically, a second directed edge may be determined from the candidate directed edges determined by the second connectable information, and the determined second directed edge may be added to the fourth directed acyclic graph. And the second directed edge is determined from candidate directed edges which are formed by connecting output nodes to input nodes in the fourth directed acyclic graph by taking the fourth directed acyclic graph as a starting point, and the determined second directed edge is added to the fourth directed acyclic graph to obtain a new directed acyclic graph until the output nodes in the obtained directed acyclic graph have no connectable input nodes, so that the second directed acyclic graph can be obtained.

In this embodiment, a second directed edge is determined from the M candidate directed edges determined from the first connectable information; adding the second directed edge to the first directed acyclic graph to obtain a fourth directed acyclic graph; the second directed acyclic graph is determined based on the fourth directed acyclic graph and second connectable information of the fourth directed acyclic graph. In this way, the candidate directed edge with the highest grading value can be preferentially connected, more second directed edges can be found under lower time complexity, and therefore a compiling circuit with the smallest number of quantum bits is found.

Sequentially determining second directed edges, and sequentially adding the second directed edges to circularly update the directed acyclic graph, wherein the specific process is as follows:

input: a connectivity matrix all_candidate;

and (3) outputting: the directed acyclic graph (i.e., the second directed acyclic graph) and the directed edge list edges after adding the second directed edge.

Step 1: for the input connectivity matrix all_candidate;

step 1.1: if the connectivity matrix has non-zero elements, determining a newly added second directed edge from the candidate directed edges determined by the connectivity matrix, adding the newly added second directed edge to the directed edge list new_edges, updating the connectivity matrix all_candidate, and repeating the step 1.1;

step 1.2: if the connectivity matrix is zero element, the cycle is ended;

step 2: and when the updating is finished, adding the directed edge list new_edges to the directed edge list edges of the first directed acyclic graph, and outputting a second directed acyclic graph.

Optionally, the first connectable information is represented by a first matrix, and the determining a second directed edge from M candidate directed edges determined by the first connectable information includes:

updating the first matrix for each candidate directed edge under the condition that the candidate directed edge is simulated to be added in the first directed acyclic graph to obtain a second matrix, wherein the second matrix is used for representing the connectivity from an output node to an input node in the directed acyclic graph obtained after the candidate directed edge is added in the first directed acyclic graph;

Determining a scoring value of the candidate directed edge based on the second matrix;

and determining the candidate directed edge with the largest scoring value among the M candidate directed edges as a second directed edge.

In this embodiment, the first connectable information may be represented by a first matrix, the first matrix may be a two-dimensional matrix, a row label of the first matrix represents a label of an input node, a column label of the first matrix is an identifier of an output node, and the corresponding element may represent connectivity between the output node and the input node.

In an alternative embodiment, an element value of 1 may indicate that the output node is connectable to the input node, and an element value of 0 may indicate that the output node is not connectable to the input node.

For example, the first matrix of the first connectable information may be represented by the following formula (1), and the first matrix is a 4×4 two-dimensional matrix.

Wherein, in the above formula (1), each non-zero element may represent a candidate directed edge from an output node to an input node, wherein, specifically, which output node to which input node is the candidate directed edge is determined by the position (including a row label and a column label) of the non-zero element.

For each candidate directed edge, under the condition that the candidate directed edge is added in the first directed acyclic graph in a simulation mode, nodes and directed paths in the directed acyclic graph, which are affected by connecting the candidate directed edge, can be determined according to the transfer property of the directed edge, and a first matrix is updated according to the connectivity from an output node to an input node in the directed acyclic graph, so that a second matrix is obtained. For example, for a candidate directed edge from node B to node C, after the candidate directed edge is connected in the directed acyclic graph, a path exists between the input node a and the output node E according to the transfer property of the directed edge, and correspondingly, if the node E to the node a in the directed acyclic graph are connectable, the element values in the column label of the node E and the row label position of the node a in the first matrix are updated correspondingly, so that after the candidate directed edge is added, the element values in the second matrix can indicate that the node E to the node a are not connectable.

And then, determining the theoretical maximum value in the number of the directed edges which can be added from the output node to the input node in the directed acyclic graph after adding the candidate directed edges based on the second matrix, and obtaining the grading value of the candidate directed edges.

And determining the candidate directed edge with the largest scoring value among the M candidate directed edges as a second directed edge, so that the determination of the second directed edge can be simply realized.

Optionally, each element in the first matrix is used to characterize connectivity from an output node to an input node in the first directed acyclic graph, and updating the first matrix to obtain a second matrix includes:

updating the element values corresponding to the candidate directed edges in the first matrix to a first target value;

updating each element value in the row of the candidate directed edge corresponding element in the first matrix to the first target value, and updating each element value in the column of the candidate directed edge corresponding element in the first matrix to the first target value;

updating the element values of the positions determined by the target row coordinates and the target column coordinates in the first matrix to be the first target value, wherein the target row coordinates are row coordinates, in which the element values in the columns of the candidate directed edge corresponding elements are the first target value, and the target column coordinates are column coordinates, in which the element values in the rows of the candidate directed edge corresponding elements are the first target value;

Wherein the first target value is used to characterize that output nodes are not connectable to input nodes in the directed acyclic graph.

In this embodiment, the first target value may be 0.

After the first matrix is obtained, for non-zero elements (u, v) in the first matrix, the non-zero elements represent candidate directed edges from node v to node u, according to the transitivity of the directed edges, the terminal nodes and the root nodes which are connected with the u, v nodes and have paths form paths in pairs after the directed edges (u, v) are connected, so that column coordinates { y_1, y_2, } and row coordinates { x_1, x_2, }, corresponding to all zero elements in the u th row and the v th column (i.e. the terminal nodes and the root nodes which are connected with the u, v nodes and have paths) can be found, and all elements in the u th row and the v th column are marked as zero.

Corresponding to the first matrix shown in equation (1) above, traversing the first connectable candidate directed edge as the (1, 2) element in the connectable matrix may copy the connectable matrix as all_candidate_copy. Next, all elements of 0 in the 1 st row and the 2 nd column of the connectable matrix are traversed to obtain column coordinates {1,3} and row coordinates {2}, element values of (2, 1) and (2, 3) positions are marked as 0 in the matrix all_candidate_copy, and all elements of the 1 st row and the 2 nd column are marked as 0, so that a second matrix of candidate directed edges for the (1, 2) element positions is obtained, which is represented by the following formula (2).

Thus, the connectable matrix, i.e. the second matrix, after connecting the candidate directed edges (u, v) can be determined simply.

Optionally, the determining, based on the second matrix, a scoring value of the candidate directed edge includes:

acquiring the number of rows and the number of columns, wherein the element values of the columns are second target values, in the second matrix;

and determining the grading value of the candidate directed edge based on the number of rows and the number of columns.

In this embodiment, the second target value may be a non-zero element, for example, may be 1.

The theoretical maximum of the number of directed edges in the directed acyclic graph that output nodes can connect to input nodes can be determined by the number of rows and columns of non-zero elements present in the second matrix, the number of rows can represent the number r of input nodes (i.e., root nodes) that still have candidate directed edges, and the number of columns can represent the number t of output nodes (i.e., end nodes) that still have candidate directed edges.

And determining the grading value of the candidate directed edge based on the number of rows and the number of columns. In an alternative embodiment, the scoring value of the candidate directed edge may be determined by a preset function formula based on the number of rows and the number of columns.

In another alternative embodiment, since the smaller value min (r, t) of the root node number r and the terminal node number t is the theoretical maximum value of the number of connectable directed edges in the directed acyclic graph after the connection (u, v), the scoring value of the candidate directed edge may be determined based on the small one of the row number and the column number. For example, the small one of the number of rows and the number of columns may be directly determined as the score value of the candidate directed edge.

Since the small one of the number of rows and the number of columns may be equal to 0, the score value of the candidate directed edge may conflict with the score value (score of 0) of the non-candidate directed edge. Optionally, the determining the scoring value of the candidate directed edge based on the number of rows and the number of columns includes:

a third target value is determined as the score value of the candidate directed edge, the third target value being the sum of 1 and the small one of the number of rows and the number of columns.

Therefore, when calculating the score value of the candidate directed edge (u, v), the score value of min (r, t) +1 may be determined so that when min (r, t) =0, the score value of the candidate directed edge (score value of 1) and the score value of the non-candidate directed edge (score value of 0) may be distinguished.

For example, for the second matrix shown in the above formula (2), the number r of root nodes where candidate directed edges (i.e., non-zero elements) still exist in the directed acyclic graph may be obtained as 3, and the number t of terminal nodes as 2, so that the scoring value of the (1, 2) candidate directed edges in the connectable matrix may be 3.

According to the scoring standard, the scoring values of all candidate directed edges in the connectable matrix can be counted into the scoring matrix with the same size, the candidate directed edge with the highest scoring value in the scoring matrix is selected, and the candidate directed edge is used as a second directed edge determined and added by the round, namely, after the second directed edge is connected as much as possible, the existence of the remaining connectable directed edges is ensured as much as possible.

In an alternative embodiment, the specific procedure for determining the second directed edge is as follows:

input: a directed acyclic graph, input node list input, output node list output, connectivity matrix all_candidate;

and (3) outputting: the newly added second directed edge and the connectivity matrix all_bridge after the addition of the second directed edge.

Step 1: initializing a blank matrix edge_score, wherein the number of rows and the number of columns of the blank matrix edge_score are equal to the number of rows and the number of columns of a connectivity matrix all_candidate respectively;

step 2: traversing non-zero elements (u, v) in the connectivity matrix all_candidate;

step 2.1: initializing a variable score, and copying an all_candidate matrix, which is marked as all_candidate_copy;

step 2.2: traversing all elements in the u-th row in the all_candidate matrix, and finding out column coordinates { y_1, y_2, & gt, y_j, & gt, corresponding to all elements with element values of 0; traversing all elements in the v-th column in the all_candidate matrix, and finding out row coordinates { x_1, x_2, & gt, x_i, & gt, corresponding to all elements with element values of 0;

step 2.3: all { (x_i, y_j) } elements in the matrix all_candidate_copy are marked as 0;

step 2.4: all elements of the u-th row and v-th column in the matrix all_filtered_copy are marked as 0;

Step 2.5: calculating the number r of root nodes and the number t of terminal nodes of the candidate directed edges (namely non-zero elements) still existing in the matrix all_candidiat_copy;

step 2.6: score was calculated as min (r, t) +1;

step 2.7: the element value of the (u, v) position in the edge_score matrix is recorded as score;

step 3: selecting the position (m, n) with the maximum element value in the edge_score matrix obtained in the step 2, and correspondingly marking the candidate directed edge pointing to the inputs [ m ] from the node output [ n ] as new_edge as a newly added second directed edge of the round;

step 4: updating the all_filtered matrix added with new_edge by utilizing the step 2;

step 5: the newly added second directed edge is returned and output.

Optionally, the step S102 specifically includes:

traversing the first instruction list according to the instruction arrangement sequence from left to right, and acquiring a second target list and a first qubit acted by the currently traversed instruction, wherein the second target list comprises instructions which are sequenced before the currently traversed instruction in the first instruction list;

traversing the second target list according to the order of the order from right to left, and acquiring a first target order, wherein the quantum bit acted by the first target order and the first quantum bit have an intersection;

Taking the identification of the first target instruction as a source node, taking the identification of the currently traversed instruction as a target node, and constructing the first directed edge;

and acquiring the first directed acyclic graph based on the constructed first directed edge under the condition that the first instruction list traversal is completed.

In this embodiment, the conversion process from the quantum circuit to the first directed acyclic graph is as follows:

input: quantum circuit instruction list circuit_list;

and (3) outputting: the directed acyclic graph (first directed acyclic graph) inputs the node list and outputs the node list.

Step 1: recording as n according to the circuit width represented by the quantum circuit instruction list circuit_list; cycling through lists [0,1, …, n-1], recording currently cycled elements as idx, generating a circuit instruction gate= [ reset, idx, [ [1], [0] ], none ], adding the circuit instruction gate= [ reset, idx, [ [0] ], none ] to the forefront of a circuit_list list, and obtaining an updated circuit_list, thus obtaining a first instruction list;

step 2: cycling through a circle_list, marking the element currently cycled as gate, wherein the gate is positioned at the ith bit of the circle_list, adding an ID attribute for the gate, and the value of the ID is i;

step 3: initializing a directed graph, and initializing two empty lists, namely input_ids and output_ids;

Step 4: the loop traversal list loop_list (i.e. traversed according to the order of instruction from left to right), note that the currently cycled element is gate, and gate is at the ith bit of the loop_list, perform operations a), b) as follows:

operation a) recording that the list of the first i elements in the circuit_list is pre_gates (i.e., the second target list);

operation b) obtaining a qubit (namely a first qubit) acted by a gate instruction, and recording the currently circulated qubit as idx;

operation c) reverse-loop traversing pre_gates (i.e., traversing in order of instruction arrangement from right to left), and noting the currently-circulated element as pre_gate; if the qubit acted on by the pre_gate has an intersection with idx, then the pre_gate is the first target instruction; recording node1 as the identification ID of the pre-gate instruction, node2 as the identification ID of the gate instruction, constructing and adding nodes node1 and node2 into the directed graph, and adding a directed edge pointing from node1 (source node) to node2 (target node); then jumping out of the layer for circulation;

step 5: if gate is a reset instruction, adding the corresponding ID to the last of the input_ids list; if gate is a measurement instruction, adding the corresponding ID to the last of the output_ids list;

Step 6: returning to the directed graph (first directed acyclic graph), the input node list input_ids and the output node list output_ids.

In this embodiment, by performing a loop traversal of an instruction in the first instruction list, for a currently traversed instruction, other instructions having a timing relationship (i.e., two instructions act on the same qubit) are searched before the currently traversed instruction, a node having a timing relationship is correspondingly constructed, and a directed edge is constructed and added to the graph, so that the first directed acyclic graph can be obtained under the condition that the loop traversal is completed. In this way, the construction of the first directed acyclic graph can be simply implemented.

In addition, when the first directed acyclic graph is constructed, only the ID of the corresponding instruction is used, and the circuit instruction is not needed to be used as a node of the graph, so that corresponding operation is reduced as much as possible.

Optionally, the step S103 specifically includes:

the determining the first connectable information of the first directed acyclic graph includes:

determining reachability information of the first directed acyclic graph, wherein the reachability information is used for representing reachability from an input node to an output node in the first directed acyclic graph, and the reachability indicates whether a path reaching the output node exists in the input node;

The first connectable information is determined based on the reachability information.

In this embodiment, the reachability information may be represented by a two-dimensional matrix, where a row label of the two-dimensional matrix represents a label of an input node, a column label represents an identifier of an output node, and the corresponding element represents whether the input node is reachable to the output node, that is, whether a path exists between the input node and the output node, if a path exists, the reachability is achieved, and if no path exists, the reachability is not achieved.

In an alternative embodiment, a value of 1 for an element may indicate that the input node is not reachable to the output node, and a value of 0 for an element may indicate that the input node is reachable to the output node.

The connectable information is opposite to the indication of the reachability information, and for the elements of the same row label and list, if the reachability information indicates that the input node is not reachable to the output node, the connectable information indicates that the output node is connectable to the input node, and if the reachability information indicates that the input node is reachable to the output node, the connectable information indicates that the output node is not connectable to the input node.

In an alternative embodiment, a value of 1 for an element may indicate that an output node is connectable to an input node, and a value of 0 for an element may indicate that an output node is not connectable to an input node.

According to constraint 1): in order for the entire directed acyclic graph to still conform to the timing relationship of the circuit instructions, it is necessary to ensure that the entire directed acyclic graph remains acyclic after more directed edges are added. To ensure that constraint 1) is satisfied after adding a directed edge, a depth-first search algorithm (or other effective algorithm) may be used to determine whether each input node to output node in the directed acyclic graph is reachable, thereby avoiding adding a ring structure resulting from adding a directed edge from an output node to an input node, and if an input node is not reachable, marking an output node to an input node as connectable, otherwise not connectable. In this way, the connectible information can be determined based on the reachability information using the indicated opposite of the connectible information to the reachability information, so that the determination of the connectible information of the first directed acyclic graph can be simply achieved.

The specific search procedure for connectivity may be as follows:

input: a directed acyclic graph (which may be a first directed acyclic graph), an input node list input, and an output node list output;

and (3) outputting: the two-dimensional matrix all_candidate contains the connectivity from the output node to the input node, and when the value of an element is 1, the output node can be connected to the input node, and when the value of the element is 0, the output node can not be connected to the input node.

Step 1: for each element in the input node list, a depth-first search (or other efficient algorithm) is used to determine whether it is reachable to each output node in the output node list. Specifically, step 1 comprises step c) and step d):

step c) initializing a two-dimensional matrix all_candidate, wherein the number of rows is equal to the length of an input node list, the number of columns is equal to the length of an output node list, and the initial value of all elements is 1 (when the element value is 1, the input node is not reachable to the output node, namely the output node is connectable to the input node; an element value of 0 indicates that the input node is reachable to the output node, and the output node is not connectable to the input node);

step d) circularly traversing the output node list output, and recording the currently traversed element as output: judging whether each input node in the input nodes has a path reaching the node output in the graph by utilizing depth-first search (or other effective algorithms), if so, recording the input node as an unreachable node of the output node, and marking an element under a corresponding row and column of a two-dimensional matrix all_candidate as 0; otherwise, the element value under the corresponding row and column of the two-dimensional matrix all_candidate is not changed (namely, the element value is kept to be 1);

Step 2: the output matrix all_candidate is a two-dimensional matrix representing reachability information, and the two-dimensional matrix may also represent connectable information.

Optionally, the step S105 specifically includes:

based on the second directed acyclic graph, reordering the instructions in the first instruction list to obtain a third instruction list;

and based on the first target list, performing equivalent compiling on the instructions in the third instruction list to obtain the second instruction list.

In this embodiment, the instructions in the first instruction list of the first quantum circuit may be reordered based on the second directed acyclic graph to obtain a third instruction list. The arrangement order of the instructions in the third instruction list is matched with the topological structure of the nodes in the second directed acyclic graph.

The arrangement order of the instructions in the third instruction list is matched with the topological structure of the nodes in the second directed acyclic graph, which means that if one node A points to the directed edge of the node B in the second directed acyclic graph, the corresponding instructions of the node A in the third instruction list are ordered before the corresponding instructions of the node B.

In an alternative embodiment, the instructions in the first instruction list may be reordered based on the second directed acyclic graph by exchanging the instructions with each other, for example, performing graph traversal, and exchanging two related instructions in the first instruction list according to the traversed nodes and directed edges to match the topology structure of the graph.

In another alternative embodiment, a topology ordered list corresponding to the second directed acyclic graph may be obtained; the instructions in the first instruction list are reordered based on the topologically ordered list.

Then, based on the first target list, the instructions in the third instruction list can be equivalently compiled to obtain a second instruction list. The purpose of equivalent compiling is to re-act the quantum bit acted by the instruction corresponding to the input node on the re-utilized quantum bit after the measurement of the output node, so that the quantum bit number of the compiled quantum circuit can be reduced, and the optimization of the quantum circuit is realized.

Optionally, the reordering the instructions in the first instruction list based on the second directed acyclic graph to obtain a third instruction list includes:

obtaining a topological ordering list corresponding to the second directed acyclic graph, wherein in the topological ordering list, for each directed edge in the second directed acyclic graph, the source node of the directed edge is ordered before the target node of the directed edge;

and reordering the instructions in the first instruction list based on the topological ordering list to obtain the third instruction list.

In this embodiment, the topology ordered list refers to a list that characterizes the topology of the second directed acyclic graph, for example, if there is a directed edge of a node a pointing to a node B, then the node a will be ranked in front of the node B in the topology ordered list. The topologically ordered list may be obtained by traversing the second directed acyclic graph.

Then, the instructions in the first instruction list may be reordered based on the topology ordering list, for example, an empty instruction list may be initialized, the topology ordering list may be traversed, and according to the arrangement sequence of the topology ordering list, the instructions corresponding to the nodes in the topology ordering list in the first instruction list are arranged to the instruction list, so as to obtain a third instruction list.

In this way, reordering of the first instruction list may be achieved.

Optionally, the equivalently compiling the instructions in the third instruction list based on the first target list to obtain the second instruction list includes:

and updating second qubits acted by second target instructions in the third instruction list into third qubits aiming at each second directed edge in the first target list, wherein the second qubits are qubits acted by target nodes in the second directed edge corresponding to instructions, and the third qubits are qubits acted by source nodes in the second directed edge corresponding to the instructions.

In this embodiment, in the second directed edge, the source node refers to the output node, and the target node refers to the input node. The quantum bit acted by the instruction corresponding to the input node (namely, the second quantum bit corresponds to the quantum bit) can be acted on the reset quantum bit (namely, the third quantum bit corresponds to the quantum bit) after the measurement of the output node again, so that the quantum bit number of the quantum circuit obtained by compiling can be reduced, and the optimization of the quantum circuit is realized.

The equivalent compilation process of the second directed acyclic graph to the quantum circuit is as follows:

input: quantum circuit instruction list circuit_list (i.e., first instruction list), directed acyclic graph (i.e., second directed acyclic graph), directed edge list edges (i.e., first target list);

and (3) outputting: a compiled list of quantum circuit instructions (i.e., a second list of instructions).

Step 1: obtaining a corresponding topological sorting list according to the directed acyclic graph, and marking the topological sorting list as a scaled_gate_ids;

step 2: sequencing a quantum circuit instruction list circuit_list according to the sequence of the scaled_gate_ids;

step 3: traversing the directed edge list edge circularly, recording the element which is currently circulated as edge, recording the quantum bit acted by the circuit instruction corresponding to the source node of the edge as new_idx, and recording the quantum bit acted by the circuit instruction corresponding to the target node of the edge as old_idx; looping through the circuit_list, and rewriting all instructions acting on the quantum bit old_idx into instructions acting on new_idx;

Step 4: and returning the updated quantum circuit instruction list circuit_list as output.

Fig. 5 is a flowchart of a quantum circuit processing method of a specific example, and for a quantum circuit, the detailed procedure of the quantum circuit processing method of the present embodiment is as follows:

input: quantum circuit instruction list circuit_list (i.e., first instruction list);

and (3) outputting: a compiled list of dynamic quantum circuit instructions (i.e., a second list of instructions).

Step 1: acquiring a first quantum circuit;

step 2: taking a circuit_list as input, acquiring a first directed acyclic graph, inputting a node list input, and outputting a node list output;

step 3: taking graphs, inputs and outputs as inputs, and obtaining a connectivity matrix all_candidate (namely a first matrix);

step 4: taking a directed acyclic graph, and taking a connectivity matrix all_candidate as an input to score candidate directed edges;

step 5: selecting the candidate directed edge with the highest scoring as a second directed edge, adding the second directed edge to the directed edge list edge, adding the second directed edge to the directed acyclic graph, and updating the connectivity matrix all_candidate; returning to the step 4 to circularly update the directed acyclic graph until the second directed edge cannot be added continuously under the condition that the connectibility matrix all_candidate indicates that the connectible directed edge exists, so as to obtain a new directed acyclic graph;

Step 6: and under the condition that the connectivity matrix all_candidate indicates that no connectable directed edges exist, taking a circuit_list, a new_graph and edges as inputs, and acquiring a second instruction list of the compiled dynamic quantum circuit as output.

Second embodiment

As shown in fig. 6, the present disclosure provides a quantum circuit processing apparatus 600, comprising:

an obtaining module 601, configured to obtain a first instruction list of a first quantum circuit;

a first determining module 602, configured to determine, based on the first instruction list, a first directed acyclic graph, where the first directed acyclic graph includes a node corresponding to an instruction in the first instruction list and at least two first directed edges, and the first directed edges are used to characterize a timing relationship between different instructions in the first instruction list;

a second determining module 603, configured to determine first connectable information of the first directed acyclic graph, where the first connectable information is used to characterize a connectivity from an output node to an input node, the input node is a node corresponding to a reset operation instruction in the first instruction list, and the output node is a node corresponding to a quantum measurement operation instruction in the first instruction list;

A third determining module 604, configured to sequentially determine a second directed edge based on the first directed acyclic graph and the first connectable information, and sequentially add the second directed edge to obtain a second directed acyclic graph, where the second directed acyclic graph includes the second directed edge and the first directed edge, a path formed by the second directed edge and the first directed edge does not include a directed loop, each output node in the second directed acyclic graph has no connectable input node, the second directed edge is a candidate directed edge with a largest scoring value among M candidate directed edges that are connectable from the output node to the input node and determined based on the first connectable information, and the scoring value is used to characterize a maximum value among the number of the candidate directed edges that are connectable from the output node to the input node in a third directed acyclic graph, where M is a positive integer after adding the candidate directed edge in the first directed acyclic graph;

and the equivalent compiling module 605 is configured to perform equivalent compiling on the first quantum circuit based on the second directed acyclic graph, the first target list formed by the second directed edges, and the first instruction list, so as to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit.

Optionally, the third determining module 604 includes:

a first determining submodule, configured to determine a second directed edge from M candidate directed edges determined by the first connectable information;

the adding submodule is used for adding one second directed edge in the first directed acyclic graph to obtain a fourth directed acyclic graph;

a second determining sub-module for determining the second directed acyclic graph based on the fourth directed acyclic graph and second connectable information of the fourth directed acyclic graph.

Optionally, the first connectable information is represented by a first matrix, and the first determining submodule includes:

the updating unit is used for updating the first matrix to obtain a second matrix aiming at each candidate directed edge under the condition that the candidate directed edge is added in the first directed acyclic graph in an analog mode, and the second matrix is used for representing the connectivity from an output node to an input node in the directed acyclic graph obtained after the candidate directed edge is added in the first directed acyclic graph;

a first determining unit configured to determine a score value of the candidate directed edge based on the second matrix;

and the second determining unit is used for determining the candidate directed edge with the largest scoring value among the M candidate directed edges as a second directed edge.

Optionally, each element in the first matrix is used to characterize connectivity from an output node to an input node in the first directed acyclic graph, and the updating unit is specifically configured to:

Optionally, the first determining unit is specifically configured to:

Optionally, the second determining submodule is specifically configured to:

Optionally, the first determining module 602 is specifically configured to:

Optionally, the second determining module 603 is specifically configured to:

Optionally, the equivalent compiling module 605 includes:

a reordering sub-module, configured to reorder the instructions in the first instruction list based on the second directed acyclic graph, to obtain a third instruction list;

and the equivalent compiling sub-module is used for carrying out equivalent compiling on the instructions in the third instruction list based on the first target list to obtain the second instruction list.

Optionally, the reordering submodule is specifically configured to:

Optionally, the equivalent compiling sub-module is specifically configured to:

The quantum circuit processing apparatus 600 provided in the present disclosure can implement each process implemented by the quantum circuit processing method embodiment, and can achieve the same beneficial effects, so that repetition is avoided, and no further description is provided herein.

In the technical scheme of the disclosure, the related processes of collecting, storing, using, processing, transmitting, providing, disclosing and the like of the personal information of the user accord with the regulations of related laws and regulations, and the public order colloquial is not violated.

According to embodiments of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

FIG. 7 illustrates a schematic block diagram of an example electronic device that may be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 7, the apparatus 700 includes a computing unit 701 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 702 or a computer program loaded from a storage unit 708 into a Random Access Memory (RAM) 703. In the RAM 703, various programs and data required for the operation of the device 700 may also be stored. The computing unit 701, the ROM 702, and the RAM 703 are connected to each other through a bus 704. An input/output (I/O) interface 705 is also connected to bus 704.

Various components in device 700 are connected to I/O interface 705, including: an input unit 706 such as a keyboard, a mouse, etc.; an output unit 707 such as various types of displays, speakers, and the like; a storage unit 708 such as a magnetic disk, an optical disk, or the like; and a communication unit 709 such as a network card, modem, wireless communication transceiver, etc. The communication unit 709 allows the device 700 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.

The computing unit 701 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 701 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 701 performs the various methods and processes described above, such as a quantum circuit processing method. For example, in some embodiments, the quantum circuit processing method may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 708. In some embodiments, part or all of the computer program may be loaded and/or installed onto device 700 via ROM 702 and/or communication unit 709. When a computer program is loaded into RAM 703 and executed by computing unit 701, one or more steps of the quantum circuit processing method described above may be performed. Alternatively, in other embodiments, the computing unit 701 may be configured to perform the quantum circuit processing method by any other suitable means (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.

The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server incorporating a blockchain.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel, sequentially, or in a different order, provided that the desired results of the disclosed aspects are achieved, and are not limited herein.

The above detailed description should not be taken as limiting the scope of the present disclosure. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.

Claims

1. A quantum circuit processing method, comprising:

acquiring a first instruction list of a first quantum circuit;

based on the second directed acyclic graph, a first target list formed by the second directed edges and the first instruction list, performing equivalent compiling on the first quantum circuit to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit;

The performing equivalent compiling on the first quantum circuit based on the first target list formed by the second directed acyclic graph and the second directed edge and the first instruction list to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit, including:

determining a timing relationship between the nodes based on the second directed acyclic graph;

reordering the first instruction list based on the timing relationship;

utilizing the relation between the input node and the output node in the first target list to equivalently compile the command which acts on other quantum bits after the quantum measurement operation command into a quantum bit which acts on the quantum measurement operation command, and obtaining a second command list of a second quantum circuit equivalent to the first quantum circuit; the other quantum bits are the quantum bits acted by the corresponding instruction of the input node which is connected with the output node in a directed way.

2. The method of claim 1, wherein the sequentially determining a second directed edge based on the first directed acyclic graph and the first connectable information and sequentially adding the second directed edge, results in a second directed acyclic graph, comprises:

3. The method of claim 2, wherein the first connectable information is represented by a first matrix, the determining a second directed edge from the M candidate directed edges determined by the first connectable information comprising:

4. A method according to claim 3, wherein each element in the first matrix is used to characterize connectivity of an output node to an input node in the first directed acyclic graph, and the updating the first matrix to obtain the second matrix comprises:

5. A method according to claim 3, wherein the determining a scoring value for the candidate directed edge based on the second matrix comprises:

6. The method of claim 5, wherein the determining a scoring value for the candidate directed edge based on the number of rows and the number of columns comprises:

7. The method of claim 2, wherein the determining the second directed acyclic graph based on the fourth directed acyclic graph and second connectable information of the fourth directed acyclic graph comprises:

8. The method of claim 1, wherein the determining a first directed acyclic graph based on the first list of instructions comprises:

9. The method of claim 1, wherein the determining the first connectable information of the first directed acyclic graph comprises:

10. The method of claim 1, wherein the equivalently compiling the first quantum circuit based on the second directed acyclic graph, the first target list of second directed edges, and the first instruction list to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit, comprises:

11. The method of claim 10, wherein the reordering instructions in the first instruction list based on the second directed acyclic graph to obtain a third instruction list comprises:

12. The method of claim 10, wherein the equivalently compiling the instructions in the third instruction list based on the first target list to obtain the second instruction list includes:

13. A quantum circuit processing apparatus comprising:

The equivalent compiling module is used for carrying out equivalent compiling on the first quantum circuit based on the second directed acyclic graph, the first target list formed by the second directed edges and the first instruction list to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit;

the equivalent compiling module is specifically used for:

reordering the first instruction list based on the timing relationship;

14. The apparatus of claim 13, wherein the third determination module comprises:

15. The apparatus of claim 14, wherein the first connectible information is represented by a first matrix, the first determination submodule comprising:

16. The apparatus of claim 15, wherein each element in the first matrix is configured to characterize connectivity of an output node to an input node in the first directed acyclic graph, and the updating unit is configured to:

17. The apparatus of claim 15, wherein the first determining unit is specifically configured to:

18. The apparatus of claim 17, wherein the first determining unit is specifically configured to:

19. The apparatus of claim 14, wherein the second determination submodule is configured to:

20. The apparatus of claim 13, wherein the first determining module is specifically configured to:

21. The apparatus of claim 13, wherein the second determining module is specifically configured to:

22. The apparatus of claim 13, wherein the equivalent compiling module comprises:

23. The apparatus of claim 22, wherein the reordering sub-module is specifically configured to:

24. The apparatus of claim 22, wherein the equivalent compiling sub-module is specifically configured to:

25. An electronic device, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-12.

26. A non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of any one of claims 1-12.

27. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any of claims 1-12.