CN116187458B  Quantum circuit processing method and device and electronic equipment  Google Patents
Quantum circuit processing method and device and electronic equipment Download PDFInfo
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 CN116187458B CN116187458B CN202310181527.8A CN202310181527A CN116187458B CN 116187458 B CN116187458 B CN 116187458B CN 202310181527 A CN202310181527 A CN 202310181527A CN 116187458 B CN116187458 B CN 116187458B
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Abstract
The disclosure provides a quantum circuit processing method, a quantum circuit processing device and electronic equipment, relates to the technical field of quantum computing, and particularly relates to the technical field of quantum circuits. The specific implementation scheme is as follows: acquiring a first instruction list of a first quantum circuit; based on the first instruction list, acquiring a dependency relationship of an execution sequence of an operation instruction of the first quantum circuit; based on the dependency relationship, reordering the operation instructions of the first quantum circuit according to the sequence from small to large of the qubit marks acted by the operation instructions to obtain a second instruction list of the first quantum circuit; based on the second instruction list, performing equivalent compiling on the first quantum circuit to obtain a third instruction list of the second quantum circuit equivalent to the first quantum circuit, wherein the third instruction list comprises: the operation instruction of the reset operation is located after the operation instruction of the quantum measurement operation, and the quantum bit number of the second quantum circuit is smaller than the quantum bit number of the first quantum circuit.
Description
Technical Field
The disclosure relates to the technical field of quantum computing, in particular to the technical field of quantum circuits, and specifically relates to a quantum circuit processing method, a quantum circuit processing device and electronic equipment.
Background
The quantum computing provides a brand new and very promising information processing mode by utilizing the specific operation rule in the quantum world. Quantum algorithms can offer advantages over classical algorithms over a number of specific problems. For example, large integers can be efficiently decomposed using the schiff (shell) algorithm, and data search can be performed faster using the Grover (Grover) algorithm. With the development of quantum theory, new quantum algorithms are continuously proposed, and how to efficiently simulate the algorithms or run the algorithms on real quantum hardware is always an important problem.
Currently, classical simulation or true operation of quantum algorithms is mainly limited by the number of qubits. In classical simulation, since the length of the column vector describing the quantum state grows exponentially with the corresponding number of bits (e.g., the length of the column vector of an nbit quantum state is 2 ^{n} ) Classical computers have difficulty simulating largescale quantum algorithms. Limited by computer memory and processor capacity, existing quantum circuit simulation methods can support algorithms simulating tens of qubits at most。
Disclosure of Invention
The disclosure provides a quantum circuit processing method, a quantum circuit processing device and electronic equipment.
According to a first aspect of the present disclosure, there is provided a quantum circuit processing method, comprising:
obtaining a first instruction list of a first quantum circuit, the first instruction list comprising: the quantum gate operation control method comprises an operation instruction of quantum measurement operation and an operation instruction of quantum gate operation, wherein the operation instruction of quantum measurement operation is positioned behind the operation instruction of quantum gate operation;
based on the first instruction list, acquiring a dependency relationship of an execution sequence of an operation instruction of the first quantum circuit;
based on the dependency relationship, reordering the operation instructions of the first quantum circuit according to the sequence from small to large of the qubit marks acted by the operation instructions to obtain a second instruction list of the first quantum circuit;
based on the second instruction list, performing equivalent compiling on the first quantum circuit to obtain a third instruction list of a second quantum circuit equivalent to the first quantum circuit, wherein the third instruction list comprises: and the operation instruction of the reset operation is positioned after the operation instruction of the quantum measurement operation, the reset operation is used for resetting the quantum state of the quantum bit to the zero state, and the quantum bit number of the second quantum circuit is smaller than that of the first quantum circuit.
According to a second aspect of the present disclosure, there is provided a quantum circuit processing apparatus comprising:
a first obtaining module, configured to obtain a first instruction list of a first quantum circuit, where the first instruction list includes: the quantum gate operation control method comprises an operation instruction of quantum measurement operation and an operation instruction of quantum gate operation, wherein the operation instruction of quantum measurement operation is positioned behind the operation instruction of quantum gate operation;
the second acquisition module is used for acquiring the dependency relationship of the execution sequence of the operation instruction of the first quantum circuit based on the first instruction list;
the reordering module is used for reordering the operation instructions of the first quantum circuit according to the sequence from small to large of the quantum bit marks acted by the operation instructions based on the dependency relationship, so as to obtain a second instruction list of the first quantum circuit;
the equivalent compiling module is configured to perform equivalent compiling on the first quantum circuit based on the second instruction list, and obtain a third instruction list of the second quantum circuit equivalent to the first quantum circuit, where the third instruction list includes: and the operation instruction of the reset operation is positioned after the operation instruction of the quantum measurement operation, the reset operation is used for resetting the quantum state of the quantum bit to the zero state, and the quantum bit number of the second quantum circuit is smaller than that of the first quantum circuit.
According to a third aspect of the present disclosure, there is provided an electronic device comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform any one of the methods of the first aspect.
According to a fourth aspect of the present disclosure, there is provided a nontransitory computerreadable storage medium storing computer instructions for causing a computer to perform any of the methods of the first aspect.
According to a fifth aspect of the present disclosure, there is provided a computer program product comprising a computer program which, when executed by a processor, implements any of the methods of the first aspect.
The technology solves the problem that classical simulation and true operation of a quantum circuit are difficult in the related technology, so that the classical simulation and true operation of the quantum circuit with largescale quantum bits can be realized.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.
Drawings
The drawings are for a better understanding of the present solution and are not to be construed as limiting the present disclosure. Wherein:
fig. 1 is a flow diagram of a quantum circuit processing method according to a first embodiment of the present disclosure;
FIG. 2 is a schematic diagram of an exemplary static quantum circuit;
FIG. 3 is a schematic diagram of an exemplary quantum circuit including classical control quantum operations;
FIG. 4 is a schematic diagram of a static quantum circuit processed based on the deferred measurement principle;
FIG. 5 is a schematic diagram of an exemplary dynamic quantum circuit;
FIG. 6 is a schematic diagram of a static quantum circuit after numbering of the quantum operations;
FIG. 7 is a schematic diagram of another example static quantum circuit structure;
FIG. 8 is a schematic diagram of another exemplary dynamic quantum circuit configuration;
FIG. 9 is a graph comparing the results of the operation of a static quantum circuit and a dynamic quantum circuit;
fig. 10 is a schematic structural view of a quantum circuit processing apparatus according to a second embodiment of the present disclosure;
fig. 11 is a schematic block diagram of an example electronic device used to implement embodiments of the present disclosure.
Detailed Description
Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of wellknown functions and constructions are omitted in the following description for clarity and conciseness.
First embodiment
As shown in fig. 1, the present disclosure provides a quantum circuit processing method, including the steps of:
step S101: obtaining a first instruction list of a first quantum circuit, the first instruction list comprising: an operation instruction of a quantum measurement operation and an operation instruction of a quantum gate operation, the operation instruction of the quantum measurement operation being located after the operation instruction of the quantum gate operation.
In this embodiment, the quantum circuit processing method relates to the technical field of quantum computing, in particular to the technical field of quantum circuits, and can be widely applied to classical simulation and true operation scenes of quantum circuits. The quantum circuit processing method of the embodiment of the present disclosure may be performed by the quantum circuit processing apparatus of the embodiment of the present disclosure. The quantum circuit processing apparatus of the embodiments of the present disclosure may be configured in any electronic device to perform the quantum circuit processing method of the embodiments of the present disclosure.
The existing quantum circuit simulation mode can support an algorithm for simulating tens of quantum bits at most under the limitation of the memory and the processor capacity of a computer. For example, notebooks can simulate around 2030 qubits, and large supercomputers and clusters can simulate up to around 3040 qubits. On the true machine operation, the problem of scalability of the current quantum chip is not solved, so that the number of quantum bits which can be provided by a quantum computer is very limited. Quantum circuit optimization is therefore a fundamental problem in the field of quantum computing.
The quantum circuit optimization is realized by a certain technical means, and a given quantum circuit can be simplified to reduce the requirements of classical simulation and true operation of the quantum circuit, so that the research of a quantum algorithm and the landing of quantum calculation in an actual scene are accelerated.
The quantum circuit processing in this embodiment may be quantum circuit optimization processing, and the purpose of the quantum circuit processing in this embodiment is to make the quantum circuit obtained by compiling perform optimization compilation on the quantum circuit greatly simplify the original quantum circuit in terms of the number of quantum bits. On one hand, the scale of the classical simulation of the quantum algorithm can be further improved, the verification capability of a classical computer on the quantum algorithm is enhanced, on the other hand, the bit number requirement of the quantum algorithm on the true machine operation can be reduced, and the defect of expandability of the current quantum chip is overcome.
The quantum circuit model is described in detail below.
Currently, quantum computing implementations can be based on quantum circuit models, i.e., the evolution of the quantum states is accomplished by acting a series of quantum gates on the qubits, and quantum measurements are made at the ends of the circuit to obtain the computation results.
Currently, the quantum circuits used in relatively large numbers are static quantum circuits, i.e. quantum circuits that contain quantum measurement operations only at the ends of the circuit. With the rapid development of hardware in recent years, mainly the significant improvement of the coherence time of qubits and the realization of highfidelity intermediate state measurement and reset operations, dynamic quantum circuits including circuit intermediate measurement and reset operations are increasingly receiving attention from the industry.
Due to the introduction of intermediate measurement of the circuit, the dynamic quantum circuit can effectively combine quantum computation with realtime classical computation and communication within the coherence time of the quantum bit. This feature greatly increases the variety of computational tasks that can be accomplished by quantum circuit models. For example, with intermediate measurements of dynamic quantum circuits, a feedforward operation may be implemented in the circuit operation, i.e. deciding what quantum gate to act next based on the results obtained from the intermediate measurements, or discarding the current calculation results to restart the calculation task. Such functionality is very important in implementing quantum error correction. It is therefore expected that dynamic quantum circuits will become an important component of various quantum algorithms and quantum applications in the future.
Furthermore, since the qubits in the dynamic quantum circuit can be reset and used continuously in the subsequent calculation process, the dynamic quantum circuit can effectively reduce the number of qubits required for the calculation task without any influence on the calculation capability in theory, compared with the static quantum circuit, in the case of running the same quantum algorithm. For example, in a static quantum circuit, the BersteinVazirani algorithm requiring n qubits can be implemented in a dynamic quantum circuit with only 2 qubits.
It can be seen that dynamic quantum circuits have many advantages and are increasingly being appreciated by the industry. However, more static quantum circuits are still used at present, so that one core problem of introducing dynamic quantum circuits is that: given a static quantum circuit, how to obtain a dynamic quantum circuit equivalent thereto. The embodiment can equivalently compile a static quantum circuit into a dynamic quantum circuit, and can greatly reduce the number of quantum bits used by the whole calculation task, thereby being beneficial to realizing a plurality of advantages of the dynamic quantum circuit.
The quantum circuit diagram may represent the overall process of quantum circuit model computation.
Fig. 2 is a schematic diagram of an exemplary static quantum circuit, and as shown in fig. 2, a qubit system may be represented by a horizontal line, where qubits of a qubit are numbered sequentially from top to bottom, where the number of qubits tends to start from zero.
The time evolution direction in the quantum circuit diagram is from left to right, the leftmost end is an initial quantum state, wherein each quantum bit is initialized to be a zero state, and then different quantum gate operations are sequentially applied to the initial state to complete the evolution of the quantum state. Meanwhile, quantum measurement can be carried out on some qubits, and measurement results are obtained.
If no reset, intermediate quantum measurement, etc. operations are included in one quantum circuit and all measurement operations are located at the very end of the quantum circuit, such a quantum circuit is referred to as a static quantum circuit, an example of which is shown in fig. 2.
The remainder of the quantum circuit diagram, except for the initial quantum state, may be generally represented by an ordered list of instructions in the order of action of the quantum gates, each element in the list representing an operational instruction, which may be a quantum gate operational instruction or a quantum measurement operational instruction.
Each single bit quantum gate (e.g., H, X, Y, Z, S, T, rx, ry, rz, etc.) is represented as an operation instruction [ name, while_qubit, parameters, condition ] containing four elements, where name is the name of the quantum gate, while_qubit is the qubit that the quantum gate acts on, parameters are the parameters of the quantum gate (default to None if no parameters are present), and conditions indicate which qubit measurement the quantum gate operation is controlled by (this parameter defaults to None in standard quantum circuits). For example, [ Rx,2, pi, none ] represents acting an Rx rotation gate on the qubit on qubit 2, with a rotation angle pi.
Each twobit quantum gate (e.g., control not gate CNOT, control Z gate CZ) is represented as an instruction containing four elements [ name, white_qubit, parameters, condition ]. Wherein name is the name of the quantum gate, while_qubit is a list composed of control bits and controlled bits, parameters are parameters of the quantum gate (if no parameters are defaults to None), and condition parameters in a standard quantum circuit are defaults to None. For example, [ SWAP, [1,2], none ] represents the action of a SWAP gate between qubits 1 and 2; [ CNOT, [1,3], none ] represents a control NOT acting on qubit 1 and qubit 3, where qubit 1 is the control bit and qubit 3 is the control bit.
The measurement under each computation is represented as an instruction containing four elements [ measure, white_qubit, none ]. For example, [ measure,2, none ] represents a measurement based on the calculation of qubit 2.
According to the instruction representation rules as above, the static quantum circuit in fig. 2 can be represented as an ordered list of instructions as follows: static_circuit= [ [ H,0, none ], [ H,1, none ], [ H,2, none ], [ CNOT, [0,1], none ], [ SWAP, [1,2], none ], [ Rx,0, α, none ], [ Ry,1, β, none ], [ Rz,2, γ, none ], [ measure,0, none ], [ measure,1, none ], [ measure,2, none ] ].
Classical control quantum operation: in addition to the abovedescribed types of operations in static quantum circuits, quantum measurements of a portion of the qubits may occur in the operation of the quantum circuit, and the evolution of the remaining qubits is regulated in accordance with the results of the measurements, such operations being referred to as classical control quantum operations. An example of a quantum circuit containing classical control quantum operations is shown in fig. 3, where quantum operation 301 is a classical control quantum operation.
Each classical control quantum gate operation is represented as an instruction containing four elements [ name, white_qubit, parameters, condition ], where name is the name of the quantum gate, white_qubit is the qubit of the qubit that the quantum gate acts on, parameters are parameters of the quantum gate (default to None if no parameters are present), and condition indicates which qubit measurement the quantum gate operation is controlled by. For example, the classical controlled quantum X gate for quantum operation 301 in fig. 3 may be represented as [ X,2, none,1], i.e., the Pauli X gate acting on the qubit of qubit 2, with the controlled condition being the measurement of the qubit on qubit 1, with the measurement of 0 not acting on the quantum gate and the measurement of 1 acting on the quantum gate.
For classical control quantum operations in quantum circuits, it is generally more difficult to run on real quantum computers, and it is therefore necessary to convert them by deferred measurement principles.
The deferred measurement principle is as follows: any measurement at the intermediate stage of the quantum circuit can always be moved to the end of the circuit; classical control quantum operations may be replaced by quantum control operations if the measurement is used at a certain stage of the circuit. For example, the quantum circuit shown in fig. 3, the static quantum circuit obtained after the delay measurement process can be represented as shown in fig. 4 below.
In some application scenarios, it may be allowed to measure some qubits in the middle of the quantum circuit and reset them to the 0> state after the measurement results for continued use by subsequent computations. And a quantum circuit that includes a circuit intermediate measurement and a reset operation is called a dynamic quantum circuit.
Each reset operation instruction may be represented as an instruction [ reset, whish_qubit, none ] containing four elements, where whish_qubit is a qubit of a qubit that needs to be reset, and after the reset operation, the qubit of the qubit is available for further use in subsequent computation.
As shown in fig. 5, which is a schematic structural diagram of an exemplary dynamic quantum circuit, the dynamic quantum circuit in fig. 5 is equivalent to the static quantum circuit shown in fig. 4, where the symbol R of the quantum operation in fig. 5 represents a reset operation, and according to the instruction expression rule as above, the dynamic quantum circuit in fig. 5 may be represented as the following ordered instruction list: dynamic_circuit= [ [ H,0, none ], [ H,1, none ], [ CNOT, [0,1], none ], [ H,0, none ], [ measure,0, none ], [ reset,0, none ], [ H,0, none ], [ SWAP, [0,1], none, none ], [ H,0, none ], [ H,1, none ], [ CNOT, [1,0], none ], [ measure,0, none ], [ measure,1, none ], [ reset,0, none ], [ reset,1, none ] ].
In step S101, the first quantum circuit may be a static quantum circuit, and the order of quantum operations in the first quantum circuit is represented by an ordered instruction list, which is a first instruction list, and may include therein an operation instruction of the first quantum circuit, including an operation instruction of a quantum measurement operation and an operation instruction of a quantum gate operation. For any classical control quantum operation, it is always possible to translate into a quantum control operation by deferring the measurement principle, so classical control quantum operation is not included in the input static quantum circuit.
The first instruction list of the first quantum circuit stored in advance may be acquired, or the first instruction list of the first quantum circuit input by the user may be acquired, which is not particularly limited herein.
Step S102: based on the first instruction list, the dependency relationship of the execution sequence of the operation instructions of the first quantum circuit is obtained.
In this step, for an operation instruction, the dependency relationship may refer to an operation instruction that must be executed before the current operation instruction is executed.
The dependency of the execution order of the respective operation instructions may be determined based on the qubits acted upon by the operation instructions in the first instruction list. If there is an intersection of qubits acted upon by different operation instructions, then the operation instructions have a dependency on the order of execution. For example, the first operation instruction is arranged in the first instruction list before the second operation instruction, and if the quantum bits acted on by the first operation instruction and the second operation instruction are respectively acted on the quantum bits 0, the first operation instruction must be executed and completed before the second operation instruction is executed, and a dependency relationship exists between the two operation instructions.
In an alternative embodiment, for each operation instruction, the first instruction list may be traversed reversely (i.e. from back to front), and other operation instructions having intersections with the qubit acted on by the operation instruction are obtained, and the dependency relationship of the operation instruction may include other operation instructions ordered before the operation instruction and having intersections with the qubit.
In another alternative embodiment, the qubit acted on by the operation instruction in the first instruction list may be acquired; numbering the operation instructions based on the sequence of the quantum bits acted by the operation instructions in the quantum operation of the first quantum circuit to obtain the numbering information of the operation instructions of the first quantum circuit; and searching other operation instructions associated with the operation instructions in the first quantum circuit based on the serial number information of the operation instructions to obtain the dependency relationship.
Step S103: and based on the dependency relationship, reordering the operation instructions of the first quantum circuit according to the sequence from small to large of the qubit marks acted by the operation instructions to obtain a second instruction list of the first quantum circuit.
In this step, after obtaining the dependency relationship of the execution order of the operation instructions of the first quantum circuit, the operation instructions of the first quantum circuit may be sequentially optimized, that is, reordered.
The operation instructions in the first instruction list may be reordered according to a preset priority rule to implement reordering of the operation instructions of the first quantum circuit, where the preset priority rule may be a line order priority rule, and the line order priority rule indicates that the operation instructions are ordered according to the order of the qubit labels acted by the operation instructions from small to large, that is, the operation instructions acted by the qubit 0 are ordered first, the operation instructions acted by the qubit 1 are ordered again, and so on.
That is, taking into account the dependency of the execution order of the operation instructions of the first quantum circuit, the quantum operations are executed in the row order as much as possible, so that all operations on a certain qubit are executed as soon as possible, and the quantum measurement is performed on the qubit.
In an alternative embodiment, the operation instructions in the first instruction list may be reordered according to a line order priority principle, and then based on the reordering, the dependency relationship between the operation instructions is considered, that is, based on the dependency relationship between the operation instructions, the operation instructions are reordered, so as to obtain a second instruction list of the first quantum circuit. The operation instructions of the first quantum circuit can be ordered according to the corresponding sequence by reordering twice.
In another alternative embodiment, in a reordering process, the operation instructions in the first instruction list may be reordered according to a line order priority principle while considering the dependency relationship between the operation instructions, so as to obtain the second instruction list.
By reordering the operation instructions, the operation instructions in the reordered second instruction list are executed according to the ordering order indicated by the line order priority principle as far as possible while the dependency relationship among the operation instructions is considered. Therefore, on one hand, the equivalence with the original quantum circuit is not destroyed, and on the other hand, the subsequent equivalent compiling (namely equivalent compiling from the first quantum circuit to the second quantum circuit) is also preprocessed, so that the number of bits required by the compiled dynamic quantum circuit is ensured to be as small as possible.
Step S104: based on the second instruction list, performing equivalent compiling on the first quantum circuit to obtain a third instruction list of a second quantum circuit equivalent to the first quantum circuit, wherein the third instruction list comprises: and the operation instruction of the reset operation is positioned after the operation instruction of the quantum measurement operation, the reset operation is used for resetting the quantum state of the quantum bit to the zero state, and the quantum bit number of the second quantum circuit is smaller than that of the first quantum circuit.
In this step, on the basis of preprocessing the first instruction list to obtain a second instruction list, for each operation instruction in the second instruction list, an equivalent compiling may be performed on the operation instruction, so as to compile the operation instruction into an operation instruction in a second quantum circuit equivalent to the operation instruction. The second quantum circuit may be a dynamic quantum circuit.
When equivalent compiling is carried out, the quantum bit acted by the operation instruction in the second instruction list can be obtained, a register unit is allocated for the quantum bit, and the register unit can correspond to the quantum bit in the second quantum circuit. That is, the operation instruction can be mapped to a dynamic quantum circuit, and specifically, the operation on each qubit in the first quantum circuit (that is, the qubit acted by the operation instruction in the second instruction list) can be dynamically loaded into the register unit of the second quantum circuit.
After the operation instruction of the quantum measurement operation is equivalently compiled, the register unit corresponding to the operation instruction of the quantum measurement operation can be recovered, the operation instruction of the reset operation can be added after the operation instruction of the quantum measurement operation, and the register unit distributed to the quantum bit can be recovered for subsequent calculation and use through the reset operation instruction. Thus, the width of the equivalent compiled dynamic quantum circuit can be ensured to be as small as possible.
In this embodiment, by acquiring the dependency relationship between the operation instructions of the input static quantum circuit, and taking the dependency relationship between the operation instructions of the quantum circuit into consideration, the quantum operations are executed in the row order as much as possible, so that all operations on a certain quantum bit are executed as soon as possible, and quantum measurement is performed on the quantum bit, so that by preprocessing the reorder of the operation instructions, and by adding the operation instruction of the reset operation after the operation instruction of the quantum measurement operation during equivalent compiling, the operation instruction of the reset operation is used for calculating the quantum bit of the subsequent quantum bit, so that the number of bits required for the dynamic quantum circuit obtained after compiling the static quantum circuit is as small as possible, so that classical simulation and true machine operation on the quantum circuit of a largescale quantum bit can be realized, and the method can be well applied to classical simulation of a largescale quantum algorithm.
And the quantum computer based on different architecture designs can provide different quantum bit numbers and different realization capacities of various operations. Through equivalent compiling, the running scheme of the quantum circuit on a real quantum computer can be more flexible, and the dynamic quantum circuit and the static quantum circuit can be flexibly selected according to actual hardware conditions. For example, for a superconducting quantum computer with shorter coherence time but easy expansion of the number of quantum bits, it is more suitable for running a static quantum circuit with larger width and smaller depth; for a quantum computer based on an ion trap architecture, which has longer coherence time but relatively poorer expansibility, the quantum computer is more suitable for running a dynamic quantum circuit with smaller width and larger depth.
Optionally, the step S102 specifically includes:
acquiring a qubit acted by an operation instruction in the first instruction list;
numbering the operation instructions based on the order in which the qubits acted by the operation instructions appear in the quantum operations of the first quantum circuit, so as to obtain the numbering information of the operation instructions of the first quantum circuit;
and searching other operation instructions related to the operation instructions in the first quantum circuit based on the serial number information of the operation instructions to obtain the dependency relationship, wherein the quantum bits acted by the other operation instructions comprise quantum bits acted by the operation instructions, and the execution sequence of the other operation instructions is before the operation instructions.
In this embodiment, each quantum operation in the static quantum circuit may be numbered, and a dependency relationship between execution sequences of each quantum operation may be found according to the number.
The qubit acted by the operation instruction can be acquired by circularly traversing the first instruction list static_circuit of the input static quantum circuit, and each operation instruction in the qubit is numbered according to the qubit, so that the numbering information is obtained.
The number information of the operation instruction may be represented by a number parameter (which is a cmd_index parameter), and the cmd_index parameter may be added to the operation instruction. The specific format of the parameter may be a list, and the stored element is a binary array, i.e., cmd_index= [ [ white_qubit, gate_index ], … ], where white_qubit represents a qubit acted on by the operation instruction, gate_index represents an order in which the operation instruction acts on the white_qubit, and after the parameter is added, each operation instruction in the instruction list of the quantum circuit becomes a list containing five elements, i.e., gate= [ name, white_qubit, parameter, condition, cmd_index ].
For each single qubit gate, the elements in the cmd_index list contain a binary array, such as the second H gate acting on qubit 2 in fig. 4, whose operation instructions become after adding the cmd_index parameter: [ H,2, none, [2,3] ]; for each double qubit gate, the elements in the cmd_index list contain two binary arrays that mark the qubit that the double qubit gate acts on and the order in which it appears on the acting qubit, e.g., the SWAP gates acting on qubits 1 and 2 in fig. 4, respectively, the operating instructions become after adding the cmd_index parameter: [ SWAP, [1,2], none, [ [1,3], [2,2] ] ]. The results of numbering the quantum operations in the static circuit shown in fig. 4 are shown in fig. 6.
The specific process of numbering the quantum operations is as follows:
input: static quantum circuit list static_circuit;
and (3) outputting: a list of static_circuits after adding the cmd_index parameter for each operation.
Step 1: judging the currently traversed element gate by circularly traversing the static_circuit list;
step 2.1: if the current element is a singlequantumbit quantum operation (comprising a singlequantumbit gate operation and a quantum measurement operation), recording a quantum bit whish_qubit acted by the current element as a qubit_index; initializing a variable gate_index=1, and traversing all elements before the current element gate in the static_circuit list; if the qubit white_qubit list acted by the currently traversed element contains the value of the qubit_index, adding 1 to the variable gate_index; if the currently traversed element acting qubit whish_qubit list does not contain whish_qubit, continuing to traverse the next element; after the traversal is completed, adding cmd_index parameters for the current element gate, namely gate= [ name, white_qubit, parameters, conditions, [ white_qubit, gate_index ] ];
step 2.2: if the current element is a doublequantum bit gate operation, recording two values in a quantum bit white_qubit list acted by the current element as a qubit_index_0 and a qubit_index_1 respectively; initializing two variables gate_index_0=1 and gate_index_1=1, and traversing all elements before the current element gate in the static_circuit list; if the qubit_qubit list acted by the currently traversed element contains a qubit_0, adding 1 to a variable gate_index_0; if not, not performing the operation; if the qubit_1 is contained in the qubit which_qiput list acted by the currently traversed element, adding 1 to a variable gate_index_1; if not, continuing to traverse the next element; after the traversing is completed, adding cmd_index parameters for the current element gate, namely gate= [ name, white_qubit, parameters, conditions, cmd_index= [ [ qubit_0, gate_index_0], [ qubit_1, gate_index_1] ];
Step 3: and traversing the complete static_circuit list, and returning the static_circuit list after adding the cmd_index parameter for each operation instruction.
And then, searching other operation instructions associated with the operation instructions in the first quantum circuit based on the serial number information of the operation instructions, wherein the dependency relationship of the operation instructions comprises the other operation instructions associated with the operation instructions. The dependency relationship of the operation instruction may include all other operation instructions which are ordered before the operation instruction and act on the same qubit as the operation instruction, or may include only the operation instruction which is the nearest neighbor and has to be executed before the current operation instruction is executed, which is not particularly limited herein.
In the present embodiment, the quantum bits to which the operation instruction acts are numbered for each quantum operation in the static quantum circuit, and the dependency relationship between the execution sequences of each quantum operation is found according to the numbers, so that the determination of the dependency relationship of the execution sequence of the operation instruction of the first quantum circuit can be easily realized.
Optionally, the searching for other operation instructions associated with the operation instruction in the first quantum circuit based on the number information of the operation instruction to obtain the dependency relationship includes:
Acquiring target number information based on the number information of the operation instruction, wherein the number of the qubit in the target number information is the same as the number of the qubit in the number information of the operation instruction, and the occurrence order of the qubit in the quantum operation of the first quantum circuit in the target number information is smaller than the occurrence order of the qubit in the quantum operation of the first quantum circuit in the number information of the operation instruction;
and acquiring the other operation instructions corresponding to the target number information to obtain the dependency relationship, wherein the other operation instructions are operation instructions which are executed in the first quantum circuit in sequence before the operation instructions and are adjacent to the operation instructions.
In this embodiment, the determination of the dependency relationship of the execution order of the operation instructions of the first quantum circuit is realized by searching for the operation instruction that has to be executed in the nearest neighbor to the completion before the current operation instruction is executed.
The target number information may be searched for based on the number information of the operation instruction, the target number information may be included in the number information of the operation instruction that has to be executed the nearest neighbor completed before the current operation instruction, and then the dependency relationship of the operation instruction may be determined based on the target number information, and the dependency relationship may include the number information of the operation instruction that has to be executed the nearest neighbor completed before the current operation instruction.
In an alternative embodiment, a dependency parameter, referred to as domain parameter, may be added for each operation instruction in the list by cycling through the instruction list static_circuit of the static quantum circuit that has added the cmd_index parameter for each element. The specific form of this parameter is a list, i.e., domain= [ cmd_index, … ], where all cmd_index stored are cmd_index values that must be performed for the completed operation before the current operation is performed.
Only the nearest neighbor operation that has to be performed before the current operation is performed may be considered, and after adding the parameter, each operation instruction in the list becomes a list containing six elements, i.e. gate= [ name, white_qubit, parameters, condition, cmd_index, domain ].
For each singlequbit quantum operation, the domain parameter list contains only cmd_index values of one other operation instruction, and the other operation instruction may be a singlequbit quantum operation or a doublequbit gate operation. If the other operation instruction is a singlequbit quantum operation, the domain parameter of the operation instruction only includes a binary array, for example, the measurement operation numbered [0,4] on the qubit 0 in fig. 6 only needs to execute the H gate with the target number information of [0,3] before executing the operation, so that the operation instruction becomes after the measurement operation has added the domain parameter: [ measure,0, none, [0,4], [ [0,3] ]; if the other operation instruction is a twoqubit gate, the domain parameter of the operation instruction includes two binary arrays contained in a list, and the two binary arrays are represented as the number information of one operation instruction, for example, the H gate numbered [0,3] on the qubit 0 in fig. 6, and the CNOT gate numbered [ [0,2], [1,2] ] acting between the qubit 0 and the qubit 1 needs to be executed before the operation is executed, so that the list of instructions becomes after the H gate adds the domain parameter: [ H,0, none, [0,3], [ [ [0,2], [1,2] ] ].
For each twoqubit gate, the operations that must be performed on the two qubits that perform their role before the quantum gate can be recorded separately, i.e., the domain parameter of each twoqubit gate contains the cmd_index values of two other operation instructions, which can be stored separately as a separate list. The other operation instruction may be a single double qubit operation, and if the two other operation instructions are the same double qubit gate, the cmd_index value for that gate is stored twice, i.e., also as two separate lists.
For example, the CNOT gate with the reference number [ [0,2], [1,2] ] acting between qubit 0 and 1 in FIG. 6, the H gate with the reference number [0,1] on qubit 0 and the H gate with the reference number [1,1] on qubit 1 need to be executed before executing the CNOT gate, so that the operation instruction after adding domain parameters becomes: [ CNOT, [0,1], none, [ [0,2], [1,2] ], [ (0, 1], [1,1] ] ].
Whereas the SWAP gate with reference number [ [1,3], [2,2] ] acting between qubits 1 and 2 in fig. 6, the execution of the SWAP gate was preceded by the execution of the CNOT gate with reference number [ [0,2], [1,2] ] between qubits 0 and 1 and the H gate with reference number [2,1] on qubit 2, so the instruction list after the SWAP gate added domain parameters becomes: [ SWAP, [1,2], none, [ [1,3], [2,2] ], [ [ [0,2], [1,2] ], [2,1] ].
If no other operation is required before executing a certain operation, the domain parameter of the operation instruction is an empty list, for example, the H gate denoted by [1,1] acting on the qubit 1 in fig. 6, and the operation instruction becomes after adding the domain parameter: [ H,1, none, [1,1], [ ] ].
Input: an instruction list static_circuit of the static quantum circuit to which the cmd_index parameter is added;
and (3) outputting: a static_circuit list after domain parameters is added for each operation instruction.
Step 1: traversing the static_circle list circularly, adding domain parameters for each traversing to one element, and judging the initial value as an empty list according to the current element gate;
step 2.1: if the current element is a quantum operation of single quantum bit, recording the quantum bit whish_qubit acted by the current element as a qubit_index; then traversing all elements before the current element gate in the static_circuit list in a reverse order through circulation; if the traversed qubit white_qubit list acted by the current element contains the value of the qubit_index, adding the value of the cmd_index of the current traversed element into a domain parameter of the gate operation, and skipping out the cycle traversal; if the traversed qubit whish_qubit list of the current element action does not contain the value of the qubit_index, continuing to traverse the next element;
Step 2.2: if the current element is a doublequantum bit gate, respectively recording two values in a quantum bit white_qubit list acted by the current element as a qubit_index_0 and a qubit_index_1, and initializing two variables of Boolean type, namely, qubit_0_done=false, wherein qubit_1_done=false; then traversing all elements before the current element gate in the static_circuit list by cycling into the reverse order; if the traversed qubit white_qubit list of the current element contains the value of qubit_index_0 and the value of qubit_0_done is False, adding the value of cmd_index of the current traversed element to the domain parameter of the gate operation, and simultaneously modifying the value of qubit_0_done to True; if the traversed qubit which_qubit list acted by the current element does not contain the value of the qubit_index_0 or the value of the qubit_0_done is True, not performing operation; if the traversed qubit white_qubit list acted by the current element contains the value of the qubit_index_1 and the value of the qubit_1_done is False, adding the value of the cmd_index of the current traversed element into the domain parameter of the gate operation, and simultaneously modifying the value of the qubit_1_done to True; if the traversed qubit which_qubit list acted by the current element does not contain the value of the qubit_index_0 or the value of the qubit_1_done is True, not performing operation; if the values of the qubit_0_done and the qubit_1_done are True, jumping out of the loop, otherwise continuing to traverse the next element;
Step 3: after the loop traverses the static_circle list, the static_circle list after adding domain parameters for each operation instruction is returned.
In this embodiment, the determination of the dependency relationship of the execution order of the operation instructions of the first quantum circuit can be easily realized by searching for the operation instruction that has to be executed in the nearest neighbor before the current operation instruction is executed.
Optionally, the step S103 specifically includes:
first reordering the operation instructions of the first quantum circuit according to the sequence from small to large of the quantum bit marks acted by the operation instructions to obtain a fourth instruction list of the first quantum circuit, wherein in the fourth instruction list, the marks of target quantum bits in the operation instructions ordered before are smaller than the marks of target quantum bits in the operation instructions ordered after, and the operation instructions with the same marks of the acted quantum bits are arranged according to the relative sequence of the operation instructions in the first quantum circuit, and the target quantum bits are the quantum bits with small marks in the operation instructions;
and based on the dependency relationship, performing second reordering on the fourth instruction list to obtain the second instruction list.
In this embodiment, the operation instructions in the first instruction list may be reordered according to the line order priority principle, and then based on the reordering, the dependency relationship between the operation instructions is considered, that is, based on the dependency relationship between the operation instructions, the operation instructions are reordered to obtain the second instruction list. That is, the operation instructions can be ordered according to the corresponding sequence by reordering twice.
In the first reordering process, comparing the target quantum bit acted by each operation instruction in the instruction list of the quantum circuit, wherein the operation instruction with the small sequence number of the target quantum bit is arranged in front; and for the instructions with the same target qubit sequence number, arranging the instructions according to the relative sequence of the instructions in the instruction list of the original qubit circuit, and correspondingly obtaining an instruction list under default ordering, namely a fourth instruction list. For quantum operation of single quantum bit, the target quantum bit takes the value of the quantum bit whish_qubit acted by the target quantum bit; for a twoqubit gate, the target qubit sequence number takes the value of the smaller one of the qubits in its active whish_qubit list.
Note that default ordering does not take into account dependencies between operational nodes, but rather is an ideal ordering. And carrying out second reordering according to the dependency relationship among the operation instructions on the basis of default ordering to obtain a second instruction list.
In an alternative embodiment, the operation instructions in the fourth instruction list may be reordered by exchanging between different operation instructions, so that, for each operation instruction, other operation instructions with dependency relationships are ordered before the operation instruction, and the order of the operation instructions after the second reordering is the default order.
In another alternative embodiment, the second reordering of the operation instructions in the fourth instruction list may be implemented by obtaining a list of operation instructions ordered after and having a dependency relationship with the operation instructions, and by ordering the different lists.
Wherein the different lists may include a list of operation instructions ordered before the operation instruction, a list of operation instructions ordered after the operation instruction and having a dependency relationship therewith, a list of operation instructions, and a list of operation instructions ordered after the operation instruction and having no dependency relationship therewith.
In this embodiment, the operation instructions in the first instruction list are reordered according to the line order priority principle, and then the dependency relationship between the operation instructions is considered on the basis of the reordering, that is, the operation instructions are reordered based on the dependency relationship between the operation instructions, so as to obtain the second instruction list. That is, the operation instructions can be ordered according to the corresponding sequence by reordering twice. In this way, the process of reordering the operation instructions can be simplified.
Optionally, the performing, based on the dependency relationship, a second reordering on the fourth instruction list to obtain the second instruction list includes:
Traversing the fourth instruction list aiming at operation instructions, splitting the fourth instruction list aiming at the operation instructions which are currently traversed to obtain a first list, a second list and a third list, wherein the first list is a list formed by the operation instructions which are sequenced in the first position in the fourth instruction list to the previous operation instructions adjacent to the operation instructions which are currently traversed, the second list is a list formed by the operation instructions which are currently traversed, and the third list is a list formed by the operation instructions which are sequenced in the fourth instruction list and are sequenced after the operation instructions which are currently traversed;
based on a target dependency relationship between the currently traversed operation instruction and the operation instruction of the first quantum circuit, the first list, the second list and the third list in the dependency relationship, rearranging the operation instruction of the fourth instruction list;
and determining the second instruction list based on the rearranged fourth instruction list under the condition that the fourth instruction list traversal is completed.
In this embodiment, the second reordering of the operation instructions in the fourth instruction list may be implemented by acquiring a list of operation instructions ordered after the operation instruction and having a dependency relationship with the operation instruction, and by ordering the operation instructions in a different list.
Specifically, the fourth instruction list may be traversed with respect to the operation instruction, and the fourth instruction list may be split with respect to the currently traversed operation instruction, to obtain a first list, a second list, and a third list. For example, if the currently traversed operation instruction is the jth instruction, the first list is a list formed by the operation instructions ordered from 1 st to j1 st in the fourth instruction list, the second list is a list formed by the currently traversed operation instruction, and the third list is a list formed by the operation instructions ordered from j+1 to m in the fourth instruction list. Where m is the length of the fourth instruction list, i.e. the number of operation instructions.
Accordingly, a list of operation instructions ordered after the operation instruction and having a target dependency relationship with the operation instruction may be selected from the third list based on the target dependency relationship and the first list between the currently traversed operation instruction and the operation instruction of the first quantum circuit.
The list stitching may be performed based on the first list, the list (i.e., the list of the operation instructions ordered after the operation instruction currently traversed and having the target dependency relationship with the operation instruction), the second list, and the order of the list of the operation instructions ordered after the operation instruction and having no target dependency relationship with the operation instruction determined based on the third list and the list, so that the second reordering of the operation instructions in the fourth instruction list may be implemented, and the second instruction list may be obtained.
Therefore, the sequencing adjustment of the operation instructions in default sequencing can be realized based on the dependency relationship among the operation instructions, and the sequencing adjustment process is simpler.
Optionally, the rearranging the operation instruction for the fourth instruction list based on the target dependency relationship between the currently traversed operation instruction and the operation instruction for the first quantum circuit in the dependency relationship, the first list, the second list, and the third list includes:
acquiring a first target list based on the target dependency relationship and the first list, wherein the first target list indicates an operation instruction with the target dependency relationship between the first list and the currently traversed operation instruction;
determining a third target list based on the first target list and a second target list, wherein the second target list indicates an operation instruction with the target dependency relationship between the fourth instruction list and the currently traversed operation instruction, and the third target list is a list obtained by deleting the first target list from the second target list;
deleting an operation instruction indicated by the third target list from the third list to obtain a fourth list under the condition that the third target list is not an empty set;
And performing list splicing on the first list, the operation instruction indicated by the third target list, the second list and the fourth list according to the sequence from front to back to obtain a rearranged fourth instruction list.
In this embodiment, based on the target dependency relationship between the currently traversed operation instruction and the operation instruction of the first quantum circuit, the operation instruction having the target dependency relationship with the currently traversed operation instruction may be acquired from the first list, and these operation instructions may constitute the first target list. For example, an operation instruction including a domain parameter in the currently traversed operation instruction may be obtained from the first list, to obtain a first target list.
And acquiring a second target list, wherein the second target list can comprise operation instructions with target dependency relations between the fourth instruction list and the operation instructions currently traversed, and the list obtained after deleting the first target list from the second target list is a third target list which is a list of operation instructions sequenced after the operation instructions currently traversed and with target dependency relations. The operation instructions in the third target list are ordered according to a line order priority principle, namely default ordering.
If the third target list is empty, the third list is indicated that no operation instruction with target dependency relationship with the currently traversed operation instruction exists.
If the third target list is not empty, the operation instruction with the target dependency relationship with the operation instruction currently traversed exists in the third list. Correspondingly, the operation instructions in the third target list in the third list can be deleted to obtain a fourth list, wherein the fourth list is a list of operation instructions which are ordered after the currently traversed measurement instructions and have no target dependency relationship with the measurement instructions.
And performing list splicing according to the arrangement sequence of the first list, the third target list, the second list and the fourth list from front to back, so as to obtain a rearranged fourth instruction list, and then determining a second instruction list based on the rearranged fourth instruction list. In this way, determination of the second instruction list may be achieved.
Based on the default ordering (namely ordering indicated by a line order priority principle), the procedure of ordering adjustment according to the dependency relationship between operation instructions is as follows:
input: an instruction list static_circuit of the static quantum circuit added with cmd_index and domain parameters;
And (3) outputting: and operating an instruction list of the static quantum circuit after the execution sequence optimization.
Step 1: the method comprises the steps of carrying out default sorting on an input instruction list static_circuit, wherein the length of a record list is m;
step 2: by cycling through the static_circle list, assume that the current element gate is the ith element in the list (where i ε {1,2, …, m }); setting a parameter optimal=false, and when optimal=false, performing the following operations:
operation 2.1: recording a list formed by 1 st to i1 st elements in the list static_circuit as an S1 list (a first list), storing the currently traversed element gate into an S2 list (a second list), and recording a list formed by i+1 th to mth elements in the list static_circuit as an S3 list (a third list);
operation 2.2: recording a set formed by cmd_index parameters of all operation instructions in the S1 list in a circuit_indexes list, and recording a set formed by domain parameters of operation instruction gate in the S2 list in a domains list;
operation 2.3: performing set operation p_index=domains\circuits_indexes, namely solving elements in the domains list, which are not included in the circuits_indexes list, and storing the elements in the p_index list; if the P_index list is not empty, traversing the S3 list, finding operation instructions corresponding to all elements in the P_index in the S3 list, storing the operation instructions in the P list (namely operation instructions indicated by a third target list), carrying out default ordering on all operation instructions in the P list, deleting all operation instructions in the P list from the S3 list to obtain an S4 list (a fourth list), and updating the order of the static_circuit list to [ S1, P, S2, S4]; if the P_index list is empty, rewriting an optimal parameter into True, jumping out of the current loop, and continuing to loop through the (i+1) th operation instruction in the static_circuit list;
Step 3: after all elements of the static_circuit list are circularly traversed, the updated static_circuit list is an instruction list of the quantum circuit after the execution sequence is optimized.
In order to measure a certain quantum bit in the quantum circuit as soon as possible, so as to facilitate the reset of the quantum bit for subsequent calculation, after the second reordering is completed, the execution sequence of each quantum measurement operation in the rearranged fourth instruction list may be moved forward as far as possible.
Optionally, after the second reordering of the fourth instruction list based on the dependency relationship, the method further includes:
moving the operation instruction of the quantum measurement operation in the rearranged fourth instruction list to a target position to obtain a second instruction list;
the target position is a position located after a target operation instruction in the rearranged fourth instruction list and adjacent to the target operation instruction, the qubit acted by the target operation instruction comprises the qubit acted by the operation instruction of the quantum measurement operation, and the operation instruction ordered after the target position in the second instruction list does not comprise the qubit acted by the operation instruction of the quantum measurement operation.
The specific process is as follows:
input: the fourth instruction list is an instruction list static_circuit after the execution sequence of each quantum operation is optimized and sequenced;
and (3) outputting: and (3) an instruction list after optimizing the execution sequence of all quantum measurement operations.
Step 1: traversing the instruction list static_circuit through a loop;
step 2.1: if the currently traversed operation instruction is an operation instruction of a measurement operation, recording the measured qubit as measured_qubit=white_qubit, and traversing the static_circuit list in reverse order from the previous operation of the measurement operation, and setting the currently traversed element as gate= [ name, white_qubit, parameter, condition, cmd_index, domain ]; if the measured_qubit is contained in the qubit white_qubit list acted by the currently traversed element gate, inserting an operation instruction of the currently traversed measurement operation into the gate operation, and then jumping out of the reverse sequence traversal;
step 2.2: if the measured_qubit is not contained in the qubit whish_qubit list acted on by the currently traversed element gate, continuing to traverse the next operation instruction;
Step 3: after the traversing of the whole static_circuit is completed, returning to the instruction list after the execution sequence optimization of the measurement operation, namely, a second instruction list.
In this way, all operations on a qubit can be performed as quickly as possible and the qubit can be measured.
Optionally, the step S104 specifically includes:
for each operation instruction in the second instruction list, executing the following operation:
obtaining a qubit acted by the operation instruction;
determining a target identification of a register unit of a second quantum circuit allocated for the quantum bit based on the quantum bit and a register unit dictionary, wherein the register unit dictionary comprises a corresponding relation between the register unit and the quantum bit;
and based on the target identification, performing equivalent compiling on the operation instruction to obtain an operation instruction in a second quantum circuit equivalent to the operation instruction, wherein the third instruction list comprises the operation instruction in the second quantum circuit obtained by equivalent compiling.
In this embodiment, equivalent compiling may be performed for each operation instruction in the second instruction list.
The operation instructions in the second instruction list may include instruction types and acted upon qubits.
In the equivalent compiling process, a quantum register can be introduced, and the dynamic increase and decrease management is carried out on the register unit, so that the static_circuit list is further compiled into a dynamic quantum circuit instruction list dynamic_circuit.
Specifically, when traversing the instruction list static_circuit of the input static circuit, each qubit in the instruction list static_circuit can be dynamically corresponding to a register unit of the quantum register, and the unit address of the register unit is the qubit in the compiled dynamic quantum circuit.
The target identification of the register unit of the second quantum circuit allocated for the qubit, i.e., the address of the register unit, may be determined based on the qubit acted upon by the operation instruction and the constructed register unit dictionary. The register unit dictionary may be used to record the occupied state of the register unit, that is, the key of the data in the register unit dictionary may be the address of the register unit, and the corresponding value may be which qubit in the static quantum circuit instruction list the register unit is allocated to.
For example, the registering unit dictionary may be: { '0':0, '1': none, '2':3}, indicating that register cell with address 0 is allocated to qubit 0, register cell with address 1 is idle (i.e., not allocated), and register cell with address 2 is allocated to qubit 3.
In an alternative embodiment, before performing equivalent compiling of the second instruction list, an empty register unit dictionary may be constructed, and correspondingly, when performing equivalent compiling of the instruction in the second instruction list, a register unit may be allocated based on a qubit acted by the register unit dictionary as an operation instruction (e.g., when the register unit dictionary is empty, a new register unit may be created and an address of the register unit is recorded), and the register unit dictionary may be updated based on a correspondence relationship between the qubit and the address of the register unit, so as to record an occupied state of the register unit. Then, based on the qubit acted by the operation instruction in the second instruction list and the updated register unit dictionary, the equivalent compiling of the operation instruction in the second instruction list can be continued.
In the case of obtaining the target identifier, the operation instruction in the second instruction list may be equivalently compiled based on the target identifier, where the target identifier may indicate a qubit of a qubit acted on by the operation instruction in the second quantum circuit equivalent to the operation instruction. The equivalent compiling process will be described in detail in the following embodiments.
In this way, an equivalent compilation of the operating instructions of the first quantum circuit can be achieved to obtain the operating instructions in the second quantum circuit equivalent to the first quantum circuit.
Optionally, the determining, based on the qubit and the register unit dictionary, the target identification of the register unit of the second quantum circuit allocated to the qubit includes at least one of the following:
under the condition that the corresponding relation of the quantum bit is included in the register unit dictionary, determining the identification of the register unit corresponding to the quantum bit as the target identification;
and under the condition that the corresponding relation of the quantum bit is not included in the register unit dictionary, distributing the register unit for the quantum bit based on the register unit dictionary, determining the identification of the register unit distributed by the quantum bit as the target identification, and updating the register unit dictionary based on the identification of the register unit distributed by the quantum bit.
In this embodiment, if one qubit in the instruction list of the static quantum circuit has a corresponding register unit, all quantum operations on the qubit in the instruction list of the static quantum circuit are transferred to the qubit of the dynamic quantum circuit corresponding to the register unit address for execution.
If a qubit does not have a corresponding register unit, it is allocated a register unit. Optionally, the allocating the register unit for the qubit based on the register unit dictionary may be performed by searching whether an idle register unit is available for allocation in the created register unit, including at least one of:
Under the condition that the register unit dictionary comprises the identification of a first register unit, the first register unit is allocated to the qubit, and the first register unit is not allocated to a node;
and under the condition that the register unit dictionary does not comprise the identification of the first register unit, acquiring the number of the register units represented by the register unit dictionary, determining the identification of the created second register unit based on the number, and distributing the second register unit to the quantum bit.
If there are multiple idle register units, in an embodiment, the first register unit is the register unit with the smallest identifier in the register units not allocated to the node, that is, the register unit with the smallest address is selected for allocation, so that accurate and orderly allocation of the register units can be ensured.
If all of the currently created register units are occupied, a new register unit is created and allocated to the qubit.
Thus, the register units are dynamically increased as required, if there are free units (e.g., 1: none, indicating that register unit 1 is a free register unit), then the free units are preferentially allocated, otherwise a new register unit is created, and based on the number of register units characterized by the register unit dictionary (e.g., register unit dictionary { '0':0, '1':2}, the number of characterized register units is 2), the identity of the created second register unit is determined, and the second register unit is allocated to the qubit acted upon by the currently equivalently compiled operation instruction.
And updating the registering unit dictionary based on the registering unit marks distributed by the qubit, namely adding the corresponding relation between the qubit and the target mark into the registering unit dictionary. After the whole static_circuit list is traversed, the total number of the created register units is the number of quantum bits required by the dynamic quantum circuits corresponding to the compiled dynamic quantum circuits, so that the width of the compiled dynamic quantum circuits can be ensured to be as small as possible, and the number of quantum bits required in executing a model can be greatly reduced.
The specific process of dynamically allocating register units for qubits is as follows:
input: the register unit dictionary qreg needs to allocate the quantum bit whish_qubit of the register unit;
and (3) outputting: the updated registering unit dictionary qreg; the register address assigned to the qubit whish_qubit.
Step 1: traversing all values of the register unit dictionary qreg and judging;
step 2.1: if the which_qubit is contained, indicating that the qubit is allocated with a register unit, recording a register unit address corresponding to the which_qubit value as address, and not operating the qreg dictionary;
step 2.2: if the whish_qubit is not allocated with a register unit, searching all register unit addresses with the value None in the register unit dictionary qreg, storing the register unit addresses into an available_units list, and judging based on the available_units list; if the available_units list is empty, no idle register units exist in the current register units, calculating the number L of the register units in qreg, recording the number L as register unit addresses assigned to the whish_qubit, and then creating a new register unit in the qreg dictionary, wherein the key is the unit address, and the value is the corresponding qubit whish_qubit; if the available_units list is not empty, an idle register unit exists in the current register unit, the smallest unit address in the available_units list is taken and recorded as a register unit address allocated to the whish_qubit, and then a value corresponding to the address in the qreg is modified into the whish_qubit;
Step 3: and returning and outputting the updated register unit dictionary qreg of the unit state and the register unit address allocated to the whish_qubit.
Optionally, based on the target identifier, performing equivalent compiling on the operation instruction to obtain an operation instruction in a second quantum circuit equivalent to the operation instruction, where the operation instruction includes at least one of the following:
under the condition that the operation instruction is an operation instruction of quantum gate operation, based on the target identification, equivalently compiling the operation instruction into an operation instruction of quantum gate operation in a second quantum circuit;
and under the condition that the operation instruction is an operation instruction of quantum measurement operation, based on the target identification, equivalently compiling the operation instruction into an operation instruction of quantum measurement operation in a second quantum circuit, updating the register unit dictionary, and generating an operation instruction of reset operation in the second quantum circuit, wherein the updated register unit dictionary indicates that a register unit corresponding to the target identification is a register unit which is not allocated to a quantum bit.
Based on the dynamic allocation rule of the register unit, the equivalent compiling from the static quantum circuit to the dynamic quantum circuit can be realized, and the specific process is as follows:
Input: executing a static circuit instruction list static_circuit after optimizing the sequence;
and (3) outputting: the dynamic quantum circuit instruction list dynamic_circuit equivalent thereto.
Step 1: initializing an empty register unit dictionary qreg for recording the dynamic allocation state of each register unit; simultaneously initializing an empty list dynamic_circuit for recording a compiled dynamic quantum circuit instruction list;
step 2: traversing the input circuit instruction list static_circuit through a loop;
step 2.1: if the operation instruction operation traversed at present is singlequantumbit quantum operation, obtaining a quantum bit which_qubit acted by the operation at present, and taking the quantum bit which_qubit and qreg as inputs to obtain address of a register unit and updated qreg; generating a singlequbit operation circuit instruction gate= [ name, address, parameters, condition ], and then adding the singlequbit operation circuit instruction gate= [ name, address, parameters, condition ] into a dynamic quantum circuit instruction list dynamic_circuit;
step 2.2: if the current operation instruction operation is a measurement operation, acquiring a qubit which_qubit acted by the current operation, and taking the qubit which_qubit and qreg as inputs to acquire address of a register unit and updated qreg; generating a quantum circuit measurement instruction gate= [ measure, address, none ], and then adding the quantum circuit measurement instruction gate= [ measure, address, none ] into a dynamic quantum circuit instruction list dynamic_circuit; recovering a register unit corresponding to the address in the register unit dictionary qreg, namely modifying a value corresponding to an address key into None; generating a quantum circuit reset instruction gate= [ reset, address, none ], and then adding the quantum circuit reset instruction gate= [ reset, address, none ] into a dynamic quantum circuit instruction list dynamic_circuit;
Step 2.3: if the current operation instruction operation is a doublequantum bit operation, recording a first element in a whish_qubit list as whish_qubit_0 and recording a second element as whish_qubit_1; taking the whish_qubit_0 and qreg as inputs, obtaining an updated qreg dictionary, recording the output register unit address as address_0, taking the whish_qubit_1 and qreg as inputs, obtaining an updated qreg dictionary, and recording the output register unit address as address_1; generating a doublequantum bit operation circuit instruction gate= [ name, [ address_0, address_1], parameters, condition ], and then adding the doublequantum bit operation circuit instruction gate= [ name, [ address_0 ], address_1], parameters and condition into a dynamic quantum circuit instruction list dynamic_circuit;
step 3: after the input circuit instruction list static_circuit is traversed, a dynamic quantum circuit instruction list dynamic_circuit is returned and output.
In the above process, after compiling the measurement instruction, the register unit corresponding to the measurement instruction may be recovered for subsequent calculation.
In this embodiment, a quantum register is introduced to dynamically manage the use condition of each quantum bit of the dynamic quantum circuit, after all operations on a certain quantum bit are performed and measured, the quantum bit is reset, and the reset quantum bit is recovered and used in a subsequent calculation process, so that the width of the finally compiled dynamic quantum circuit can be ensured to be as small as possible, and the execution of a quantum algorithm on hardware is more facilitated.
To facilitate understanding of the scheme in this embodiment, a specific example is given.
An example of a static quantum circuit is shown in fig. 7, and after the equivalent compiling is performed by the quantum circuit processing method of the embodiment, the obtained dynamic quantum circuit is shown in fig. 8, compared with the static quantum circuit shown in fig. 7, the dynamic quantum circuit reduces two quantum bits, and the number of quantum bits required by the quantum circuit is greatly reduced.
The static quantum circuit shown in fig. 7 and the dynamic quantum circuit shown in fig. 8 are respectively simulated, and the operation results are shown in fig. 9, wherein the abscissa represents the measurement result of the quantum bit, the ordinate represents the probability distribution of the quantum bit sampling, the white bar represents the operation result of the static quantum circuit, and the black bar represents the operation result of the dynamic quantum circuit. It can be seen that the running results of the static qubit and the dynamic qubit are matched, so that the number of qubits used by the quantum circuit can be significantly reduced without affecting the running results.
Second embodiment
As shown in fig. 10, the present disclosure provides a quantum circuit processing apparatus 1000, comprising:
a first obtaining module 1001, configured to obtain a first instruction list of a first quantum circuit, where the first instruction list includes: the quantum gate operation control method comprises an operation instruction of quantum measurement operation and an operation instruction of quantum gate operation, wherein the operation instruction of quantum measurement operation is positioned behind the operation instruction of quantum gate operation;
A second obtaining module 1002, configured to obtain a dependency relationship of an execution sequence of an operation instruction of the first quantum circuit based on the first instruction list;
a reordering module 1003, configured to reorder the operation instructions of the first quantum circuit according to the order from small to large of the qubit labels acted by the operation instructions based on the dependency relationship, so as to obtain a second instruction list of the first quantum circuit;
an equivalent compiling module 1004, configured to perform equivalent compiling on the first quantum circuit based on the second instruction list, to obtain a third instruction list of the second quantum circuit equivalent to the first quantum circuit, where the third instruction list includes: and the operation instruction of the reset operation is positioned after the operation instruction of the quantum measurement operation, the reset operation is used for resetting the quantum state of the quantum bit to the zero state, and the quantum bit number of the second quantum circuit is smaller than that of the first quantum circuit.
Optionally, the second obtaining module 1002 includes:
the first acquisition submodule is used for acquiring the qubit acted by the operation instruction in the first instruction list;
The coding submodule is used for numbering the operation instructions based on the sequence of the quantum bits acted by the operation instructions in the quantum operation of the first quantum circuit, so as to obtain the numbering information of the operation instructions of the first quantum circuit;
and the searching submodule is used for searching other operation instructions related to the operation instructions in the first quantum circuit based on the serial number information of the operation instructions to obtain the dependency relationship, wherein the quantum bits acted by the other operation instructions comprise quantum bits acted by the operation instructions, and the execution sequence of the other operation instructions is before the operation instructions.
Optionally, the searching submodule is specifically configured to:
acquiring target number information based on the number information of the operation instruction, wherein the number of the qubit in the target number information is the same as the number of the qubit in the number information of the operation instruction, and the occurrence order of the qubit in the quantum operation of the first quantum circuit in the target number information is smaller than the occurrence order of the qubit in the quantum operation of the first quantum circuit in the number information of the operation instruction;
and acquiring the other operation instructions corresponding to the target number information to obtain the dependency relationship, wherein the other operation instructions are operation instructions which are executed in the first quantum circuit in sequence before the operation instructions and are adjacent to the operation instructions.
Optionally, the reordering module 1003 includes:
the first reordering submodule is used for carrying out first reordering on the operation instructions of the first quantum circuit according to the sequence from small to large on the quantum bit marks acted by the operation instructions to obtain a fourth instruction list of the first quantum circuit, wherein in the fourth instruction list, the marks of target quantum bits in the operation instructions sequenced in front are smaller than the marks of target quantum bits in the operation instructions sequenced in back, and the operation instructions with the same marks of the acted quantum bits are arranged according to the relative sequence of the operation instructions in the first quantum circuit, and the target quantum bits are the quantum bits with the small marks in the operation instructions;
and the second reordering submodule is used for performing second reordering on the fourth instruction list based on the dependency relationship to obtain the second instruction list.
Optionally, the second reordering submodule includes:
the splitting unit is used for traversing the fourth instruction list aiming at the operation instructions, splitting the fourth instruction list aiming at the currently traversed operation instructions to obtain a first list, a second list and a third list, wherein the first list is a list formed by ordering the operation instructions at the first position in the fourth instruction list to the previous operation instructions adjacent to the currently traversed operation instructions, the second list is a list formed by ordering the operation instructions after the currently traversed operation instructions in the fourth instruction list;
A rearrangement unit, configured to rearrange the operation instructions of the fourth instruction list based on a target dependency relationship between the currently traversed operation instruction and the operation instructions of the first quantum circuit, the first list, the second list, and the third list in the dependency relationship;
and the determining unit is used for determining the second instruction list based on the rearranged fourth instruction list under the condition that the fourth instruction list is traversed.
Optionally, the rearrangement unit is specifically configured to:
acquiring a first target list based on the target dependency relationship and the first list, wherein the first target list indicates an operation instruction with the target dependency relationship between the first list and the currently traversed operation instruction;
determining a third target list based on the first target list and a second target list, wherein the second target list indicates an operation instruction with the target dependency relationship between the fourth instruction list and the currently traversed operation instruction, and the third target list is a list obtained by deleting the first target list from the second target list;
Deleting an operation instruction indicated by the third target list from the third list to obtain a fourth list under the condition that the third target list is not an empty set;
and performing list splicing on the first list, the operation instruction indicated by the third target list, the second list and the fourth list according to the sequence from front to back to obtain a rearranged fourth instruction list.
Optionally, the reordering module 1003 further includes:
the moving submodule is used for moving the rearranged operation instructions of the quantum measurement operation in the fourth instruction list to a target position to obtain the second instruction list;
the target position is a position located after a target operation instruction in the rearranged fourth instruction list and adjacent to the target operation instruction, the qubit acted by the target operation instruction comprises the qubit acted by the operation instruction of the quantum measurement operation, and the operation instruction ordered after the target position in the second instruction list does not comprise the qubit acted by the operation instruction of the quantum measurement operation.
Optionally, the equivalent compiling module 1004 includes:
The second acquisition submodule is used for acquiring a quantum bit acted by each operation instruction in the second instruction list;
a determining submodule, configured to determine, based on the qubit and a register unit dictionary, a target identifier of a register unit of a second qucircuit allocated to the qubit, where the register unit dictionary includes a correspondence between a register unit and the qubit;
and the equivalent compiling submodule is used for carrying out equivalent compiling on the operation instruction based on the target identifier to obtain the operation instruction in the second quantum circuit equivalent to the operation instruction, and the third instruction list comprises the operation instruction in the second quantum circuit obtained by equivalent compiling.
Optionally, the determining submodule includes:
a first determining subunit, configured to determine, when it is queried that the register unit dictionary includes a correspondence of the qubit, an identifier of a register unit corresponding to the qubit as the target identifier;
and the second determining subunit is used for allocating the register units for the qubits based on the register unit dictionary, determining the identification of the register units allocated by the qubits as the target identification and updating the register unit dictionary based on the identification of the register units allocated by the qubits under the condition that the corresponding relation of the qubits is not included in the register unit dictionary.
Optionally, the second determining subunit is specifically configured to:
under the condition that the register unit dictionary comprises the identification of a first register unit, the first register unit is allocated to the qubit, and the first register unit is not allocated to a node;
and under the condition that the register unit dictionary does not comprise the identification of the first register unit, acquiring the number of the register units represented by the register unit dictionary, determining the identification of the created second register unit based on the number, and distributing the second register unit to the quantum bit.
Optionally, the first register unit is the smallest identified register unit among the register units not allocated to the node.
Optionally, the equivalent compiling submodule is specifically configured to:
under the condition that the operation instruction is an operation instruction of quantum gate operation, based on the target identification, equivalently compiling the operation instruction into an operation instruction of quantum gate operation in a second quantum circuit;
and under the condition that the operation instruction is an operation instruction of quantum measurement operation, based on the target identification, equivalently compiling the operation instruction into an operation instruction of quantum measurement operation in a second quantum circuit, updating the register unit dictionary, and generating an operation instruction of reset operation in the second quantum circuit, wherein the updated register unit dictionary indicates that a register unit corresponding to the target identification is a register unit which is not allocated to a quantum bit.
The quantum circuit processing apparatus 1000 provided in the present disclosure can implement each process implemented by the quantum circuit processing method embodiment, and can achieve the same beneficial effects, so that repetition is avoided, and no further description is provided herein.
In the technical scheme of the disclosure, the related processes of collecting, storing, using, processing, transmitting, providing, disclosing and the like of the personal information of the user accord with the regulations of related laws and regulations, and the public order colloquial is not violated.
According to embodiments of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.
FIG. 11 illustrates a schematic block diagram of an example electronic device that may be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.
As shown in fig. 11, the apparatus 1100 includes a computing unit 1101 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 1102 or a computer program loaded from a storage unit 1108 into a Random Access Memory (RAM) 1103. In the RAM 1103, various programs and data required for the operation of the device 1100 can also be stored. The computing unit 1101, ROM 1102, and RAM 1103 are connected to each other by a bus 1104. An input/output (I/O) interface 1105 is also connected to bus 1104.
Various components in device 1100 are connected to I/O interface 1105, including: an input unit 1106 such as a keyboard, a mouse, etc.; an output unit 1107 such as various types of displays, speakers, and the like; a storage unit 1108, such as a magnetic disk, optical disk, etc.; and a communication unit 1109 such as a network card, modem, wireless communication transceiver, or the like. The communication unit 1109 allows the device 1100 to exchange information/data with other devices through a computer network such as the internet and/or various telecommunication networks.
The computing unit 1101 may be a variety of general purpose and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 1101 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 1101 performs the respective methods and processes described above, such as a quantum circuit processing method. For example, in some embodiments, the quantum circuit processing method may be implemented as a computer software program tangibly embodied on a machinereadable medium, such as storage unit 1108. In some embodiments, some or all of the computer programs may be loaded and/or installed onto device 1100 via ROM 1102 and/or communication unit 1109. When a computer program is loaded into the RAM 1103 and executed by the computing unit 1101, one or more steps of the quantum circuit processing method described above may be performed. Alternatively, in other embodiments, the computing unit 1101 may be configured to perform the quantum circuit processing method by any other suitable means (e.g. by means of firmware).
Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or generalpurpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.
Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a standalone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of this disclosure, a machinereadable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machinereadable medium may be a machinereadable signal medium or a machinereadable storage medium. The machinereadable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machinereadable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a readonly memory (ROM), an erasable programmable readonly memory (EPROM or flash memory), an optical fiber, a portable compact disc readonly memory (CDROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.
The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a frontend component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or frontend components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.
The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a clientserver relationship to each other. The server may be a cloud server, a server of a distributed system, or a server incorporating a blockchain.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel, sequentially, or in a different order, provided that the desired results of the disclosed aspects are achieved, and are not limited herein.
The above detailed description should not be taken as limiting the scope of the present disclosure. It will be apparent to those skilled in the art that various modifications, combinations, subcombinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.
Claims (27)
1. A quantum circuit processing method, comprising:
obtaining a first instruction list of a first quantum circuit, the first instruction list comprising: the quantum gate operation control method comprises an operation instruction of quantum measurement operation and an operation instruction of quantum gate operation, wherein the operation instruction of quantum measurement operation is positioned behind the operation instruction of quantum gate operation;
based on the first instruction list, acquiring a dependency relationship of an execution sequence of an operation instruction of the first quantum circuit; the dependency relationship of the execution sequence of the operation instructions of the first quantum circuit refers to the operation instructions which have to be executed before the current operation instructions in the first quantum circuit are executed;
Based on the dependency relationship, reordering the operation instructions of the first quantum circuit according to the sequence from small to large of the qubit marks acted by the operation instructions to obtain a second instruction list of the first quantum circuit;
based on the second instruction list, performing equivalent compiling on the first quantum circuit to obtain a third instruction list of a second quantum circuit equivalent to the first quantum circuit, wherein the third instruction list comprises: an operation instruction of a reset operation, wherein the operation instruction of the reset operation is positioned after the operation instruction of the quantum measurement operation, the reset operation is used for resetting the quantum state of the quantum bit to the zero state, and the quantum bit number of the second quantum circuit is smaller than that of the first quantum circuit;
the performing equivalent compiling on the first quantum circuit based on the second instruction list to obtain a third instruction list of a second quantum circuit equivalent to the first quantum circuit, including:
for each operation instruction in the second instruction list, performing equivalent compiling on the operation instruction based on a register unit allocated for a qubit acted by the operation instruction so as to compile the operation instruction into an operation instruction in a second quantum circuit equivalent to the operation instruction, and obtaining a third instruction list of the second quantum circuit equivalent to the first quantum circuit;
In the equivalent compiling process, an operation instruction of a reset operation is added after an operation instruction of a quantum measurement operation after equivalent compiling, so that a register unit of a quantum bit acted by the operation instruction of the quantum measurement operation is recovered, and the register unit is reassigned to the quantum bit acted by an uncompiled operation instruction in the second instruction list.
2. The method of claim 1, wherein the obtaining, based on the first instruction list, a dependency of an order of execution of the operation instructions of the first quantum circuit comprises:
acquiring a qubit acted by an operation instruction in the first instruction list;
numbering the operation instructions based on the order in which the qubits acted by the operation instructions appear in the quantum operations of the first quantum circuit, so as to obtain the numbering information of the operation instructions of the first quantum circuit;
and searching other operation instructions related to the operation instructions in the first quantum circuit based on the serial number information of the operation instructions to obtain the dependency relationship, wherein the quantum bits acted by the other operation instructions comprise quantum bits acted by the operation instructions, and the execution sequence of the other operation instructions is before the operation instructions.
3. The method of claim 2, wherein the looking up other operation instructions associated with the operation instructions in the first quantum circuit based on the number information of the operation instructions to obtain the dependency relationship includes:
acquiring target number information based on the number information of the operation instruction, wherein the number of the qubit in the target number information is the same as the number of the qubit in the number information of the operation instruction, and the occurrence order of the qubit in the quantum operation of the first quantum circuit in the target number information is smaller than the occurrence order of the qubit in the quantum operation of the first quantum circuit in the number information of the operation instruction;
and acquiring the other operation instructions corresponding to the target number information to obtain the dependency relationship, wherein the other operation instructions are operation instructions which are executed in the first quantum circuit in sequence before the operation instructions and are adjacent to the operation instructions.
4. The method of claim 1, wherein the reordering the operation instructions of the first quantum circuit in order of the qubit labels acted on by the operation instructions from small to large based on the dependency relationship, to obtain the second instruction list of the first quantum circuit, comprises:
First reordering the operation instructions of the first quantum circuit according to the sequence from small to large of the quantum bit marks acted by the operation instructions to obtain a fourth instruction list of the first quantum circuit, wherein in the fourth instruction list, the marks of target quantum bits in the operation instructions ordered before are smaller than the marks of target quantum bits in the operation instructions ordered after, and the operation instructions with the same marks of the acted quantum bits are arranged according to the relative sequence of the operation instructions in the first quantum circuit, and the target quantum bits are the quantum bits with small marks in the operation instructions;
and based on the dependency relationship, performing second reordering on the fourth instruction list to obtain the second instruction list.
5. The method of claim 4, wherein the second reordering the fourth instruction list based on the dependency relationship to obtain the second instruction list comprises:
traversing the fourth instruction list aiming at operation instructions, splitting the fourth instruction list aiming at the operation instructions which are currently traversed to obtain a first list, a second list and a third list, wherein the first list is a list formed by the operation instructions which are sequenced in the first position in the fourth instruction list to the previous operation instructions adjacent to the operation instructions which are currently traversed, the second list is a list formed by the operation instructions which are currently traversed, and the third list is a list formed by the operation instructions which are sequenced in the fourth instruction list and are sequenced after the operation instructions which are currently traversed;
Based on a target dependency relationship between the currently traversed operation instruction and the operation instruction of the first quantum circuit, the first list, the second list and the third list in the dependency relationship, rearranging the operation instruction of the fourth instruction list;
and determining the second instruction list based on the rearranged fourth instruction list under the condition that the fourth instruction list traversal is completed.
6. The method of claim 5, wherein the reordering of the fourth list of instructions of operations based on a target dependency between the currently traversed instruction of operations in the dependency and the instructions of operations of the first quantum circuit, the first list, the second list, and the third list comprises:
acquiring a first target list based on the target dependency relationship and the first list, wherein the first target list indicates an operation instruction with the target dependency relationship between the first list and the currently traversed operation instruction;
determining a third target list based on the first target list and a second target list, wherein the second target list indicates an operation instruction with the target dependency relationship between the fourth instruction list and the currently traversed operation instruction, and the third target list is a list obtained by deleting the first target list from the second target list;
Deleting an operation instruction indicated by the third target list from the third list to obtain a fourth list under the condition that the third target list is not an empty set;
and performing list splicing on the first list, the operation instruction indicated by the third target list, the second list and the fourth list according to the sequence from front to back to obtain a rearranged fourth instruction list.
7. The method of claim 4, wherein the second reordering of the fourth list of instructions based on the dependency further comprises:
moving the operation instruction of the quantum measurement operation in the rearranged fourth instruction list to a target position to obtain a second instruction list;
the target position is a position located after a target operation instruction in the rearranged fourth instruction list and adjacent to the target operation instruction, the qubit acted by the target operation instruction comprises the qubit acted by the operation instruction of the quantum measurement operation, and the operation instruction ordered after the target position in the second instruction list does not comprise the qubit acted by the operation instruction of the quantum measurement operation.
8. The method of claim 1, wherein the equivalently compiling the first quantum circuit based on the second instruction list to obtain a third instruction list of a second quantum circuit equivalent to the first quantum circuit, comprises:
for each operation instruction in the second instruction list, executing the following operation:
obtaining a qubit acted by the operation instruction;
determining a target identification of a register unit of a second quantum circuit allocated for the quantum bit based on the quantum bit and a register unit dictionary, wherein the register unit dictionary comprises a corresponding relation between the register unit and the quantum bit;
and based on the target identification, performing equivalent compiling on the operation instruction to obtain an operation instruction in a second quantum circuit equivalent to the operation instruction, wherein the third instruction list comprises the operation instruction in the second quantum circuit obtained by equivalent compiling.
9. The method of claim 8, wherein the determining, based on the qubit and register unit dictionary, a target identification of a register unit of a second quantum circuit allocated for the qubit comprises at least one of:
under the condition that the corresponding relation of the quantum bit is included in the register unit dictionary, determining the identification of the register unit corresponding to the quantum bit as the target identification;
And under the condition that the corresponding relation of the quantum bit is not included in the register unit dictionary, distributing the register unit for the quantum bit based on the register unit dictionary, determining the identification of the register unit distributed by the quantum bit as the target identification, and updating the register unit dictionary based on the identification of the register unit distributed by the quantum bit.
10. The method of claim 9, wherein the assigning register units to the qubits based on the register unit dictionary comprises at least one of:
under the condition that the register unit dictionary comprises the identification of a first register unit, the first register unit is allocated to the qubit, and the first register unit is not allocated to a node;
and under the condition that the register unit dictionary does not comprise the identification of the first register unit, acquiring the number of the register units represented by the register unit dictionary, determining the identification of the created second register unit based on the number, and distributing the second register unit to the quantum bit.
11. The method of claim 10, wherein the first register unit is a leastidentified register unit of the register units not allocated to the node.
12. The method of claim 8, wherein the equivalently compiling the operation instruction based on the target identifier, to obtain an operation instruction in a second quantum circuit equivalent to the operation instruction, includes at least one of:
under the condition that the operation instruction is an operation instruction of quantum gate operation, based on the target identification, equivalently compiling the operation instruction into an operation instruction of quantum gate operation in a second quantum circuit;
and under the condition that the operation instruction is an operation instruction of quantum measurement operation, based on the target identification, equivalently compiling the operation instruction into an operation instruction of quantum measurement operation in a second quantum circuit, updating the register unit dictionary, and generating an operation instruction of reset operation in the second quantum circuit, wherein the updated register unit dictionary indicates that a register unit corresponding to the target identification is a register unit which is not allocated to a quantum bit.
13. A quantum circuit processing apparatus comprising:
a first obtaining module, configured to obtain a first instruction list of a first quantum circuit, where the first instruction list includes: the quantum gate operation control method comprises an operation instruction of quantum measurement operation and an operation instruction of quantum gate operation, wherein the operation instruction of quantum measurement operation is positioned behind the operation instruction of quantum gate operation;
The second acquisition module is used for acquiring the dependency relationship of the execution sequence of the operation instruction of the first quantum circuit based on the first instruction list; the dependency relationship of the execution sequence of the operation instructions of the first quantum circuit refers to the operation instructions which have to be executed before the current operation instructions in the first quantum circuit are executed;
the reordering module is used for reordering the operation instructions of the first quantum circuit according to the sequence from small to large of the quantum bit marks acted by the operation instructions based on the dependency relationship, so as to obtain a second instruction list of the first quantum circuit;
the equivalent compiling module is configured to perform equivalent compiling on the first quantum circuit based on the second instruction list, and obtain a third instruction list of the second quantum circuit equivalent to the first quantum circuit, where the third instruction list includes: an operation instruction of a reset operation, wherein the operation instruction of the reset operation is positioned after the operation instruction of the quantum measurement operation, the reset operation is used for resetting the quantum state of the quantum bit to the zero state, and the quantum bit number of the second quantum circuit is smaller than that of the first quantum circuit;
The equivalent compiling module is specifically configured to:
for each operation instruction in the second instruction list, performing equivalent compiling on the operation instruction based on a register unit allocated for a qubit acted by the operation instruction so as to compile the operation instruction into an operation instruction in a second quantum circuit equivalent to the operation instruction, and obtaining a third instruction list of the second quantum circuit equivalent to the first quantum circuit;
in the equivalent compiling process, an operation instruction of a reset operation is added after an operation instruction of a quantum measurement operation after equivalent compiling, so that a register unit of a quantum bit acted by the operation instruction of the quantum measurement operation is recovered, and the register unit is reassigned to the quantum bit acted by an uncompiled operation instruction in the second instruction list.
14. The apparatus of claim 13, wherein the second acquisition module comprises:
the first acquisition submodule is used for acquiring the qubit acted by the operation instruction in the first instruction list;
the coding submodule is used for numbering the operation instructions based on the sequence of the quantum bits acted by the operation instructions in the quantum operation of the first quantum circuit, so as to obtain the numbering information of the operation instructions of the first quantum circuit;
And the searching submodule is used for searching other operation instructions related to the operation instructions in the first quantum circuit based on the serial number information of the operation instructions to obtain the dependency relationship, wherein the quantum bits acted by the other operation instructions comprise quantum bits acted by the operation instructions, and the execution sequence of the other operation instructions is before the operation instructions.
15. The apparatus of claim 14, wherein the lookup submodule is specifically configured to:
acquiring target number information based on the number information of the operation instruction, wherein the number of the qubit in the target number information is the same as the number of the qubit in the number information of the operation instruction, and the occurrence order of the qubit in the quantum operation of the first quantum circuit in the target number information is smaller than the occurrence order of the qubit in the quantum operation of the first quantum circuit in the number information of the operation instruction;
and acquiring the other operation instructions corresponding to the target number information to obtain the dependency relationship, wherein the other operation instructions are operation instructions which are executed in the first quantum circuit in sequence before the operation instructions and are adjacent to the operation instructions.
16. The apparatus of claim 13, wherein the reordering module comprises:
the first reordering submodule is used for carrying out first reordering on the operation instructions of the first quantum circuit according to the sequence from small to large on the quantum bit marks acted by the operation instructions to obtain a fourth instruction list of the first quantum circuit, wherein in the fourth instruction list, the marks of target quantum bits in the operation instructions sequenced in front are smaller than the marks of target quantum bits in the operation instructions sequenced in back, and the operation instructions with the same marks of the acted quantum bits are arranged according to the relative sequence of the operation instructions in the first quantum circuit, and the target quantum bits are the quantum bits with the small marks in the operation instructions;
and the second reordering submodule is used for performing second reordering on the fourth instruction list based on the dependency relationship to obtain the second instruction list.
17. The apparatus of claim 16, wherein the second reordering submodule comprises:
the splitting unit is used for traversing the fourth instruction list aiming at the operation instructions, splitting the fourth instruction list aiming at the currently traversed operation instructions to obtain a first list, a second list and a third list, wherein the first list is a list formed by ordering the operation instructions at the first position in the fourth instruction list to the previous operation instructions adjacent to the currently traversed operation instructions, the second list is a list formed by ordering the operation instructions after the currently traversed operation instructions in the fourth instruction list;
A rearrangement unit, configured to rearrange the operation instructions of the fourth instruction list based on a target dependency relationship between the currently traversed operation instruction and the operation instructions of the first quantum circuit, the first list, the second list, and the third list in the dependency relationship;
and the determining unit is used for determining the second instruction list based on the rearranged fourth instruction list under the condition that the fourth instruction list is traversed.
18. The device according to claim 17, wherein the rearrangement unit is specifically configured to:
acquiring a first target list based on the target dependency relationship and the first list, wherein the first target list indicates an operation instruction with the target dependency relationship between the first list and the currently traversed operation instruction;
determining a third target list based on the first target list and a second target list, wherein the second target list indicates an operation instruction with the target dependency relationship between the fourth instruction list and the currently traversed operation instruction, and the third target list is a list obtained by deleting the first target list from the second target list;
Deleting an operation instruction indicated by the third target list from the third list to obtain a fourth list under the condition that the third target list is not an empty set;
and performing list splicing on the first list, the operation instruction indicated by the third target list, the second list and the fourth list according to the sequence from front to back to obtain a rearranged fourth instruction list.
19. The apparatus of claim 16, wherein the reordering module further comprises:
the moving submodule is used for moving the rearranged operation instructions of the quantum measurement operation in the fourth instruction list to a target position to obtain the second instruction list;
the target position is a position located after a target operation instruction in the rearranged fourth instruction list and adjacent to the target operation instruction, the qubit acted by the target operation instruction comprises the qubit acted by the operation instruction of the quantum measurement operation, and the operation instruction ordered after the target position in the second instruction list does not comprise the qubit acted by the operation instruction of the quantum measurement operation.
20. The apparatus of claim 13, wherein the equivalent compiling module comprises:
The second acquisition submodule is used for acquiring a quantum bit acted by each operation instruction in the second instruction list;
a determining submodule, configured to determine, based on the qubit and a register unit dictionary, a target identifier of a register unit of a second qucircuit allocated to the qubit, where the register unit dictionary includes a correspondence between a register unit and the qubit;
and the equivalent compiling submodule is used for carrying out equivalent compiling on the operation instruction based on the target identifier to obtain the operation instruction in the second quantum circuit equivalent to the operation instruction, and the third instruction list comprises the operation instruction in the second quantum circuit obtained by equivalent compiling.
21. The apparatus of claim 20, wherein the determination submodule comprises:
a first determining subunit, configured to determine, when it is queried that the register unit dictionary includes a correspondence of the qubit, an identifier of a register unit corresponding to the qubit as the target identifier;
and the second determining subunit is used for allocating the register units for the qubits based on the register unit dictionary, determining the identification of the register units allocated by the qubits as the target identification and updating the register unit dictionary based on the identification of the register units allocated by the qubits under the condition that the corresponding relation of the qubits is not included in the register unit dictionary.
22. The apparatus of claim 21, wherein the second determining subunit is specifically configured to:
under the condition that the register unit dictionary comprises the identification of a first register unit, the first register unit is allocated to the qubit, and the first register unit is not allocated to a node;
and under the condition that the register unit dictionary does not comprise the identification of the first register unit, acquiring the number of the register units represented by the register unit dictionary, determining the identification of the created second register unit based on the number, and distributing the second register unit to the quantum bit.
23. The apparatus of claim 22, wherein the first register unit is a leastidentified register unit of the register units not allocated to the node.
24. The apparatus of claim 20, wherein the equivalent compiling submodule is specifically configured to:
under the condition that the operation instruction is an operation instruction of quantum gate operation, based on the target identification, equivalently compiling the operation instruction into an operation instruction of quantum gate operation in a second quantum circuit;
and under the condition that the operation instruction is an operation instruction of quantum measurement operation, based on the target identification, equivalently compiling the operation instruction into an operation instruction of quantum measurement operation in a second quantum circuit, updating the register unit dictionary, and generating an operation instruction of reset operation in the second quantum circuit, wherein the updated register unit dictionary indicates that a register unit corresponding to the target identification is a register unit which is not allocated to a quantum bit.
25. An electronic device, comprising:
at least one processor; and
a memory communicatively coupled to the at least one processor; wherein,,
the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 112.
26. A nontransitory computer readable storage medium storing computer instructions for causing the computer to perform the method of any one of claims 112.
27. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any of claims 112.
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