CN117313877A

CN117313877A - Quantum circuit processing method and device and electronic equipment

Info

Publication number: CN117313877A
Application number: CN202311264893.6A
Authority: CN
Inventors: 方堃
Original assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Current assignee: Beijing Baidu Netcom Science and Technology Co Ltd
Priority date: 2023-09-27
Filing date: 2023-09-27
Publication date: 2023-12-29

Abstract

The disclosure provides a quantum circuit processing method, a quantum circuit processing device and electronic equipment, relates to the technical field of quantum computing, and particularly relates to the technical field of quantum circuits. The specific implementation scheme is as follows: acquiring a first instruction list of a first quantum circuit comprising 2N quantum bits, wherein the first quantum circuit is a quantum circuit with a combined structure or a sub-circuit of the quantum circuit with the combined structure; based on the first instruction list, performing equivalent compiling on the first quantum circuit to obtain a second instruction list of the second quantum circuit; equivalent compilation includes: adding a first reset operation instruction after the first measurement operation instruction in the first instruction list; remapping each first target operating instruction in the first instruction list to a qubit of the qubit i; adding a second reset operation instruction after the second measurement operation instruction in the first instruction list; each second target operating instruction in the first instruction list is remapped to a qubit of qubit n+h.

Description

Quantum circuit processing method and device and electronic equipment

Technical Field

The disclosure relates to the technical field of quantum computing, in particular to the technical field of quantum circuits, and specifically relates to a quantum circuit processing method, a quantum circuit processing device and electronic equipment.

Background

The quantum computing provides a brand new and very promising information processing mode by utilizing the specific operation rule in the quantum world. Quantum algorithms can offer advantages over classical algorithms over a number of specific problems. For example, large integers can be efficiently decomposed using the schiff (shell) algorithm, and data search can be performed faster using the Grover (Grover) algorithm. With the development of quantum theory, new quantum algorithms are continuously proposed, and how to efficiently simulate the algorithms or run the algorithms on real quantum hardware is always an important problem.

Classical simulation or true operation of quantum algorithms is mainly limited by the number of qubits. In classical simulation, since the length of the column vector describing the quantum state grows exponentially with the corresponding number of bits (e.g., the length of the column vector of an n-bit quantum state is 2 ⁿ ) Classical computers have difficulty simulating large-scale quantum algorithms. The existing quantum circuit simulation mode can support an algorithm for simulating tens of quantum bits at most under the limitation of the memory and the processor capacity of a computer.

Currently, a heuristic algorithm is generally adopted to perform equivalent compiling on a quantum circuit, so as to obtain a dynamic quantum circuit equivalent to the quantum circuit.

Disclosure of Invention

The disclosure provides a quantum circuit processing method, a quantum circuit processing device and electronic equipment.

According to a first aspect of the present disclosure, there is provided a quantum circuit processing method, comprising:

obtaining a first instruction list of a first quantum circuit comprising 2N quantum bits, the first quantum circuit being: a quantum circuit of a combined structure or a sub-circuit of the quantum circuit of the combined structure, wherein 2N quantum bits are sequentially arranged according to quantum bits from 0 to 2N-1 of the quantum bits, a first double-quantum bit gate is sequentially acted between the quantum bits of the quantum bits j and the quantum bits of the quantum bits n+j according to the sequence from j to big, a second double-quantum bit gate is sequentially acted between the quantum bits of the quantum bits 0 and the quantum bits of the quantum bits n+j according to the sequence from j to big, the second double-quantum bit gate is positioned behind the first double-quantum bit gate in the quantum state time evolution direction, the value range of j is [0, N-1], and the sub-circuit is a quantum circuit obtained by deleting part of operation instructions from an instruction list of the quantum circuit of the combined structure, and N is an integer greater than or equal to 2;

Based on the first instruction list, performing equivalent compiling on the first quantum circuit to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit;

wherein the number of qubits of the second quantum circuit is smaller than the number of qubits of the first quantum circuit, the equivalent compilation comprising: adding a first reset operation instruction after a first measurement operation instruction in the first instruction list; remapping each first target operation instruction in the first instruction list to a qubit of a qubit i, wherein the first measurement operation instruction and the first reset operation instruction both act on the qubit i, and the first target operation instruction acts on the qubit i+1; and adding a second reset operation instruction after the second measurement operation instruction in the first instruction list; and remapping each second target operation instruction in the first instruction list to a quantum bit of a quantum bit N+h, wherein the second measurement operation instruction and the second reset operation instruction both act on the quantum bit N+h, the second target operation instruction acts on the quantum bit N+h+1, the value range of i is [1, N-2], and the value range of h is [0, N-2].

According to a second aspect of the present disclosure, there is provided a quantum circuit processing apparatus comprising:

an acquisition module, configured to acquire a first instruction list of a first quantum circuit including 2N quantum bits, the first quantum circuit being: a quantum circuit of a combined structure or a sub-circuit of the quantum circuit of the combined structure, wherein 2N quantum bits are sequentially arranged according to quantum bits from 0 to 2N-1 of the quantum bits, a first double-quantum bit gate is sequentially acted between the quantum bits of the quantum bits j and the quantum bits of the quantum bits n+j according to the sequence from j to big, a second double-quantum bit gate is sequentially acted between the quantum bits of the quantum bits 0 and the quantum bits of the quantum bits n+j according to the sequence from j to big, the second double-quantum bit gate is positioned behind the first double-quantum bit gate in the quantum state time evolution direction, the value range of j is [0, N-1], and the sub-circuit is a quantum circuit obtained by deleting part of operation instructions from an instruction list of the quantum circuit of the combined structure, and N is an integer greater than or equal to 2;

the equivalent compiling module is used for carrying out equivalent compiling on the first quantum circuit based on the first instruction list to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit;

According to a third aspect of the present disclosure, there is provided an electronic device comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

The memory stores instructions executable by the at least one processor to enable the at least one processor to perform any one of the methods of the first aspect.

According to a fourth aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform any of the methods of the first aspect.

According to a fifth aspect of the present disclosure, there is provided a computer program product comprising a computer program which, when executed by a processor, implements any of the methods of the first aspect.

The technology solves the problem that classical simulation and true operation of the quantum circuits of the combined structure and the sub-circuits of the quantum circuits of the combined structure are difficult in the related technology, can realize optimal compilation of the quantum circuits of the combined structure and the sub-circuits of the quantum circuits of the combined structure, so that the width of the compiled quantum circuits can be minimized, namely, the quantum circuits of one combined structure or the sub-circuits of the quantum circuits of one combined structure can be compiled into a dynamic quantum circuit with the minimum number of required quantum bits equivalent to the quantum circuits of the combined structure, thereby simplifying classical simulation and true operation of the quantum circuits of the combined structure and the sub-circuits of the quantum circuits of the combined structure.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the disclosure, nor is it intended to be used to limit the scope of the disclosure. Other features of the present disclosure will become apparent from the following specification.

Drawings

The drawings are for a better understanding of the present solution and are not to be construed as limiting the present disclosure. Wherein:

fig. 1 is a flow diagram of a quantum circuit processing method according to a first embodiment of the present disclosure;

FIG. 2 is a schematic diagram of an exemplary static quantum circuit;

FIG. 3 is a schematic diagram of another example static quantum circuit structure;

FIG. 4 is a schematic diagram of a compiled dynamic quantum circuit of the quantum circuit of FIG. 3;

FIG. 5 is a schematic diagram of a quantum circuit of an exemplary combined structure;

FIG. 6 is a schematic diagram of a quantum circuit of another example combined structure;

FIG. 7 is a schematic diagram of a sub-circuit of a quantum circuit of an exemplary combined structure;

FIG. 8 is a schematic diagram of a compiled dynamic quantum circuit of the quantum circuit of FIG. 6;

fig. 9 is a schematic structural view of a quantum circuit processing apparatus according to a second embodiment of the present disclosure;

fig. 10 is a schematic block diagram of an example electronic device used to implement embodiments of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to facilitate understanding, and should be considered as merely exemplary. Accordingly, one of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

First embodiment

As shown in fig. 1, the present disclosure provides a quantum circuit processing method, including the steps of:

step S101: obtaining a first instruction list of a first quantum circuit comprising 2N quantum bits, the first quantum circuit being: the quantum circuit of the combined structure or the sub-circuit of the quantum circuit of the combined structure, 2N quantum bits are sequentially arranged according to quantum bits of quantum bit 0 to quantum bits of quantum bit 2N-1, a first double-quantum bit gate is sequentially acted between the quantum bits of quantum bit j and the quantum bits of quantum bit n+j according to the sequence of j from small to large in the combined structure, a second double-quantum bit gate is acted between the quantum bits of quantum bit 0 and the quantum bits of quantum bit n+j according to the sequence of j from small to large in the combined structure, the second double-quantum bit gate is positioned behind the first double-quantum bit gate in the quantum state time evolution direction, the value range of j is [0, N-1], and the sub-circuit is a quantum circuit obtained by deleting part of operation instructions from an instruction list of the quantum circuit of the combined structure, and N is an integer greater than or equal to 2.

In this embodiment, the quantum circuit processing method relates to the technical field of quantum computing, in particular to the technical field of quantum circuits, and can be widely applied to quantum circuits with combined structures and classical simulation and true operation scenes of sub-circuits of the quantum circuits with combined structures. The quantum circuit processing method of the embodiment of the present disclosure may be performed by the quantum circuit processing apparatus of the embodiment of the present disclosure. The quantum circuit processing apparatus of the embodiments of the present disclosure may be configured in any electronic device to perform the quantum circuit processing method of the embodiments of the present disclosure.

Currently, the mainstream quantum computing implementation is based on a quantum circuit model, that is, a series of quantum gates act on the quantum bits to complete the evolution of the quantum state, and quantum measurement is performed at the end of the circuit to obtain a computing result. The quantum circuits currently in common use in the industry are static quantum circuits, i.e. quantum circuits that contain measurement operations only at the ends of the circuit.

With the recent rapid development of hardware (mainly the significant increase of the coherence time of qubits and the realization of high-fidelity intermediate state measurement and reset operations), dynamic quantum circuits including intermediate measurement and reset operations have been increasingly receiving attention from the industry. Due to the introduction of intermediate measurement of the circuit, the dynamic quantum circuit can effectively combine quantum computation with real-time classical computation and communication within the coherence time of the quantum bit. This feature greatly increases the variety of computational tasks that can be accomplished by quantum circuit models. For example, with intermediate measurements of dynamic quantum circuits, a feed-forward operation may be implemented in the circuit operation, i.e. deciding what quantum gate to act next based on the results obtained from the intermediate measurements, or discarding the current calculation results to restart the calculation task. Such functionality is very important in quantum error correction and fault tolerant quantum computing. It is therefore expected that dynamic quantum circuits will become an important component of various quantum algorithms and quantum applications in the future.

Since the qubits in the dynamic quantum circuit can be reset and used continuously in the subsequent calculation process, the dynamic quantum circuit can effectively reduce the number of the qubits required for the calculation task without any influence on the calculation capability in theory compared with the static quantum circuit under the condition of running the same quantum algorithm. For example, the Berstein-Vazirani algorithm, which requires n qubits in static circuits, can be implemented with only 2 qubits in dynamic quantum circuits.

The existing quantum circuit simulation mode can support an algorithm for simulating tens of quantum bits at most under the limitation of the memory and the processor capacity of a computer. For example, notebooks can simulate around 20-30 qubits, and large supercomputers and clusters can simulate up to around 30-40 qubits. On the true machine operation, the problem of scalability of the current quantum chip is not solved, so that the number of quantum bits which can be provided by a quantum computer is very limited. Quantum circuit optimization is therefore a fundamental problem in the field of quantum computing.

The quantum circuit optimization is to equivalently compile a given quantum circuit into a dynamic quantum circuit by a certain technical means so as to reduce the number of quantum bits, thus reducing the requirements of classical simulation and true operation of the quantum circuit and accelerating the research of quantum algorithm and the landing of quantum calculation in an actual scene.

In this embodiment, the quantum circuit of the combined structure or the sub-circuit of the quantum circuit of the combined structure is compiled, so that the original quantum circuit can be greatly simplified in terms of the number of qubits. On one hand, the scale of the classical simulation of the quantum algorithm can be further improved, the verification capability of a classical computer on the quantum algorithm is enhanced, on the other hand, the bit number requirement of the quantum algorithm on the true machine operation can be reduced, and the defect of expandability of the current quantum chip is overcome. The quantum circuits of the combined structure, and the sub-circuits of the quantum circuits of the combined structure are important in the use scenarios of quantum algorithms such as Simon algorithm and the like.

The quantum circuit model is described in detail below.

Currently, quantum computing implementations can be based on quantum circuit models, i.e., the evolution of the quantum states is accomplished by acting a series of quantum gates on the qubits, and quantum measurements are made at the ends of the circuit to obtain the computation results. The quantum circuit diagram may represent the overall process of quantum circuit model computation.

Fig. 2 is a schematic diagram of an exemplary quantum circuit, and as shown in fig. 2, a qubit system may be represented by a horizontal line, where qubits of a qubit are numbered sequentially from top to bottom, where the qubit is often numbered from zero.

The time evolution direction in the quantum circuit diagram is from left to right, the leftmost end is an initial quantum state, wherein each quantum bit is initialized to be a zero state, and then different quantum gate operations are sequentially applied to the initial state to complete the evolution of the quantum state. Meanwhile, quantum measurement can be carried out on some qubits, and measurement results are obtained.

If one quantum circuit does not include operations such as reset and intermediate quantum measurement, and all measurement operations are located at the extreme end of the quantum circuit, such a quantum circuit is referred to as a static quantum circuit, and the quantum circuit shown in fig. 2 is referred to as a static quantum circuit.

The operations in a quantum circuit diagram may generally be represented in order of action by an ordered list of instructions, each element of the list representing an instruction for an operation.

Each quantum state preparation (or initialization) operation is represented as an instruction [ Reset, qubit, none ] containing four elements. For example, [ Reset,2, none ] means initializing the qubit of qubit 2 to a zero state.

Each single bit quantum gate (e.g., H, X, Y, Z, S, T, rx, ry, rz, etc.) is represented as an operation instruction [ name, qubit, parameter, condition ], where name is the name of the quantum gate, qubit is the qubit that the quantum gate acts on, parameter is the parameter of the quantum gate (default to None if no parameter is present), which indicates which qubit measurement the operation of the quantum gate is controlled by (default to None in standard quantum circuits). For example, [ Rx,2, pi, none ] represents acting an Rx rotation gate on the qubit on qubit 2, with a rotation angle pi.

Each two-bit quantum gate (e.g., control not gate CNOT, SWAP gate) is represented as an instruction containing four elements. Wherein name is the name of the quantum gate, qubit is a list of control bits and controlled bits, parameter is the parameter of the quantum gate (if no parameter is default to None), and condition parameter in the standard quantum circuit is default to None. For example, [ SWAP, [1,2], none ] represents the action of a SWAP gate between qubits 1 and 2; [ CNOT, [1,3], none ] represents a control NOT acting on qubit 1 and qubit 3, where qubit 1 is the control bit and qubit 3 is the control bit.

More generally, each multiple-quantum bit gate (e.g., CCX gate) is represented as an instruction containing four elements [ name, qubit, parameter, condition ]. Where name is the name of the quantum gate, qubit is a list of qubits acted on by the multiple quantum bit gate, parameter is a parameter of the quantum gate (no if there is no parameter), and condition indicates which qubit measurement the quantum gate operation is controlled by (None if there is no parameter).

The measurement under each computation is represented as an instruction containing four elements [ measure, qubit, none ]. For example, [ measure,2, none ] represents a measurement based on the calculation of qubit 2.

According to the instruction representation rules as above, the static quantum circuit in fig. 2 can be represented as an ordered list of instructions as follows: static_circuit= [ [ Reset,0, none ], [ Reset,1, none ], [ Reset,2, none ], [ H,0, none ], [ H,1, none ], [ H,2, none ], [ CNOT, [0,1], none ], [ SWAP, [1,2], none, none ], [ Rx,0, α, none ], [ Ry,1, β, none ], [ Rz,2, γ, none ], [ Measure,0, none, none ], [ Measure,1, none, none ], [ Measure,2, none, none ] ].

In some application scenarios, it may be allowed to measure some qubits in the middle of the quantum circuit and reset them to the |0 > state after the measurement results for continued use by subsequent computations. And a quantum circuit that includes a circuit intermediate measurement and a reset operation is called a dynamic quantum circuit.

The static quantum circuit can be compiled into the dynamic quantum circuit through quantum circuit optimization, for example, the static quantum circuit shown in fig. 3 can be equivalently compiled into the dynamic quantum circuit shown in fig. 4, and compared with the original static quantum circuit, the number of quantum bits of the dynamic quantum circuit is reduced by one, but the operation effects of the two quantum circuits are equivalent.

The instruction list of the original static quantum circuit is as follows: static_circuit= [ [ Reset,0, none ], [ Reset,1, none ], [ Reset,2, none ], [ H,0, none ], [ H,1, none ], [ H,2, none ], [ CNOT, [0,1], none, none ], [ CNOT, [1,2], none, none ], [ Measure,0, none, none ], [ Measure,1, none, none ], [ Measure,2, none, none ] ]. The compiled instruction list of the dynamic quantum circuit is as follows: dynamic_circuit= [ [ Reset,0, none ], [ Reset,1, none ], [ H,0, none ], [ H,1, none ], [ CNOT, [0,1], none ], [ Measure ], 0, none ], [ Reset,0, none ], [ H,0, none ], [ CNOT, [1,0], none, none ], [ Measure,0, none ], [ Measure,1, none ] ].

The aim of this embodiment is to compile a given static quantum circuit into its equivalent dynamic quantum circuit and to minimize the number of qubits required for the compiled quantum circuit.

In step S101, the first quantum circuit may be a static quantum circuit, and the first quantum circuit is a quantum circuit of a combined structure or a sub-circuit of a quantum circuit of a combined structure. The quantum circuit of the combined structure is widely used in the design of equivalent sub-algorithms including Simon algorithm.

In the combined structure, the two parts are included, wherein the first part is to sequentially act a first double-quantum bit gate between the quantum bit of the quantum bit j and the quantum bit of the quantum bit n+j in the order from j to big, the second part is to sequentially act a second double-quantum bit gate between the quantum bit of the quantum bit 0 and the quantum bit of the quantum bit n+j in the order from j to big, and the second part is positioned behind the first part in the quantum state time evolution direction. The first and second two-qubit gates may be CNOT gates, SWAP gates, or other two-qubit gates.

Fig. 5 is a schematic diagram of a quantum circuit of an exemplary combination structure, as shown in fig. 5, in which the quantum circuit includes 6 qubits, i.e., N is 3, and a first double-qubit gate is sequentially applied between qubit 0 and qubit 3, between qubit 1 and qubit 4, and between qubit 2 and qubit 5, followed by a second double-qubit gate sequentially applied between qubit 0 and qubit 3, between qubit 0 and qubit 4, and between qubit 0 and qubit 5.

The first instruction list of the first quantum circuit stored in advance may be acquired, the first instruction list of the first quantum circuit input by the user may be acquired, or the first instruction list of the first quantum circuit may be acquired based on the instruction list of the third quantum circuit equivalent to the first quantum circuit, which is not particularly limited herein.

The instruction list for the quantum circuit in fig. 5 is: static_circuit= [ [ Reset,0, none ], [ Reset,1, none ], [ Reset,2, none ], [ Reset,3, none ], [ Reset,4, none ], [ Reset,5, none, none ], [ CNOT, [0,3], none, none ], [ CNOT, [1,4], none, none ], [ CNOT, [2,5], none, none ], [ CNOT, [0,3], none, none ], [ CNOT, [0,4], none, none ], [ CNOT, [0,5], none, none ], [ Measure,0, none, none ], [ Measure,1, none, none ], [ Measure,2, none, none ], [ Measure,3, none ], [ Measure,4, none, none ], [ Measure,5, none, none ] ].

In addition, in the case that the first quantum circuit is a sub-circuit of the quantum circuit of the combined structure, the first instruction list of the first quantum circuit may be determined based on the instruction list of the quantum circuit of the combined structure, which is an ordered subset of the quantum circuit of the combined structure, that is, a part of the operation instruction is deleted from the instruction list of the quantum circuit of the combined structure, so as to obtain the first instruction list.

Step S102: based on the first instruction list, performing equivalent compiling on the first quantum circuit to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit; wherein the number of qubits of the second quantum circuit is smaller than the number of qubits of the first quantum circuit, the equivalent compilation comprising: adding a first reset operation instruction after a first measurement operation instruction in the first instruction list; remapping each first target operation instruction in the first instruction list to a qubit of a qubit i, wherein the first measurement operation instruction and the first reset operation instruction both act on the qubit i, and the first target operation instruction acts on the qubit i+1; and adding a second reset operation instruction after the second measurement operation instruction in the first instruction list; and remapping each second target operation instruction in the first instruction list to a quantum bit of a quantum bit N+h, wherein the second measurement operation instruction and the second reset operation instruction both act on the quantum bit N+h, the second target operation instruction acts on the quantum bit N+h+1, the value range of i is [1, N-2], and the value range of h is [0, N-2].

In this step, the second quantum circuit may be a dynamic quantum circuit.

When equivalent compiling is carried out, first measurement operation instructions in a first instruction list can be sequentially obtained, and for each first measurement operation instruction, based on a qubit i acted by the first measurement operation instruction, a first reset operation instruction on the qubit i is added after the first measurement operation instruction, and each first target operation instruction in the first instruction list is remapped to a qubit of the qubit i. The first measurement operation instruction is a measurement operation instruction acting on the qubit 1 … and the qubit N-2, respectively.

And sequentially acquiring second measurement operation instructions in the first instruction list, adding second reset operation instructions on the qubit N+h after the second measurement operation instructions based on the qubit N+h acted by the second measurement operation instructions for each second measurement operation instruction, and remapping each second target operation instruction in the first instruction list to the qubit of the qubit N+h. The second measurement operation instruction is a measurement operation instruction acting on the qubit N, the qubit N+ … and the qubit 2N-2 respectively.

If N is 2, the first measurement operation instruction is an empty set, and the second measurement operation instruction is a measurement operation instruction acting on qubit 2. That is, in the equivalent compiling, a second reset operation instruction on the qubit 2 is added after a second measurement operation instruction on the qubit 2, and a second target operation instruction acting on the qubit 3 in the first instruction list is remapped and mapped onto the qubit of the qubit 2, thereby obtaining a second instruction list of a second quantum circuit equivalent to the first quantum circuit.

If N is 3, the first measurement operation instruction is a measurement operation instruction acting on the qubit 1, and the second measurement operation instruction is a measurement operation instruction acting on the qubit 3 and the qubit 4, respectively. That is, during equivalent compiling, first, for the first measurement operation instruction on the qubit 1, a first reset operation instruction on the qubit 1 is added after the first measurement operation instruction on the qubit 1, and the first target operation instruction acting on the qubit 2 in the first instruction list is remapped, and mapped onto the qubit of the qubit 1. Then for the second measurement operation instruction on the qubit 3, the second reset operation instruction on the qubit 3 is added after the second measurement operation instruction on the qubit 3, and the second target operation instruction acting on the qubit 4 in the first instruction list is remapped, and mapped onto the qubit of the qubit 3, and for the second measurement operation instruction on the qubit 4, the second reset operation instruction on the qubit 4 is added after the second measurement operation instruction on the qubit 4, and the second target operation instruction acting on the qubit 5 in the first instruction list is remapped, and mapped onto the qubit of the qubit 4, so that the second instruction list of the second quantum circuit equivalent to the first quantum circuit can be obtained.

In this way, after the operation instruction of the quantum measurement operation is equivalently compiled, the operation instruction of the reset operation may be added after the operation instruction of the quantum measurement operation, by which the register unit allocated to the quantum bit i may be recovered for the continued use of the quantum bit i+1, and the register unit allocated to the quantum bit n+h may be recovered for the continued use of the quantum bit n+h+1, so as to reduce the number of quantum bits of the second quantum circuit obtained by compiling.

In an alternative embodiment, the equivalent compiling of the first quantum circuit may be directly performed based on the first instruction list, that is, the first measurement operation instruction and the target operation instruction are respectively obtained through traversing the first instruction list, and the equivalent compiling of the first quantum circuit is performed. In another alternative embodiment, a directed acyclic graph may be constructed based on the first instruction list, and equivalent compilation of the first quantum circuit is performed based on the directed acyclic graph.

In the related art, a heuristic algorithm is generally adopted to compile a quantum circuit, so that the optimality of circuit compilation cannot be ensured, if an optimal compiling scheme is given through mathematical modeling of circuit compilation, however, the algorithm complexity increases exponentially with the number of quantum bits, and the compiling efficiency of a larger-scale circuit is very low. In this embodiment, for the structural specificity of the quantum circuit of the combined structure, the reset may be performed after the measurement of the qubit i, the remapping of all the operation instructions acting on the qubit of the qubit i+1 onto the qubit of the qubit i is performed, and the reset may be performed after the measurement of the qubit n+h, the remapping of all the operation instructions acting on the qubit of the qubit n+h+1 onto the qubit of the qubit n+h, which is obtained by the proof of theory based on the circuit structure.

In terms of time complexity, the embodiment does not need to construct a complex mathematical model, so that the compiling process is simple, the running time can linearly increase along with N, and the compiling is very efficient. In the compiling effect, the compiled dynamic quantum circuit only needs 3 quantum bits. It can be theoretically proven that the compiling scheme in this embodiment is the optimal compiling scheme, that is, it is impossible to have a compiling scheme such that the compiled circuit width is less than 3. In this way, the present embodiment provides a quantum circuit with a combined structure and an optimal compiling method for sub-circuits of the quantum circuit with the combined structure, which can be directly applied to corresponding scenes without complex computation and optimization.

And the quantum computer based on different architecture designs can provide different quantum bit numbers and different realization capacities of various operations. Through equivalent compiling, the running scheme of the quantum circuit on a real quantum computer can be more flexible, and the dynamic quantum circuit and the static quantum circuit can be flexibly selected according to actual hardware conditions. For example, for a superconducting quantum computer with shorter coherence time but easy expansion of the number of quantum bits, it is more suitable for running a static quantum circuit with larger width and smaller depth; for a quantum computer based on an ion trap architecture, which has longer coherence time but relatively poorer expansibility, the quantum computer is more suitable for running a dynamic quantum circuit with smaller width and larger depth.

Optionally, the first quantum circuit further includes at least one single-quantum bit gate, where the single-quantum bit gate is located at any position of the first quantum circuit.

The equivalent compiling process in this embodiment is independent of the number, kind, specific execution position, and other information of the single-quantum bit gates, and therefore, the first quantum circuit in this embodiment may further include the single-quantum bit gates while ensuring that it is a combined structure or that it is a sub-circuit of the quantum circuit of the combined structure.

Fig. 6 is a schematic diagram of a quantum circuit of another example combined structure, and as shown in fig. 6, a single-qubit gate may be added at any position of the quantum circuit shown in fig. 5, or a CNOT gate may be replaced with another double-qubit gate. The quantum circuit is the quantum circuit of the combined structure as long as the double-quantum bit gate of the quantum circuit meets the combined structure.

For the quantum circuit of the combined structure shown in fig. 6, the instruction list is: 0, none ], [ S,1, none ], [ T,2, none ], [ H,3, none ], [ T,0, none ], [ S,1, none ], [ T,2, none ], [ H,3, none ], [ T,4, none ], [ S,5, none ], [ CNOT, [0,3], none ], [ S,3, none ], [ CNOT, [1,4], none, none ], [ CNOT, [2,5], none, none ], [ CNOT, [0,3], none, none ], [ CNOT, [0,4], none, none ], [ CNOT, [0,5], none, none ], [ Measure,0, none, none ], [ Measure,1, none, none ], [ Measure,2, none, none ], [ Measure,3, none ], [ Measure,4, none, none ], [ Measure,5, none, none ] ].

Fig. 7 is a schematic diagram of a sub-circuit of a quantum circuit of an exemplary combined structure, as shown in fig. 7, which is a quantum circuit obtained by deleting an operation instruction of a part of the double-quantum bit gate on the basis of fig. 6.

Thus, the application range of the original quantum circuit processed by the quantum circuit can be enlarged.

Optionally, the step S102 specifically includes:

determining a first directed acyclic graph based on the first instruction list, wherein the first directed acyclic graph comprises nodes corresponding to operation instructions in the first instruction list and first directed edges, and the first directed edges are used for representing time sequence relations among different operation instructions in the first instruction list;

adding a second directed edge in the first directed acyclic graph, wherein the second directed edge comprises directed edges from an output node corresponding to the first measurement operation instruction to an input node corresponding to a third reset operation instruction, and the third reset operation instruction is a reset operation instruction acting on a quantum bit i+1;

adding a third directed edge in the first directed acyclic graph to obtain a second directed acyclic graph and a directed edge list, wherein the third directed edge comprises directed edges from an output node corresponding to the second measurement operation instruction to an input node corresponding to a fourth reset operation instruction, the fourth reset operation instruction is a reset operation instruction acting on a qubit n+h+1, and the directed edge list comprises the second directed edge and the third directed edge;

And based on the second directed acyclic graph and the directed edge list, performing equivalent compiling on the first quantum circuit to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit.

In an alternative embodiment, the first instruction list may be traversed in order of instruction arrangement from left to right, and the first directed acyclic graph may be constructed by looking up nearest-neighbor operation instructions where the acted qubits intersect with the qubits acted by the operation instruction currently traversed.

In another optional embodiment, optionally, the determining, based on the first instruction list, a first directed acyclic graph includes:

traversing the first instruction list according to the arrangement sequence of the operation instructions;

taking the currently traversed operation instruction as a node, and adding an operation instruction corresponding node positioned at the tail of the target list to a first directed edge of the currently traversed operation instruction corresponding node under the condition that the target list is not an empty list; the target list is a list corresponding to the qubit acted by the currently traversed operation instruction;

and adding the currently traversed operation instruction to the tail end of the target list, and obtaining the first directed acyclic graph under the condition that the first instruction list is traversed.

That is, the preamble operation instruction of the operation instruction currently traversed is stored by constructing 2N target lists of 2N quantum bits in one-to-one correspondence. And acquiring a target list corresponding to the qubit based on the qubit acted by the currently traversed operation instruction, wherein the qubit acted by the operation instruction in the target list has an intersection with the qubit acted by the currently traversed operation instruction. And selecting the operation instruction nearest to the target list, namely the operation instruction at the tail in the target list, so as to construct a first directed edge. Thus, the construction process of the first directed acyclic graph can be simplified, and efficient construction of the first directed acyclic graph can be realized.

Further, adding a second directed edge in the first directed acyclic graph, and adding a third directed edge in the first directed acyclic graph to obtain a second directed acyclic graph and a directed edge list. The second directed edge comprises directed edges from the output node corresponding to the first measurement operation instruction to the input node corresponding to the third reset operation instruction, and the third reset operation instruction is a reset operation instruction acting on the qubit i+1. The third directed edge comprises directed edges from the second measurement operation instruction corresponding to the output node to the fourth reset operation instruction corresponding to the input node, and the fourth reset operation instruction is a reset operation instruction acting on the qubit n+h+1.

For example, if N is 2, the second directed edge is an empty set, and the third directed edge is a directed edge from the second measurement operation instruction corresponding output node acting on qubit 2 to the fourth reset operation instruction corresponding input node acting on qubit 3.

For another example, if N is 3, the second directed edge includes: a first measurement operation instruction acting on qubit 1 corresponds to a directed edge of an output node to a third reset operation instruction acting on qubit 2 corresponds to an input node, the third directed edge comprising: the second measurement operation instruction acting on qubit 3 corresponds to the directed edge of the output node to the fourth reset operation instruction acting on qubit 4 corresponds to the input node, and the second measurement operation instruction acting on qubit 4 corresponds to the directed edge of the output node to the fourth reset operation instruction acting on qubit 5 corresponds to the input node.

And then, based on the second directed acyclic graph and the directed edge list, performing equivalent compiling on the first quantum circuit to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit. Optionally, the performing equivalent compiling on the first quantum circuit based on the second directed acyclic graph and the directed edge list to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit, including:

Obtaining the topological order of the operation instructions corresponding to the second directed acyclic graph to obtain a third instruction list;

and remapping each target operation instruction corresponding to the quantum bit acted by the input node of the directed edge in the third instruction list to the quantum bit acted by the output node of the directed edge aiming at each directed edge in the directed edge list to obtain the second instruction list.

The optimal compilation process of the first quantum circuit is as follows:

input: a first instruction list circuit_list of the first quantum circuit, wherein the circuit width is 2N (N is more than or equal to 2);

and (3) outputting: a second list of instructions for the compiled dynamic quantum circuit.

Step 1: initializing an empty directed acyclic graph;

step 2: initializing a target list causellists with the length of 2N, wherein each element is an empty list;

step 3: looping around the circuit_list, assuming that the currently looped element is an instrucition:

step 3.1: taking out a qubit value in an instruction, circulating, setting a circulated element as q, taking the instruction as a node, and adding the node into a directed acyclic graph; searching the last element of the target list causel_list [ q ], and recording as a preinstruction; if the preinstruction is not a null element, adding a first directed edge to the directed acyclic graph, from the preinstruction to the instruction; add instruction to the last of list causellists q;

Step 4: initializing an empty list add_edges (i.e., a directed edge list);

step 5: for the variable i e {1, & gtis, N-2) cycle:

step 5.1: adding a second directed edge to the directed acyclic graph, pointing from the first measurement operation instruction acting on qubit i to the third reset operation instruction acting on qubit i+1, while adding the directed edge to the add_edges list;

step 6: for the variable h e {0, & gtis, N-2) cycle:

step 6.1: adding a third directed edge to the directed acyclic graph, pointing from the second measurement operation instruction acting on the qubit n+h to the fourth reset operation instruction acting on the qubit n+h+1, and simultaneously adding the directed edge to the add_edges list;

step 7: obtaining topological ordering of all circuit instructions according to the directed acyclic graph digraph, and recording the topological ordering in a circuit_list;

step 8: cycling the add_edges list, and setting the variable of the current cycle as edge:

step 8.1: let the presuppression and posinstruction represent the output node and input node of the directed edge respectively;

step 8.2: the quantum bits under the action of the two operation instructions of the preinstruction and the postinstruction are respectively a prequbit and a postqubit; circularly traversing the circuit_list list, and updating all target operation instructions acting on the quantum bit postqubit to act on the quantum bit prequbit; when the directed edge is a second directed edge, the target operation instruction is a first target operation instruction, and when the directed edge is a third directed edge, the target operation instruction is a second target operation instruction;

Step 9: the circuit_list is returned as output.

In this way, an equivalent compilation of the quantum circuits of the combined structure, and of the sub-circuits of the quantum circuits of the combined structure, can be achieved by means of directed acyclic graphs, the implementation of which is very simple.

For the quantum circuit in fig. 6, the dynamic quantum circuit obtained by compiling the scheme in this embodiment is shown in fig. 8, and the corresponding circuit instruction list is: dynamic_circuit= [ [ Reset,0, none ], [ Reset,1, none ], [ Reset,2, none ], [ H,0, none ], [ S,1, none ], [ H,2, none ], [ CNOT, [0,2], none, none ], [ S,2, none ], [ CNOT, [0,2], none ], [ Measure,2, none ], [ Reset,2, none ], [ T,2, none ], [ CNOT, [1,2], none, the method comprises the steps of [ CNOT ], [0,2], none, none ], [ Measure,1, none, none ], [ Measure,2, none, none ], [ Reset,1, none, none ], [ Reset,2, none, none ], [ T,1, none, none ], [ S,2, none ], [ CNOT, [1,2], none, none ], [ CNOT, [0,2], none, none ], [ Measure,0, none, none ], [ Measure,1, none, none ], [ Measure,2, none, none ] ]. The quantum bit number of the dynamic quantum circuit is 3, and the method is an optimal compiling scheme.

Optionally, in the case that the first quantum circuit is a quantum circuit with a combined structure, the step S101 specifically includes:

Adding a reset operation instruction of each qubit in the first quantum circuit to a circuit list;

sequentially adding the operation instruction of each first double-quantum bit gate between the quantum bit of the quantum bit j and the quantum bit of the quantum bit n+j to the circuit list according to the sequence from j to large, and sequentially adding the operation instruction of the second double-quantum bit gate between the quantum bit of the quantum bit 0 and the quantum bit of the quantum bit n+j to the circuit list according to the sequence from j to large when the operation instruction addition of the first double-quantum bit gate is completed;

and adding a quantum measurement operation instruction of each quantum bit in the first quantum circuit to a circuit list to obtain the first instruction list.

The specific acquisition process of a circuit instruction list of a quantum circuit comprising a combined structure of 2N quantum bits is as follows:

input: quantum circuit width 2N;

and (3) outputting: instruction list of quantum circuits of combined structure.

Step 1: initializing an empty list circuit_list;

step 2: for the variable i e {0,1, · ·, 2N-1) cycle:

step 2.1: adding a Reset operation instruction [ Reset, i, none ] to the end of the list circuit_list;

Step 3: for variable j e {0,1, · ·, N-1) cycle:

step 3.1: adding an operation instruction of the first two-quantum bit gate, such as [ CNOT, [ j, N+j ], none ] to the end of the list circuit_list;

step 4: for variable j e {0,1, · ·, N-1) cycle:

step 4.1: adding a second two-qubit gate operating instruction such as [ CNOT, [0, N+j ], none ] to the end of the list circuit_list;

step 5: for the variable i e {0,1, · ·, 2N-1) cycle:

step 5.1: adding a circuit instruction [ Measure, i, none ] to the end of the list circuit_list;

step 6: the circuit_list is returned as output.

Thus, the first instruction list of the quantum circuit of the combined structure can be obtained by inputting the structure information of the quantum circuit of the combined structure, and the process is simple.

In the case that the first quantum circuit is a quantum circuit of a combined structure, optionally, before the step S101, the method further includes:

performing displacement mapping on a third quantum circuit comprising 2N quantum bits, so that the 2N quantum bits in the third quantum circuit are orderly arranged according to the quantum bits from the quantum bit 0 to the quantum bit 2N-1;

and determining that the third quantum circuit is equivalent to the first quantum circuit when the third quantum circuit after the replacement mapping is a quantum circuit with a combined structure.

For the third quantum circuit which is not the standard quantum circuit, the third quantum circuit can be converted into the standard quantum circuit, and if the standard quantum circuit obtained after conversion is a quantum circuit with a combined structure, the third quantum circuit is equivalent to the first quantum circuit. In the standard quantum circuit, 2N quantum bits are sequentially arranged according to the quantum bit of the quantum bit 0 to the quantum bit of the quantum bit 2N-1.

Optionally, in the case where the third quantum circuit after the substitution mapping is a quantum circuit with a combined structure, the step S101 specifically includes:

acquiring a fourth instruction list of the third quantum circuit;

replacing a first number list of 2N quantum bits in the third quantum circuit to obtain a second number list, wherein the second number list is sequentially arranged according to quantum bits from quantum bit 0 to quantum bit 2N-1;

and transforming the qubit acted by the operation instruction in the fourth instruction list based on the mapping relation between the first number list and the second number list to obtain the first instruction list.

The first numbered list of 2N quantum bits in the third quantum circuit may be permuted based on a permutation matrix, to obtain a second numbered list, where the permutation matrix may be input or preset by a user. Then, based on the mapping relationship between the first numbering list and the second numbering list, for example, the qubit 2 in the third quantum circuit is mapped to the qubit 0 in the first quantum circuit, the qubit acted by the operation instruction in the fourth instruction list is transformed, for example, the operation instruction acted on the qubit 2 in the fourth instruction list is remapped to the qubit 0, so as to obtain the first instruction list of the first quantum circuit.

In this way, the acquisition of the instruction list of the first quantum circuit can be realized based on the instruction list of the third quantum circuit equivalent to the first quantum circuit.

Second embodiment

As shown in fig. 9, the present disclosure provides a quantum circuit processing apparatus 900, comprising:

an obtaining module 901, configured to obtain a first instruction list of a first quantum circuit including 2N quantum bits, where the first quantum circuit is: a quantum circuit of a combined structure or a sub-circuit of the quantum circuit of the combined structure, wherein 2N quantum bits are sequentially arranged according to quantum bits from 0 to 2N-1 of the quantum bits, a first double-quantum bit gate is sequentially acted between the quantum bits of the quantum bits j and the quantum bits of the quantum bits n+j according to the sequence from j to big, a second double-quantum bit gate is sequentially acted between the quantum bits of the quantum bits 0 and the quantum bits of the quantum bits n+j according to the sequence from j to big, the second double-quantum bit gate is positioned behind the first double-quantum bit gate in the quantum state time evolution direction, the value range of j is [0, N-1], and the sub-circuit is a quantum circuit obtained by deleting part of operation instructions from an instruction list of the quantum circuit of the combined structure, and N is an integer greater than or equal to 2;

The equivalent compiling module 902 is configured to perform equivalent compiling on the first quantum circuit based on the first instruction list, to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit;

Optionally, the equivalent compiling module 902 includes:

the determining unit is used for determining a first directed acyclic graph based on the first instruction list, wherein the first directed acyclic graph comprises nodes corresponding to operation instructions in the first instruction list and first directed edges, and the first directed edges are used for representing time sequence relations among different operation instructions in the first instruction list;

the adding unit is used for adding a second directed edge in the first directed acyclic graph, wherein the second directed edge comprises directed edges from the output node corresponding to the first measurement operation instruction to the input node corresponding to a third reset operation instruction, and the third reset operation instruction is a reset operation instruction acting on the qubit i+1; adding a third directed edge in the first directed acyclic graph to obtain a second directed acyclic graph and a directed edge list, wherein the third directed edge comprises directed edges from an output node corresponding to the second measurement operation instruction to an input node corresponding to a fourth reset operation instruction, the fourth reset operation instruction is a reset operation instruction acting on a qubit n+h+1, and the directed edge list comprises the second directed edge and the third directed edge;

And the equivalent compiling unit is used for carrying out equivalent compiling on the first quantum circuit based on the second directed acyclic graph and the directed edge list to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit.

Optionally, the determining unit is specifically configured to:

Optionally, the equivalent compiling unit is specifically configured to:

Optionally, in the case that the first quantum circuit is a quantum circuit with a combined structure, the acquiring module 901 is specifically configured to:

Optionally, the apparatus further includes:

the permutation mapping module is used for permutation mapping of a third quantum circuit comprising 2N quantum bits so as to orderly arrange the 2N quantum bits in the third quantum circuit according to the quantum bits from the quantum bit 0 to the quantum bit 2N-1;

And the determining module is used for determining that the third quantum circuit is equivalent to the first quantum circuit when the third quantum circuit after the replacement mapping is a quantum circuit with a combined structure.

Optionally, in the case where the third quantum circuit after the permutation mapping is a quantum circuit with a combined structure, the obtaining module 901 is specifically configured to:

acquiring a fourth instruction list of the third quantum circuit;

The quantum circuit processing apparatus 900 provided in the present disclosure can implement each process implemented by the quantum circuit processing method embodiment, and can achieve the same beneficial effects, so that repetition is avoided, and no further description is provided herein.

In the technical scheme of the disclosure, the related processes of collecting, storing, using, processing, transmitting, providing, disclosing and the like of the personal information of the user accord with the regulations of related laws and regulations, and the public order colloquial is not violated.

According to embodiments of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

FIG. 10 illustrates a schematic block diagram of an example electronic device that may be used to implement embodiments of the present disclosure. Electronic devices are intended to represent various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular telephones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 10, the apparatus 1000 includes a computing unit 1001 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 1002 or a computer program loaded from a storage unit 1008 into a Random Access Memory (RAM) 1003. In the RAM 1003, various programs and data required for the operation of the device 1000 can also be stored. The computing unit 1001, the ROM 1002, and the RAM 1003 are connected to each other by a bus 1004. An input/output (I/O) interface 1005 is also connected to bus 1004.

Various components in device 1000 are connected to I/O interface 1005, including: an input unit 1006 such as a keyboard, a mouse, and the like; an output unit 1007 such as various types of displays, speakers, and the like; a storage unit 1008 such as a magnetic disk, an optical disk, or the like; and communication unit 1009 such as a network card, modem, wireless communication transceiver, etc. Communication unit 1009 allows device 1000 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunications networks.

The computing unit 1001 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of computing unit 1001 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 1001 performs the respective methods and processes described above, for example, a quantum circuit processing method. For example, in some embodiments, the quantum circuit processing method may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as the storage unit 1008. In some embodiments, part or all of the computer program may be loaded and/or installed onto device 1000 via ROM 1002 and/or communication unit 1009. When a computer program is loaded into RAM 1003 and executed by computing unit 1001, one or more steps of the quantum circuit processing method described above may be performed. Alternatively, in other embodiments, the computing unit 1001 may be configured to perform the quantum circuit processing method in any other suitable way (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for carrying out methods of the present disclosure may be written in any combination of one or more programming languages. These program code may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus such that the program code, when executed by the processor or controller, causes the functions/operations specified in the flowchart and/or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. The machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and pointing device (e.g., a mouse or trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), and the internet.

The computer system may include a client and a server. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server incorporating a blockchain.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps recited in the present disclosure may be performed in parallel, sequentially, or in a different order, provided that the desired results of the disclosed aspects are achieved, and are not limited herein.

The above detailed description should not be taken as limiting the scope of the present disclosure. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present disclosure are intended to be included within the scope of the present disclosure.

Claims

1. A quantum circuit processing method, comprising:

obtaining a first instruction list of a first quantum circuit comprising 2N quantum bits, the first quantum circuit being: a quantum circuit of a combined structure or a sub-circuit of the quantum circuit of the combined structure, wherein 2N quantum bits are sequentially arranged according to quantum bits of a quantum bit 0 to quantum bits of a quantum bit 2N-1, a first double-quantum bit gate is sequentially acted between the quantum bits of a quantum bit j and the quantum bits of a quantum bit n+j according to the sequence from j to big, a second double-quantum bit gate is sequentially acted between the quantum bits of the quantum bit 0 and the quantum bits of the quantum bit n+j according to the sequence from j to big, the second double-quantum bit gate is positioned behind the first double-quantum bit gate in the quantum state time evolution direction, the sub-circuit is a quantum circuit obtained by deleting part of operation instructions from an instruction list of the quantum circuit of the combined structure, and the value range of j is [0, N-1], and N is an integer greater than or equal to 2;

2. The method of claim 1, wherein the equivalently compiling the first quantum circuit based on the first instruction list to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit comprises:

3. The method of claim 2, wherein the determining a first directed acyclic graph based on the first list of instructions comprises:

4. The method of claim 2, wherein the equivalently compiling the first quantum circuit based on the second directed acyclic graph and the directed edge list to obtain a second instruction list of a second quantum circuit equivalent to the first quantum circuit comprises:

5. The method of claim 1, wherein, in the case where the first quantum circuit is a quantum circuit of a combined structure, the obtaining a first instruction list of the first quantum circuit including 2N quantum bits comprises:

6. The method of claim 1, prior to the fetching of the first instruction list of the first quantum circuit comprising 2N quantum bits, further comprising:

7. The method of claim 6, wherein, in the case where the third quantum circuit after permutation mapping is a quantum circuit of a combined structure, the obtaining the first instruction list of the first quantum circuit including 2N quantum bits includes:

acquiring a fourth instruction list of the third quantum circuit;

8. The method of claim 1, wherein the first quantum circuit further comprises at least one single-qubit gate therein, the single-qubit gate being located anywhere in the first quantum circuit.

9. A quantum circuit processing apparatus comprising:

an acquisition module, configured to acquire a first instruction list of a first quantum circuit including 2N quantum bits, the first quantum circuit being: a quantum circuit of a combined structure or a sub-circuit of the quantum circuit of the combined structure, wherein 2N quantum bits are sequentially arranged according to quantum bits of a quantum bit 0 to quantum bits of a quantum bit 2N-1, a first double-quantum bit gate is sequentially acted between the quantum bits of a quantum bit j and the quantum bits of a quantum bit n+j according to the sequence from j to big, a second double-quantum bit gate is sequentially acted between the quantum bits of the quantum bit 0 and the quantum bits of the quantum bit n+j according to the sequence from j to big, the second double-quantum bit gate is positioned behind the first double-quantum bit gate in the quantum state time evolution direction, the sub-circuit is a quantum circuit obtained by deleting part of operation instructions from an instruction list of the quantum circuit of the combined structure, and the value range of j is [0, N-1], and N is an integer greater than or equal to 2;

10. The apparatus of claim 9, wherein the equivalent compiling module comprises:

11. The apparatus according to claim 10, wherein the determining unit is specifically configured to:

12. The apparatus of claim 10, wherein the equivalent compiling unit is specifically configured to:

13. The apparatus of claim 9, wherein, in the case that the first quantum circuit is a quantum circuit of a combined structure, the obtaining module is specifically configured to:

14. The apparatus of claim 9, further comprising:

15. The apparatus of claim 14, wherein, in the case where the third quantum circuit after the permutation mapping is a quantum circuit of a combined structure, the obtaining module is specifically configured to:

acquiring a fourth instruction list of the third quantum circuit;

16. The apparatus of claim 9, wherein the first quantum circuit further comprises at least one single-qubit gate therein, the single-qubit gate being located anywhere in the first quantum circuit.

17. An electronic device, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-8.

18. A non-transitory computer readable storage medium storing computer instructions for causing the computer to perform the method of any one of claims 1-8.

19. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any of claims 1-8.