CN117311604A - Embedded multi-element backup and loading method - Google Patents

Abstract

The invention discloses an embedded multi-element backup and loading method, which is based on CPLD/low-end FPGA for control and transfer, and realizes dynamic pairing between a plurality of processors and a plurality of memories in an embedded system, thereby realizing the functions that the processors backup data to a plurality of external memories and load data from the memories when needed. The invention relates to a method for controlling the starting flow of an embedded system with a multiprocessor in a classical application scene. The invention further provides a specific application scenario based on such a design architecture.

Description

Embedded multi-element backup and loading method

Technical Field

The invention relates to bus multiplexing at hardware level and logic level, and processor startup flow control.

Background

Embedded technology has been rapidly developed in recent years, and the design field is very wide, for example, many industries: the embedded applications of mobile phones, vehicle-mounted, industrial control, military industry, medical treatment and the like are almost ubiquitous. An embedded system is usually an embedded processor board with a control program stored in an on-board memory, and usually when designing the embedded system, an additional external memory is prepared for the processor to store data to be saved, or multiple sets of control programs are respectively stored in multiple memories, and the chip selection of the memories is switched according to the requirement, so that different control programs on the processor are switched. However, with the rapid development of embedded technology, the design of an embedded system is more and more complex: from single processor to multiple processors at first, increasingly rich peripherals, etc. The number of processors in the system increases, which leads to an increase in the number of memories corresponding thereto, and the hardware design becomes more complicated. In order to cope with the difficulty caused by more and more complex design and reduce the amount of memory to reduce the cost, the data multi-backup and loading method in the patent is proposed.

Disclosure of Invention

The invention aims to provide a multi-element backup and loading method which is suitable for an embedded system of a multiprocessor, and is used for backing up application data and processor starting program data into a plurality of memories and loading the data when needed.

The technical scheme adopted by the invention for achieving the purposes is as follows:

when designing an embedded system, a CPLD or a low-end FPGA (hereinafter referred to as CPLD) is added, and bus signals connect a plurality of processors and memories through the CPLD, so that the consistency of bus types used by all the memories should be ensured, and all the processors can use bus types for accessing the memories (for example, in the case that the memories use buses of a certain type, all the processors needing to access the memories are required to support the buses of the type), thereby ensuring the possibility that the processors access the functions of the plurality of memories through a single set of buses on a hardware level.

The bus pairing of the processor and the memory is realized through the logic design in the CPLD chip, and a section of register is planned in the CPLD, so that the processor can modify the bus pairing of the processor and the memory through the registers by the bus, and the function of accessing a plurality of memories by the processor through a single group of buses on the logic level is realized.

If the program of the processor needs to be loaded by the method in the starting stage of the processor, the bus used by the processor for accessing the memory is required to be consistent with the bus used by the processor for starting, and additional hardware and logic design are required according to the starting flow of the processor, and the processor can be ensured to load the starting program from the memory and start smoothly in cooperation with the starting flow connection and control related signals of the processor.

The invention also provides a specific implementation method of each link of the architecture, which comprises the following steps:

overall hardware design:

1. all bus signals between the original processor and the memory should be connected to the CPLD, for example, the connection mode is changed from the processor < bus- > memory to the processor < bus- > CPLD < bus- > memory, at this time, since the bus signals can be connected to different banks of the CPLD, the level standards between the banks of the CPLD can be inconsistent, so that a memory inconsistent with the level standard of the processor bus signals can be selected, which further increases the flexibility of memory type selection.

2. If the processor program is loaded by the method during the starting stage of the processor, signals related to the starting process of the processor should be connected to the CPLD, such as a hard reset signal and a starting completion signal of the processor, and other signals may be connected to the CPLD according to the complexity of the starting process of the processor.

The bus pairing method is designed:

1. the main ID value is defined according to the number of the buses on the processor side, the ID register is defined according to the number of the buses on the memory side, and when the value of the ID register corresponding to the memory is equal to a certain main ID value, the corresponding processor and the memory are paired, so that the processor can access the corresponding memory.

2. The initial value of the ID register is set so that certain processors can access the designated memory in the initial state.

3. The idle ID value should be set and when the value of the ID register is idle, the memory is not paired with any processor.

The value of the id register should be readable and writable by the processor via other buses to enable dynamic pairing of processors and memories.

5. If the bus signal used contains a chip select, the processor may access registers on the CPLD via the same set of buses that use other chip select signals, which may reduce the number of connections.

6. There may be a processor that only configures the CPLD register without accessing memory, and no ID value is set to correspond to it.

The CPLD should detect the state of the ID registers at all times, and if the values of the ID registers are the same, the last modified ID register in the ID registers with the same value should be reserved, and the rest ID registers are forcedly changed into idle ID values.

8. Before the processor accesses the memory via the bus, the processor's ID register should be validated to ensure that it has paired with the memory and then perform subsequent bus transactions.

9. If there are multiple processors that can access the ID register, the busy register should be defined according to the number of buses on the processor side, the value of the register is asserted when the bus on the memory is active, and the register is de-asserted after the bus is idle for a period of time. The processor should confirm the status of the busy register before configuring the memory ID register, and reconfigure the ID register when confirming that the memory is in an idle state.

The method for controlling the starting of the processor is designed as follows:

1. this section is only used in the case of loading program startup from off-chip memory of the processor, and the complexity of the corresponding logic design will vary depending on the complexity of the processor startup procedure.

2. The boot flow of the processor that is initiated by the external memory should be triggerable and controllable by the registers, and there should be a default control boot flow to ensure that the processor is able to boot.

3. After being reset, a general processor loads programs from buses appointed by a starting mode, and starts after loading is completed. So in this case, the in-memory program is ready and the processor is paired with the memory, a hard reset signal of the processor is triggered, the state of the processor is reset, and the boot flow of the processor is started. Waiting for the starting completion signal of the processor to be asserted, and judging that the starting of the processor is successful; setting a starting timeout time of the processor, defining a starting failure signal, judging that the processor is not started successfully within a set time, and judging that the processor is started successfully, and asserting the starting failure signal to carry out subsequent operations.

4. The starting process of part of the processors is complex, the starting related configuration pins are more, the starting steps are more, and the starting time sequence is complex by taking the FPGA of the siren as an example, and the starting process is completed by purposefully designing a state machine and control logic according to the starting process introduced in the official document and matching with the processors.

The invention has the beneficial effects that:

compared with the traditional multi-element backup and loading method, the method provided by the invention uses fewer hardware resources except for using one CPLD more, simplifies the wiring design on hardware, increases the flexibility of the memory in the aspect of selecting the type, reduces the difficulty of hardware design, realizes the multi-master multi-slave access mode between the processor and the memory, compresses the quantity of the memory, and improves the utilization efficiency of the memory.

Drawings

The invention will be further described with reference to the accompanying drawings and embodiments, in which:

FIG. 1 is a schematic block diagram of an embedded system in an embodiment.

FIG. 2 is a block diagram of an initial state of an embedded system in an embodiment.

FIG. 3 is a diagram of Master SPI mode enable pins used by an FPGA in a particular embodiment.

FIG. 4 is a Master SPI mode start timing diagram used by the FPGA in a particular embodiment.

FIG. 5 is a flowchart of the startup of an embedded system in an embodiment.

FIG. 6 is a flow chart of the FPGA backup program writing in an embodiment.

Fig. 7 is a flow of CPLD detecting repair ID register conflicts in an embodiment.

Fig. 8 is a flow of accessing an occupied FLASH in an embodiment.

Fig. 9 is a logic block diagram illustrating the correspondence of the design architecture mentioned in the abstract.

Description of the embodiments

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

In the embodiment described herein, the embedded system includes one CPLD, FPGA, DSP, CPU, MCU and five QSPI FLASH pieces each. The CPLD controls a reset signal of FPGA, DSP, CPU, MCU, CPLD, CPU, MCU is started through the built-in storage unit, DSP, CPU, MCU can access the CPLD register through the SPI, DSP and CPU can access five chips QSPI FLASH, FPGA through the CPLD through the SPI, and can access five chips QSPI FLASH through the CPLD through the QSPI. A schematic block diagram of the embedded system is shown in fig. 1.

FPGA, DSP, CPU the IDs in CPLD are 0x1,0x 2 and 0x3 respectively, and MCU does not access FLASH and does not set its ID in CPLD, and the idle ID value is defined as 0x0. The initial values of the corresponding ID registers of the five pieces QSPI FLASH1 are 0x1,0x0,0x2,0x0 and 0x0 respectively, which means that the FPGA is paired with FLASH1 in the initial state, the DSP is paired with FLASH3, and FLASH2, 4 and 5 are idle. The initial state block diagram of the embedded system is shown in fig. 2.

In this case the following additional conditions are associated with the start-up sequence:

a high-speed interface SRIO is arranged between the FPGA and the DSP, and the SRIO of the DSP is only initialized once in an initialization stage after the start is completed, so that the FPGA is required to be started first and then the DSP is required to be started.

And 2, the DSP needs to acquire the ID of the SRIO from the MCU, so that the MCU is required to be started first and then the DSP is required to be started.

And 3, a high-speed interface PCIE is arranged between the DSP and the CPU, wherein the CPU is RC, the DSP is EP, so that the DSP is required to be started first and then started, otherwise, the PCIE between the DSP and the CPU fails to build a chain.

Therefore, the starting sequence of the system after power-on is CPLD- > MCU- > FPGA- > DSP- > CPU according to the conditions, and the starting flow of the system is described below:

1. the system is powered on, so the CPLD is reset FPGA, DSP, CPU, MCU after being started according to the requirement of the starting sequence, and the reset signals of the CPLD are sequentially released according to the designed state machine, the reset signals of the next processor are released after the CPLD is respectively started, if the starting time is out, the starting failure signal of the corresponding processor is asserted, the state of the next processor is entered, and the reset signals of the next processor are released.

2. Firstly, the reset signal of the MCU is released, the MCU is started from the built-in storage unit, and the MCU waits for the completion of the starting.

And 3, after the MCU is successfully started, releasing a reset signal of the FPGA and starting a starting flow of the FPGA. The FPGA used in this example is the V7 of the siren, the definition of the Master SPI mode startup interface is shown in fig. 3 (the interface of the FPGA at the SPI/DSPI is shown in the figure, the QSPI interface used in this example is different only in the data bit width of the SPI, and other signals are the same), and the startup timing in this startup mode is shown in fig. 4. According to the timing sequence in FIG. 3, the pairing of the FPGA and the FLASH is completed before the FCS_B is pulled down, the FLASH paired with the FPGA is FLASH1 at the moment, and after the FCS_B is pulled down, the FPGA loads the starting program of the FPGA from FLASH1

And 4, after the FPGA is successfully started/overtime, releasing the reset signal of the DSP and starting the starting flow of the DSP. The DSP used in this example is TI6678, after reset is released, the default starting mode of the DSP is SPI loader starting, at this time, the FLASH paired with the DSP is FLASH3, the DSP will load its starting program from FLASH3, if the loaded program is correct, the DSP will start successfully after the program loading is completed.

And 5, after the DSP is successfully started/overtime, the reset signal of the CPU is released, the starting flow of the CPU is started, and the CPU is started from the built-in storage unit to wait for the completion of the starting of the CPU.

6. Since CPLD, MCU, CPU is started from the internal storage unit, they will not start failure generally, so when the FPGA and DSP start failure, it is necessary to erase FLASH1 and FLASH3 by CPU and rewrite the starting program of FPGA and DSP, or when other FLASH has backup starting program, access the register of CPLD by MCU and CPU to change the ID register of FLASH, so as to change the pairing FLASH of FPGA and DSP, and access the register of CPLD to trigger the starting flow of the whole system again, and return to step 1.

7. If the CPU is started, the five processors are started successfully, and the whole embedded system is judged to be started successfully, and the system starts to work normally at the moment.

The starting flow of the whole embedded system is shown in figure 5.

After the system works normally, different programs may need to be run in the FPGA, i.e. dynamically loaded, according to the functional requirements, and if their backup programs are not written, one of the DSP or CPU is required to pair with the FLASH and write the corresponding backup program. If the DSP or the CPU has the function of downloading data through the network, the system can download the starting programs of the FPGA and the DSP on line without a debugging port. The flow of the FPGA backup program writing is shown in fig. 6.

If the backup program of the FPGA is already stored in the FLASH2 at this time, one of the DSP, CPU, MCU is used to access the ID register of the FLASH2 in the CPLD to pair with the FPGA, and then access the register of the CPLD after the pairing is successful, the system reset function is triggered to realize the dynamic loading of the FPGA, if the system part reset function is designed in the CPLD, the starting process of the system can be reset to a state started by the FPGA, otherwise, the whole system is reset, and the starting process of the system is started from the beginning.

After the ID register is reset, the CPLD detects that the ID registers of FLASH1 and FLASH2 have the same value, and then modifies the ID register of FLASH1 to 0x0, so that FLASH1 becomes an idle state. So that the problem of pairing conflict does not occur. The flow of CPLD detection of repair ID register conflicts is shown in FIG. 7.

After the system works normally, the DSP and the CPU can store the application data into the FLASH or read the application data from the FLASH according to the function requirements. Because the DSP and the CPU access the same memory, before accessing the FLASH through the bus, the DSP and the CPU need to access an ID register and a busy register corresponding to the FLASH in the CPLD, and firstly access the busy server to confirm whether the FLASH is occupied by another processor, if the FLASH is idle, the ID register is accessed to confirm whether the FLASH is paired with the memory, if the ID register is not matched with the ID value of the FLASH, the DSP and the CPU write the ID of the FLASH into the memory to be paired with the memory, and after the preparation work is completed, the FLASH can be accessed through the bus.

If the DSP and the CPU store and load application data in the FLASH5, the flow of the CPU accessing the FLASH5 under the condition that the DSP is paired with the FLASH5 is shown in fig. 8.

In summary, the application scenes such as the control of the starting flow of the embedded system, the multi-element backup and loading of the starting program, the multi-element backup and loading of the application data and the like under specific conditions are introduced through the specific embodiments, so that the method provided by the invention has the characteristics of strong functionality, strong flexibility, low wiring resource overhead, high memory resource utilization rate and the like in the embedded system under specific conditions, and can realize the functions of online downloading and dynamic loading of the programs of part of processors under the condition of permission, thus being very convenient for debugging of the embedded system; such design methods are friendly to software, logic developers; the method has good support for the scene of harsh hardware storage conditions, for example, an embedded system board card is inserted into a closed chassis, and when the chassis is connected with the outside only through a network cable, further updating programs and debugging can be carried out by the method.

It will be understood that modifications and variations will be apparent to those skilled in the art from the foregoing description, and it is intended that all such modifications and variations be included within the scope of the following claims.

Claims (9)

1. The embedded multielement backup and loading method is characterized in that a CPLD or a low-end FPGA is specially used as control and transfer in an embedded system, and the control part comprises bus pairing control between a processor and a memory in the system and starting flow control of the whole system. The transfer is to transfer bus signals bidirectionally on the basis of bus pairing.

2. The bus pairing control according to claim 1, wherein both paired parties should use the same kind of bus, and the kind of bus used by the memory should be compatible with the kind of bus used by the processor, so as to ensure that the processor side can exert the maximum performance of the bus, for example, the processor uses a standard SPI bus, and the memory uses a QSPI bus; vice versa, but the processor cannot use the bus for maximum performance, subject to memory side.

3. The bus pairing control according to claim 1, wherein each device of the master is discriminated by setting a master ID of the bus; and setting a slave ID register to distinguish each device of the slave. By comparing the results of the ID register and the master ID, it is decided which memory is bus paired with which processor.

4. A bus pairing as defined in claim 3, wherein the master ID corresponding to the processor is fixed in design and the value of the ID register corresponding to the memory is modifiable, the design implementing a multi-master multi-slave mode of operation of the bus, i.e. implementing the function that each processor has access to each memory.

5. The bus pairing process as set forth in claim 3, wherein the system is usable in a single-processor multi-memory and multi-processor single-memory system, but the system is not necessarily usable in a single-processor single-memory system.

6. A bus pairing method according to claim 3, wherein when there is a bidirectional transfer of signals in the bus type used, the bus pairing may cause multiple driver signals to be connected on the same line, and in order to avoid this, a mechanism of ID collision should be set in the CPLD, and when the values of the multiple ID registers are found to be the same and not the idle ID, the last configured ID register should be reserved, so that the other ID registers should be forced to be set to the idle ID.

7. A bus pairing method as defined in claim 3, wherein the same memory may be accessed by multiple processors at the same time, and wherein only the processor paired with the memory accesses the memory via the bus due to the pairing mechanism, and the other processors fail to access. To avoid this, the processor is required to confirm the paired object of the memory and the working state of the bus thereof before accessing the memory, and therefore, it is required to set the busy register of the memory bus so that the processor can confirm the working state of the memory; when a processor cannot access a register within the CPLD, it is otherwise ensured that multiple processors access the same processor within the same time period.

8. The system boot flow control of claim 1, wherein the boot flow of each processor in the system is of common general knowledge in the industry and not in the scope of the patent rights; the smart combination of these starting processes and bus pairing control and the improvement measures adopted in the patent are important protection items of the patent.

9. The bus signal relay of claim 1, wherein the bus interface used and the interface timing at access are different depending on the memory selected. After the hardware design is completed, the control logic is designed in a targeted manner according to a data manual of a memory, so that the signal transmission direction in the CPLD is changed under the condition that certain bus signal directions can be switched, and the bidirectional transmission of signals is realized.