CN117311081A - Photomask assembly and preparation method of semiconductor structure - Google Patents
Photomask assembly and preparation method of semiconductor structure Download PDFInfo
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- CN117311081A CN117311081A CN202210674446.7A CN202210674446A CN117311081A CN 117311081 A CN117311081 A CN 117311081A CN 202210674446 A CN202210674446 A CN 202210674446A CN 117311081 A CN117311081 A CN 117311081A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 45
- 238000002360 preparation method Methods 0.000 title abstract description 7
- 238000005530 etching Methods 0.000 claims abstract description 70
- 238000000034 method Methods 0.000 claims description 65
- 239000003990 capacitor Substances 0.000 claims description 50
- 238000004519 manufacturing process Methods 0.000 claims description 33
- 239000000758 substrate Substances 0.000 claims description 20
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 9
- 229910052710 silicon Inorganic materials 0.000 claims description 9
- 239000010703 silicon Substances 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 4
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 4
- 238000001259 photo etching Methods 0.000 claims description 4
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 4
- 239000010410 layer Substances 0.000 description 297
- 238000005229 chemical vapour deposition Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000005240 physical vapour deposition Methods 0.000 description 5
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 238000005137 deposition process Methods 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- 238000002513 implantation Methods 0.000 description 3
- 229910003481 amorphous carbon Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 229910017107 AlOx Inorganic materials 0.000 description 1
- 229910002601 GaN Inorganic materials 0.000 description 1
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910003134 ZrOx Inorganic materials 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229910001925 ruthenium oxide Inorganic materials 0.000 description 1
- WOCIAKWEIIZHES-UHFFFAOYSA-N ruthenium(iv) oxide Chemical compound O=[Ru]=O WOCIAKWEIIZHES-UHFFFAOYSA-N 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
- 229910001928 zirconium oxide Inorganic materials 0.000 description 1
Classifications
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
Abstract
The invention relates to a photomask assembly and a preparation method of a semiconductor structure. The photomask assembly includes: the first photomask is internally provided with a plurality of first photomask patterns which are arranged in a plurality of rows and columns at intervals; the second photomask is internally provided with a plurality of second photomask patterns which are arranged in a plurality of rows and columns at intervals; orthographic projection patterns of each row of second photomask patterns on the surface of the first photomask are positioned between two adjacent rows of first photomask patterns; the first photomask patterns and the orthographic projection patterns which are positioned in the same row are alternately arranged at intervals along the first direction, and the first photomask patterns and the orthographic projection patterns which are positioned in the same column are alternately arranged along the second direction. The first photomask pattern is not shielded when the second photomask pattern is adjusted, after an opening is formed in the supporting layer based on the photomask assembly, the opening ratio can be increased, the risk of insufficient etching can be reduced, and therefore the performance of the memory device is improved.
Description
Technical Field
The present disclosure relates to the field of integrated circuits, and more particularly, to a photomask assembly and a method for manufacturing a semiconductor structure.
Background
DRAM (Dynamic Random Access Memory ) is a semiconductor memory device commonly used in computers and is composed of a number of repeated memory cells. The DRAM stores data in the form of storing charge on the capacitor, which needs to be regularly charged and discharged every several milliseconds.
In the preparation process of the DRAM device, after a capacitor hole and a lower electrode are formed in a laminated structure comprising a supporting layer and a sacrificial layer which are sequentially overlapped from bottom to top, when a patterned mask layer is formed on the laminated structure based on a photomask and used for forming an opening in the supporting layer, due to Overlay (OVL) deviation, the opening formed in the supporting layer is less, so that when the sacrificial layer positioned below the supporting layer is removed based on the opening, underetching (underetching) is easy to occur to cause the residual of the sacrificial layer, and the performance of the DRAM device is affected.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a photomask assembly and a method for manufacturing a semiconductor structure.
To achieve the above object, in one aspect, the present invention provides a photomask assembly, comprising:
the first photomask is internally provided with a plurality of first photomask patterns, and the plurality of first photomask patterns are arranged in a plurality of rows and columns at intervals;
the second photomask is internally provided with a plurality of second photomask patterns, and the second photomask patterns are arranged in a plurality of rows and columns at intervals; the orthographic projection patterns of the second photomask patterns of each column on the surface of the first photomask are positioned between two adjacent columns of the first photomask patterns; the first photomask patterns and the orthographic projection patterns which are positioned in the same row are alternately arranged at intervals along a first direction, and the first photomask patterns and the orthographic projection patterns which are positioned in the same column are arranged at intervals along a second direction.
In one embodiment, the first photomask pattern and the orthographic pattern located in the same row have a first offset pitch along a second direction.
In one embodiment, the width of the first photomask pattern is the same as the width of the second photomask pattern, and the first dislocation distance is 1/6-1/3 of the width of the first photomask pattern or the width of the second photomask pattern.
The application also provides a preparation method of the semiconductor structure, which comprises the following steps:
providing a substrate;
forming a laminated structure of alternately laminated supporting layers and sacrificial layers on the upper surface of the substrate;
forming a capacitor hole in the laminated structure; the capacitor hole penetrates through the supporting layer and the sacrificial layer;
forming a lower electrode on the side wall and the bottom of the capacitor hole;
forming a patterned etching mask layer on the laminated structure based on the photomask assembly in any scheme, wherein a plurality of etching opening patterns which are arranged in a plurality of rows and columns at intervals are formed in the patterned etching mask layer, the etching opening patterns positioned in the same row are arranged at intervals along a first direction, the etching opening patterns positioned in the same column are arranged at intervals along a second direction, and two adjacent columns of etching opening patterns have a second dislocation distance along the second direction;
and forming an opening in the laminated structure based on the patterned etching mask layer, wherein the opening exposes the sacrificial layer, and removing the sacrificial layer based on the opening.
In one embodiment, the forming the capacitor hole in the stacked structure includes:
forming a first patterned mask layer on the upper surface of the laminated structure, wherein a plurality of first opening patterns are formed in the first patterned mask layer, and the shapes and positions of the capacitor holes are defined by the first opening patterns;
etching the laminated structure based on the first patterned mask layer to form the capacitor hole in the laminated structure;
and removing the first patterned mask layer.
In one embodiment, the forming a patterned etching mask layer on the stacked structure based on the photomask assembly according to any of the above aspects includes:
forming a first mask layer on the upper surface of the laminated structure;
forming a second mask layer on the first mask layer;
performing photoetching on the second mask layer based on the first photomask to form a second patterned mask layer, wherein a second opening pattern corresponding to the first photomask pattern is formed in the second patterned mask layer;
forming a third mask layer on the second patterned mask layer;
photoetching the third mask layer based on the second photomask to form a third patterned mask layer, wherein a third opening pattern corresponding to the second photomask pattern is formed in the third patterned mask layer;
and etching the first mask layer based on the third patterned mask layer and the second patterned mask layer to obtain the patterned etching mask layer.
In one embodiment, the forming a stacked structure in which a support layer and a sacrificial layer are alternately stacked on an upper surface of the substrate includes:
forming a first supporting layer on the upper surface of the substrate;
forming a first sacrificial layer on the upper surface of the first supporting layer;
forming a second supporting layer on the upper surface of the first sacrificial layer;
forming a second sacrificial layer on the upper surface of the second supporting layer;
and forming a third supporting layer on the upper surface of the second sacrificial layer.
In one embodiment, the first support layer, the second support layer, and the third support layer each comprise a silicon nitride layer and/or a silicon carbonitride layer, and the first sacrificial layer and the second sacrificial layer each comprise a silicon oxide layer.
In one embodiment, the forming an opening in the stacked structure based on the patterned etching mask layer, the opening exposing the sacrificial layer and removing the sacrificial layer based on the opening includes:
forming a first opening in the third supporting layer based on the patterned etching mask layer, wherein the second sacrificial layer is exposed out of the first opening;
removing the second sacrificial layer based on the first opening;
forming a second opening in the second supporting layer based on the patterned etching mask layer, wherein the second opening exposes the first sacrificial layer;
and removing the first sacrificial layer based on the second opening.
In one embodiment, each of the first openings exposes three adjacent capacitor holes.
In one embodiment, the center of each first opening coincides with the center of the area where the adjacent three capacitor holes are exposed by the first opening.
In one embodiment, the shape of the first opening and the shape of the second opening are both circular.
In one embodiment, the thickness of the third support layer is greater than the thickness of the first support layer and the thickness of the second support layer.
In one embodiment, after the removing the sacrificial layer based on the opening, the method further includes:
forming a capacitance dielectric layer on the surface of the lower electrode;
and forming an upper electrode on the surface of the capacitance medium layer.
In one embodiment, the upper electrode and the lower electrode each comprise a titanium nitride electrode; the capacitive dielectric layer includes a high-k dielectric layer.
The preparation method of the photomask component and the semiconductor structure has the following beneficial effects:
in the photomask assembly, the orthographic projection patterns of the second photomask patterns on the surfaces of the first photomasks are positioned between two adjacent rows of the first photomask patterns, the first photomask patterns and the orthographic projection patterns positioned in the same row are alternately arranged at intervals along a first direction, and the first photomask patterns positioned in the same row and the orthographic projection patterns positioned in the same row are arranged at intervals along a second direction, namely the first photomask patterns are not shielded when the second photomask patterns are adjusted; after forming the capacitor hole in the laminated structure comprising the support layer and the sacrificial layer which are alternately laminated and forming the lower electrode in the capacitor hole, when forming an opening in the support layer based on the photomask component, the center of the formed opening is overlapped with the center of the area between the three capacitor holes through flexible adjustment, so that the opening rate in the support layer can be remarkably increased, the opening formed in the support layer is maximized, and when the sacrificial layer below the support layer is removed based on the support layer, the risk of insufficient etching can be reduced, thereby improving the performance of the memory device.
The method for preparing the semiconductor structure comprises the steps of forming a patterned etching mask layer on a laminated structure by adopting the photomask assembly according to any one of the schemes, forming a plurality of etching opening patterns which are arranged in a plurality of rows and columns at intervals in the patterned etching mask layer, wherein the etching opening patterns in the same row are arranged at intervals along a first direction, the etching opening patterns in the same column are arranged at intervals along a second direction, and two adjacent etching opening patterns have a second dislocation distance along the second direction; after the capacitor holes are formed in the laminated structure of alternately laminated supporting layers and sacrificial layers and the lower electrode is formed in the capacitor holes, when an opening is formed in the supporting layers based on the photomask assembly, the center of the formed opening is overlapped with the center of the area between the three capacitor holes through flexible adjustment, the opening rate in the supporting layers can be remarkably increased, the opening formed in the supporting layers is maximized, and when the sacrificial layers below the supporting layers are removed based on the supporting layers, the risk of insufficient etching can be reduced, so that the performance of the memory device is improved.
Drawings
In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.
FIG. 1 is a schematic diagram of a photomask assembly according to one embodiment;
FIG. 2 is a flow chart illustrating a method of fabricating a semiconductor structure according to one embodiment;
fig. 3 is a schematic perspective view of a structure obtained in step S201 in a method for manufacturing a semiconductor structure according to an embodiment;
fig. 4 is a flowchart of step S202 in a method for fabricating a semiconductor structure according to an embodiment;
fig. 5 is a schematic perspective view of a structure obtained in step S2021 in a method for manufacturing a semiconductor structure according to an embodiment;
fig. 6 is a schematic perspective view of a structure obtained in step S2022 in the method for manufacturing a semiconductor structure according to an embodiment;
fig. 7 is a schematic perspective view of a structure obtained in step S2023 in the method for manufacturing a semiconductor structure according to an embodiment;
fig. 8 is a schematic perspective view of a structure obtained in step S2024 in the method for manufacturing a semiconductor structure according to an embodiment;
fig. 9 is a schematic perspective view of a structure obtained in step S2025 in the method for manufacturing a semiconductor structure according to an embodiment;
fig. 10 is a schematic flow chart of step S203 in the method for manufacturing a semiconductor structure according to an embodiment;
fig. 11 is a schematic perspective view of a structure obtained in step S203 in the method for manufacturing a semiconductor structure according to an embodiment;
fig. 12 is a schematic perspective view of a structure obtained in step S204 in the method for manufacturing a semiconductor structure according to an embodiment;
fig. 13 is a flowchart illustrating a step S205 in a method for fabricating a semiconductor structure according to an embodiment;
fig. 14 is a schematic diagram showing a three-dimensional structure of a structure obtained in step S2051 in a method for manufacturing a semiconductor structure according to an embodiment;
fig. 15 is a schematic perspective view of a structure obtained in step S2052 in the method for manufacturing a semiconductor structure according to an embodiment;
fig. 16 is a schematic perspective view of a structure obtained in step S2053 in the method for manufacturing a semiconductor structure according to an embodiment;
fig. 17 is a schematic diagram showing a three-dimensional structure of a structure obtained in step S2054 in the method for manufacturing a semiconductor structure according to an embodiment;
fig. 18 is a schematic diagram showing a three-dimensional structure of a structure obtained in step S2055 in the method for manufacturing a semiconductor structure according to an embodiment;
fig. 19 is a schematic diagram showing a three-dimensional structure of a structure obtained in step S2056 in the method for manufacturing a semiconductor structure according to an embodiment;
fig. 20 is a schematic top view of a structure obtained in step S2056 in a method for manufacturing a semiconductor structure according to an embodiment;
fig. 21 is a flow chart illustrating a step S206 in the method for fabricating a semiconductor structure according to an embodiment;
fig. 22 is a schematic cross-sectional view of the structure obtained in step S2061 in the method for manufacturing a semiconductor structure according to the embodiment;
FIG. 23 is a schematic cross-sectional view of the structure obtained in step S2062 in the method for fabricating a semiconductor structure according to one embodiment;
fig. 24 is a schematic cross-sectional view of the structure obtained in step S2063 in the method for manufacturing a semiconductor structure according to the embodiment;
fig. 25 is a schematic cross-sectional view of the structure obtained in step S2064 in the method for manufacturing a semiconductor structure according to the embodiment;
fig. 26 is a schematic cross-sectional structure of the structure obtained in step S207 in the method for manufacturing a semiconductor structure according to an embodiment;
fig. 27 is a schematic cross-sectional view of the structure obtained in step S208 in the method for manufacturing a semiconductor structure according to an embodiment.
Reference numerals illustrate:
100. a first photomask pattern; 200. orthographic projection graphics; 1. a substrate; 21. a first support layer; 22. a second support layer; 23. a third support layer; 31. a first sacrificial layer; 32. a second sacrificial layer; 4. a capacitor hole; 41. a lower electrode; 42. a capacitance dielectric layer; 43. an upper electrode; 5. patterning the etching mask layer; 51. etching the opening pattern; 54. a first mask layer; 55. a second mask layer; 56. a second patterned mask layer; 561. a second opening pattern; 57. a third mask layer; 58. a third patterned mask layer; 581. a third opening pattern; 6. a first opening.
Detailed Description
In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and/or sections, these elements, components, regions, layers, doping types and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or section from another element, component, region, layer, doping type or section. Thus, a first element, component, region, layer, doping type or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention; for example, the first doping type may be made the second doping type, and similarly, the second doping type may be made the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
Spatially relative terms, such as "under", "below", "beneath", "under", "above", "over" and the like, may be used herein to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. Furthermore, the device may also include an additional orientation (e.g., rotated 90 degrees or other orientations) and the spatial descriptors used herein interpreted accordingly.
As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. Also, as used herein, the term "and/or" includes any and all combinations of the associated listed items.
Embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention, such that variations of the illustrated shapes due to, for example, manufacturing techniques and/or tolerances are to be expected. Thus, embodiments of the present invention should not be limited to the particular shapes of the regions illustrated herein, but rather include deviations in shapes that result, for example, from manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and/or implant concentration gradients at its edges rather than a binary change from implanted to non-implanted regions. Also, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface over which the implantation is performed. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the invention.
The embodiment provides a method for manufacturing a semiconductor structure, and a DRAM (Dynamic Random Access Memory ) is a commonly used semiconductor memory device and is composed of a plurality of repeated memory cells. The DRAM stores data in the form of storing charge on the capacitor, which needs to be regularly charged and discharged every several milliseconds. In the preparation process of the DRAM device, after a capacitor hole and a lower electrode are formed in a laminated structure comprising a supporting layer and a sacrificial layer which are sequentially overlapped from bottom to top, when a patterned mask layer is formed on the laminated structure based on a photomask and used for forming an opening in the supporting layer, due to Overlay (OVL) deviation, the opening formed in the supporting layer is less, so that when the sacrificial layer positioned below the supporting layer is removed based on the opening, underetching (underetching) is easy to occur to cause the residual of the sacrificial layer, and the performance of the DRAM device is affected.
In view of the foregoing, it is desirable to provide a photomask assembly and a method for manufacturing a semiconductor structure.
To achieve the above object, an embodiment of the present invention provides a photomask assembly, as shown in fig. 1, including: a first photomask and a second photomask (not shown); the first photomask is internally provided with a plurality of first photomask patterns 100, and the plurality of first photomask patterns 100 are arranged in a plurality of rows and columns at intervals; the second photomask is internally provided with a plurality of second photomask patterns which are arranged in a plurality of rows and columns at intervals; the orthographic projection pattern 200 of each row of second photomask patterns on the surface of the first photomask is positioned between two adjacent rows of first photomask patterns 100; the first photomask patterns 100 and the front projection patterns 200 positioned in the same row are alternately arranged at intervals along the first direction, and the first photomask patterns 100 positioned in the same column and the front projection patterns 200 positioned in the same column are both arranged at intervals along the second direction.
In the photomask assembly of the embodiment, the orthographic projection patterns of the second photomask patterns on the surface of the first photomask are located between two adjacent rows of the first photomask patterns 100, the first photomask patterns 100 and the orthographic projection patterns 200 located in the same row are alternately arranged at intervals along the first direction, the first photomask patterns 100 located in the same row and the orthographic projection patterns located in the same row are all arranged at intervals along the second direction, that is, the first photomask patterns 100 are not blocked when the second photomask patterns are adjusted, after capacitor holes are formed in a laminated structure comprising alternately laminated supporting layers and sacrificial layers and lower electrodes are formed in the capacitor holes, when openings are formed in the supporting layers based on the photomask assembly, the centers of the formed openings are overlapped with the centers of the areas between the three capacitor holes, the opening ratio in the supporting layers can be remarkably increased, the openings formed in the supporting layers are maximized, and when the sacrificial layers below the supporting layers are removed based on the supporting layers, the risk of insufficient etching can be reduced, and therefore the performance of the memory device is improved.
In one embodiment, referring to fig. 1, the first photomask pattern 100 and the orthographic pattern 200 located in the same row have a first offset pitch along the second direction.
In one embodiment, the width of the first photomask pattern 100 may be the same as the width of the second photomask pattern, and the first misalignment distance is 1/6 to 1/3 of the width of the first photomask pattern 100 or the width of the second photomask pattern.
Specifically, the first misalignment distance may be 1/6, 1/5, 1/4, or 1/3 of the width of the first photomask pattern 100; any other width may be used, which is 1/6 to 1/3 of the width of the first photomask pattern 100, and is not limited by the above-described examples.
Of course, in other examples, the first photomask pattern 100 and the orthographic pattern 200 located in the same row may also be aligned along the second direction.
The application further provides a method for preparing a semiconductor structure, as shown in fig. 2, where the method for preparing a semiconductor structure may include the following steps:
s201: providing a substrate;
s202: forming a laminated structure of alternately laminated supporting layers and sacrificial layers on the upper surface of a substrate;
s203: forming a capacitor hole in the laminated structure; the capacitor hole penetrates through the supporting layer and the sacrificial layer;
s204: forming a lower electrode on the side wall and the bottom of the capacitor hole;
s205: forming a patterned etching mask layer on the laminated structure based on the photomask component of any scheme, wherein a plurality of etching opening patterns which are arranged in a plurality of rows and a plurality of columns at intervals are formed in the patterned etching mask layer, the etching opening patterns positioned in the same row are arranged at intervals along a first direction, the etching opening patterns positioned in the same column are arranged at intervals along a second direction, and two adjacent columns of etching opening patterns have a second dislocation distance along the second direction;
s206: and forming an opening in the laminated structure based on the patterned etching mask layer, exposing the sacrificial layer through the opening, and removing the sacrificial layer based on the opening.
In the method for manufacturing the semiconductor structure of the embodiment, the photomask assembly according to any one of the above schemes is adopted to form a patterned etching mask layer on the laminated structure, a plurality of etching opening patterns which are arranged in a plurality of rows and columns at intervals are formed in the patterned etching mask layer, the etching opening patterns in the same row are arranged at intervals along a first direction, the etching opening patterns in the same column are arranged at intervals along a second direction, and two adjacent columns of etching opening patterns have a second dislocation distance along the second direction; after the capacitor holes are formed in the laminated structure of alternately laminated supporting layers and sacrificial layers and the lower electrode is formed in the capacitor holes, when an opening is formed in the supporting layers based on the photomask assembly, the center of the formed opening is overlapped with the center of the area between the three capacitor holes through flexible adjustment, the opening rate in the supporting layers can be remarkably increased, the opening formed in the supporting layers is maximized, and when the sacrificial layers below the supporting layers are removed based on the supporting layers, the risk of insufficient etching can be reduced, so that the performance of the memory device is improved.
In step S201, referring to step S201 in fig. 2 and fig. 3, a substrate 1 is provided.
In one example, the substrate 1 may include, but is not limited to, a silicon substrate, a silicon carbide substrate, or a gallium nitride substrate, among others.
In another example, device structures such as buried gate word lines and bit lines may be formed in the substrate 1, which are not shown in fig. 3.
In step S202, referring to step S202 in fig. 2 and fig. 4 to 9, a stacked structure in which a support layer and a sacrificial layer are alternately stacked is formed on the upper surface of the substrate 1.
In one embodiment, as shown in fig. 4, in S202, forming a stacked structure in which a support layer and a sacrificial layer are alternately stacked on an upper surface of a substrate 1 may include the following steps:
s2021: forming a first support layer 21 on the upper surface of the substrate 1 as shown in fig. 5;
s2022: forming a first sacrificial layer 31 on the upper surface of the first supporting layer 21 as shown in fig. 6;
s2023: forming a second support layer 22 on the upper surface of the first sacrificial layer 31, as shown in fig. 7;
s2024: forming a second sacrificial layer 32 on the upper surface of the second support layer 22, as shown in fig. 8;
s2025: a third supporting layer 23 is formed on the upper surface of the second sacrificial layer 32 as shown in fig. 9.
In one embodiment, each of the first support layer 21, the second support layer 22 and the third support layer 23 may include, but is not limited to, a single-layer structure including, but not limited to, a silicon nitride layer or a silicon carbonitride layer, and may also include, but is not limited to, a double-layer structure or a multi-layer structure in which a silicon nitride layer and a silicon carbonitride layer are stacked in order. The first sacrificial layer 31 and the second sacrificial layer 32 may each include, but are not limited to, a silicon oxide layer.
In one embodiment, in each of the above steps, the first support layer 21, the second support layer 22, the third support layer 23, the first sacrificial layer 31 and the second sacrificial layer 32 may be formed by, but not limited to, a physical vapor deposition process, a chemical vapor deposition process or an atomic deposition process.
In one embodiment, the thickness of the third support layer 23 may be greater than the thickness of the first support layer 21 and the thickness of the second support layer 22.
The thickness of the third support layer 23 may be 180nm to 300nm, and specifically, the thickness of the third support layer 23 may be 180nm, 200nm, 250nm, 300nm, or the like; the thickness of the second support layer 22 may be 8nm to 50nm, and specifically, the thickness of the second support layer 22 may be 8nm, 10nm, 20nm, 30nm, 40nm, 50nm, or the like; the thickness of the first support layer 21 may be 6nm to 20nm, and specifically, the thickness of the first support layer 21 may be 6nm, 10nm, 15nm or 20nm; the thickness of the first sacrificial layer 31 may be 200nm to 500nm, specifically, the thickness of the first sacrificial layer 31 may be 200nm, 300nm, 400nm, 500nm, or the like; the thickness of the second sacrificial layer 32 may be 400nm to 500nm, and in particular, the thickness of the second sacrificial layer 32 may be 400nm, 450nm, 500nm, or the like.
In step S203, referring to step S203 in fig. 2 and fig. 10 to 11, a capacitor hole 4 is formed in the stacked structure; the capacitor holes 4 penetrate the supporting layer and the sacrificial layer.
In one embodiment, as shown in fig. 10, in S203, forming a capacitor hole in the stacked structure may include the following steps:
s2031: forming a first patterned mask layer (not shown) on the upper surface of the laminated structure, wherein a plurality of first opening patterns (not shown) are formed in the first patterned mask layer, and the first opening patterns define the shape and the position of the capacitor hole;
s2032: etching the laminated structure based on the first patterned mask layer to form a capacitor hole 4 in the laminated structure, as shown in fig. 11;
s2033: removing the first patterned mask layer; the structure after removing the first patterned mask layer is shown in fig. 11.
In one embodiment, in step S2031, a hard mask layer (such as a silicon nitride layer or the like) may be formed prior to the upper surface of the stacked structure; then forming a photoresist layer on the upper surface of the hard mask layer; exposing and developing the photoresist layer to obtain a patterned photoresist layer; etching the hard mask layer based on the patterned photoresist layer to obtain a patterned hard mask layer, wherein the patterned hard mask layer is the first patterned mask layer; and finally, removing the patterned photoresist layer.
In one embodiment, in step S2032, a dry etching process may be used to etch the stack structure based on the first patterned mask layer.
In one embodiment, in step S2033, the first patterned mask layer may be removed using a chemical mechanical polishing process or an etching process.
In step S204, referring to step S204 in fig. 2 and fig. 12, a bottom electrode 41 is formed on the sidewall and bottom of the capacitor hole 4.
In one example, the lower electrode 41 may include, but is not limited to, a titanium nitride electrode.
In one embodiment, the bottom electrode 41 may be formed on the sidewall and bottom of the capacitor hole 4 using, but not limited to, an electroplating process or a deposition process.
It should be noted that, the thickness of the lower electrode 41 is smaller than half the radius of the capacitor hole 4, and even smaller, so that after the lower electrode 41 is deposited, enough space is still provided in the capacitor hole 4 for forming the capacitor dielectric layer and the upper electrode later.
In step S205, referring to step S205 in fig. 2 and fig. 13 to 20, a patterned etching mask layer 5 is formed on the stacked structure based on the photomask assembly according to any of the above schemes, and a plurality of etching opening patterns 51 arranged in a plurality of rows and columns at intervals are formed in the patterned etching mask layer 5, the etching opening patterns 51 located in the same row are arranged at intervals along the first direction, the etching opening patterns 51 located in the same column are arranged at intervals along the second direction, and two adjacent columns of etching opening patterns 51 have a second offset distance along the second direction.
Specifically, the second dislocation pitch may be 1/6, 1/5, 1/4, or 1/3 of the width of the etched opening pattern 51; any width of 1/6 to 1/3 of the width of the etched opening pattern 51 may be used, and the present invention is not limited to the above-described example.
In one embodiment, as shown in fig. 13, in S205, forming a patterned etching mask layer on the stacked structure based on the photomask assembly according to any of the above aspects may include the following steps:
s2051: forming a first mask layer 54 on the upper surface of the laminated structure; specifically, a first mask layer 54 may be formed on the upper surface of the third support layer 23, as shown in fig. 14;
s2052: forming a second mask layer 55 on the first mask layer 54, as shown in fig. 15;
s2053: etching the second mask layer 55 based on the first photomask to form a second patterned mask layer 56, wherein a second opening pattern 561 corresponding to the first photomask pattern is formed in the second patterned mask layer 56, as shown in fig. 16;
s2054: forming a third mask layer 57 on the second patterned mask layer 56, as shown in fig. 17;
s2055: etching the third mask layer 57 based on the second photomask to form a third patterned mask layer 58, wherein a third opening pattern 581 corresponding to the second photomask pattern is formed in the third patterned mask layer 58, as shown in fig. 18;
s2056: the first mask layer 54 is etched based on the third patterned mask layer 58 and the second patterned mask layer 57 to obtain a patterned etched mask layer 5, as shown in fig. 19 and 20.
In one embodiment, referring to fig. 14 in step S2051, the first mask layer 54 may be formed on the upper surface of the stacked structure by a physical vapor deposition process or a chemical vapor deposition process. The first mask layer 54 may include, but is not limited to, a silicon nitride layer.
In one embodiment, referring to fig. 15 in step S2052, the second mask layer 55 may be formed on the first mask layer 54 using, but not limited to, a physical vapor deposition process or a chemical vapor deposition process. The second mask layer 55 may include, but is not limited to, a silicon oxide layer.
In one embodiment, referring to fig. 16, in step S2053, the second mask layer 55 may be etched using a dry etching process based on the first photomask to form the second patterned mask layer 56.
In one embodiment, referring to fig. 17, in step S2054, a physical vapor deposition process or a chemical vapor deposition process may be used to form the third mask layer 57 on the second patterned mask layer 56. The third mask layer 57 may include, but is not limited to, a silicon oxynitride layer.
In one embodiment, referring to fig. 18, in step S2055, the third mask layer 57 may be etched using a dry etching process based on the second photomask to form a third patterned mask layer 58.
In one embodiment, before forming the second mask layer 55 on the first mask layer 54, the method may further include the following steps:
forming a first Amorphous Carbon Layer (ACL) (not shown) on the first mask layer 54;
a first silicon oxynitride layer (not shown) is formed on the first amorphous carbon layer.
In one embodiment, before etching the second mask layer 55 based on the first photomask, the method may further include the following steps:
forming a first spin-on carbon layer (not shown) on the second mask layer 55;
a second silicon oxynitride layer (not shown) is formed on the first spin-on carbon layer.
In one embodiment, before forming the third mask layer 57 on the second patterned mask layer 56, the method may further include the following steps:
forming a second spin-on carbon layer (not shown) on the second patterned mask layer 56 and within the second opening pattern 561;
a third silicon oxynitride layer (not shown) is formed on the second spin-on carbon layer.
In step S206, referring to step S206 in fig. 2 and fig. 21 to 25, an opening is formed in the stacked structure based on the patterned etching mask layer 5, and the sacrificial layer is exposed by the opening; and removing the sacrificial layer based on the opening.
In one embodiment, as shown in fig. 21, in S206, forming an opening in the stacked structure based on the patterned etching mask layer 5, the opening exposing the sacrificial layer, and removing the sacrificial layer based on the opening may include the following steps:
s2061: forming a first opening 6 in the third support layer 23 based on the patterned etching mask layer 5, the first opening exposing the second sacrificial layer 32, as shown in fig. 22;
s2062: the second sacrificial layer 32 is removed based on the first opening 6 as shown in fig. 23;
s2063: forming a second opening (not shown) in the second support layer 22 based on the patterned etching mask layer 5, the second opening exposing the first sacrificial layer 31, as shown in fig. 24;
s2064: the first sacrificial layer 31 is removed based on the second opening as shown in fig. 25.
In one embodiment, since the first opening 6 corresponds to the etched opening pattern 51, please continue to refer to fig. 20, the shape and position of the etched opening pattern 51 identified in fig. 20 is the shape and position of the first opening 6. Each first opening 6 exposes three adjacent capacitor holes 4.
In one embodiment, the center of each first opening 6 may coincide with the center of the area where the first openings 6 expose the adjacent three capacitor holes, so that the maximum opening ratio may be obtained, so that the number of first openings 6 formed in the third supporting layer 23 is maximized, which is beneficial to reducing the problem of underetching.
In one embodiment, the shape of the first opening 6 and the shape of the second opening may both include, but are not limited to, circular; specifically, the circular shape is convenient for realizing that the center of the first opening 6 coincides with the center of the area where the adjacent three capacitance holes are exposed by the first opening 6, and the center of the second opening coincides with the center of the area where the adjacent three capacitance holes are exposed by the second opening.
In one embodiment, a wet etching process may be used to remove the first sacrificial layer 31 and the second sacrificial layer 32.
In one embodiment, after the sacrificial layer is removed based on the opening, the method may further include the steps of:
s207: forming a capacitance dielectric layer 42 on the surface of the lower electrode 41, as shown in fig. 26;
s208: an upper electrode 43 is formed on the surface of the capacitor dielectric layer 42, as shown in fig. 27.
In one embodiment, the upper electrode 43 may include, but is not limited to, a titanium nitride electrode. The upper electrode 43 may be formed using, but not limited to, an electroplating or deposition process.
In one embodiment, the capacitive dielectric layer 42 may include, but is not limited to, a high-k dielectric layer to increase the capacitance value of a capacitor per unit area; specifically, the capacitance medium layer 42 may include, but is not limited to, a layer formed of one or more of ZrOx (zirconium oxide) layer, hfOx (hafnium oxide) layer, ruOx (ruthenium oxide) layer, and AlOx (aluminum oxide). The capacitive dielectric layer 42 may be formed using, but is not limited to, a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.
The technical features of the above embodiments may be arbitrarily combined, and for brevity, all of the possible combinations of the technical features of the above embodiments are not described, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples only represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the claims. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (15)
1. A photomask assembly, comprising:
the first photomask is internally provided with a plurality of first photomask patterns, and the plurality of first photomask patterns are arranged in a plurality of rows and columns at intervals;
the second photomask is internally provided with a plurality of second photomask patterns, and the second photomask patterns are arranged in a plurality of rows and columns at intervals; the orthographic projection patterns of the second photomask patterns of each column on the surface of the first photomask are positioned between two adjacent columns of the first photomask patterns; the first photomask patterns and the orthographic projection patterns which are positioned in the same row are alternately arranged at intervals along a first direction, and the first photomask patterns and the orthographic projection patterns which are positioned in the same column are arranged at intervals along a second direction.
2. The photomask assembly of claim 1, wherein the first photomask pattern and the orthographic pattern in the same row have a first offset pitch along a second direction.
3. The photomask assembly of claim 2, wherein the width of the first photomask pattern is the same as the width of the second photomask pattern, and the first misalignment distance is 1/6 to 1/3 of the width of the first photomask pattern or the width of the second photomask pattern.
4. A method of fabricating a semiconductor structure, comprising:
providing a substrate;
forming a laminated structure of alternately laminated supporting layers and sacrificial layers on the upper surface of the substrate;
forming a capacitor hole in the laminated structure; the capacitor hole penetrates through the supporting layer and the sacrificial layer;
forming a lower electrode on the side wall and the bottom of the capacitor hole;
forming a patterned etching mask layer on the laminated structure based on the photomask assembly according to any one of claims 1 to 3, wherein a plurality of etching opening patterns which are arranged in a plurality of rows and columns at intervals are formed in the patterned etching mask layer, the etching opening patterns positioned on the same row are arranged at intervals along a first direction, the etching opening patterns positioned on the same column are arranged at intervals along a second direction, and two adjacent columns of etching opening patterns have a second dislocation distance along the second direction;
and forming an opening in the laminated structure based on the patterned etching mask layer, wherein the opening exposes the sacrificial layer, and removing the sacrificial layer based on the opening.
5. The method of claim 4, wherein forming a capacitor hole in the stacked structure comprises:
forming a first patterned mask layer on the upper surface of the laminated structure, wherein a plurality of first opening patterns are formed in the first patterned mask layer, and the shapes and positions of the capacitor holes are defined by the first opening patterns;
etching the laminated structure based on the first patterned mask layer to form the capacitor hole in the laminated structure;
and removing the first patterned mask layer.
6. The method of manufacturing a semiconductor structure according to claim 5, wherein forming a patterned etching mask layer on the stacked structure based on the photomask assembly according to any of claims 1 to 3 comprises:
forming a first mask layer on the upper surface of the laminated structure;
forming a second mask layer on the first mask layer;
performing photoetching on the second mask layer based on the first photomask to form a second patterned mask layer, wherein a second opening pattern corresponding to the first photomask pattern is formed in the second patterned mask layer;
forming a third mask layer on the second patterned mask layer;
photoetching the third mask layer based on the second photomask to form a third patterned mask layer, wherein a third opening pattern corresponding to the second photomask pattern is formed in the third patterned mask layer;
and etching the first mask layer based on the third patterned mask layer and the second patterned mask layer to obtain the patterned etching mask layer.
7. The method of fabricating a semiconductor structure according to claim 4, wherein forming a stacked structure of alternately stacked support layers and sacrificial layers on an upper surface of the substrate comprises:
forming a first supporting layer on the upper surface of the substrate;
forming a first sacrificial layer on the upper surface of the first supporting layer;
forming a second supporting layer on the upper surface of the first sacrificial layer;
forming a second sacrificial layer on the upper surface of the second supporting layer;
and forming a third supporting layer on the upper surface of the second sacrificial layer.
8. The method of claim 7, wherein the first support layer, the second support layer, and the third support layer each comprise a silicon nitride layer and/or a silicon carbonitride layer, and wherein the first sacrificial layer and the second sacrificial layer each comprise a silicon oxide layer.
9. The method of claim 7, wherein forming an opening in the stacked structure based on the patterned etch mask layer, the opening exposing the sacrificial layer and removing the sacrificial layer based on the opening, comprises:
forming a first opening in the third supporting layer based on the patterned etching mask layer, wherein the second sacrificial layer is exposed out of the first opening;
removing the second sacrificial layer based on the first opening;
forming a second opening in the second supporting layer based on the patterned etching mask layer, wherein the second opening exposes the first sacrificial layer;
and removing the first sacrificial layer based on the second opening.
10. The method of claim 9, wherein each of the first openings exposes three adjacent capacitor holes.
11. The method of claim 10, wherein a center of each of the first openings coincides with a center of an area where adjacent three of the capacitor holes are exposed by the first opening.
12. The method of claim 9, wherein the shape of the first opening and the shape of the second opening are both circular.
13. The method of claim 7, wherein the thickness of the third support layer is greater than the thickness of the first support layer and the thickness of the second support layer.
14. The method of manufacturing a semiconductor structure according to any one of claims 4 to 13, wherein after the removing the sacrificial layer based on the opening, further comprising:
forming a capacitance dielectric layer on the surface of the lower electrode;
and forming an upper electrode on the surface of the capacitance medium layer.
15. The method of claim 14, wherein the upper electrode and the lower electrode each comprise a titanium nitride electrode; the capacitive dielectric layer includes a high-k dielectric layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210674446.7A CN117311081A (en) | 2022-06-15 | 2022-06-15 | Photomask assembly and preparation method of semiconductor structure |
| PCT/CN2022/101957 WO2023240684A1 (en) | 2022-06-15 | 2022-06-28 | Photomask assembly and method for preparing semiconductor structure |
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| CN202210674446.7A CN117311081A (en) | 2022-06-15 | 2022-06-15 | Photomask assembly and preparation method of semiconductor structure |
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| KR20100042469A (en) * | 2008-10-16 | 2010-04-26 | 주식회사 하이닉스반도체 | Method for forming contact hole of semiconductor device |
| CN106910677B (en) * | 2015-12-23 | 2020-12-18 | 中芯国际集成电路制造(上海)有限公司 | Patterning method for manufacturing semiconductor device, and semiconductor device manufacturing method |
| KR20200112218A (en) * | 2019-03-21 | 2020-10-05 | 삼성전자주식회사 | Semiconductor device having supporter pattern |
| KR20210027635A (en) * | 2019-08-29 | 2021-03-11 | 삼성전자주식회사 | Semiconductor device and method of fabricating the same |
| KR20210050319A (en) * | 2019-10-28 | 2021-05-07 | 삼성전자주식회사 | Method of manufacturing photomask set for forming patterns, and method of manufacturing semiconductor device using the photomask set |
| CN113206074B (en) * | 2021-04-30 | 2024-04-05 | 福建省晋华集成电路有限公司 | Semiconductor device and method for manufacturing the same |
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