CN117310262B - Primary side information detection circuit and detection chip of transformer - Google Patents

Primary side information detection circuit and detection chip of transformer Download PDF

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Publication number
CN117310262B
CN117310262B CN202311596378.8A CN202311596378A CN117310262B CN 117310262 B CN117310262 B CN 117310262B CN 202311596378 A CN202311596378 A CN 202311596378A CN 117310262 B CN117310262 B CN 117310262B
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unit
resistor
voltage
sampling
comparator
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CN117310262A (en
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强玮
汤琦
卿健
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Chengdu Yichong Wireless Power Technology Co ltd
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Chengdu Yichong Wireless Power Technology Co ltd
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/02—Measuring effective values, i.e. root-mean-square values
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
    • G01R23/02—Arrangements for measuring frequency, e.g. pulse repetition rate; Arrangements for measuring period of current or voltage
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

Abstract

The application provides a primary side information detection circuit and a detection chip of a transformer, wherein an upper computer is respectively connected with a reference voltage unit, a comparator and an analog-to-digital conversion unit; the input end of the voltage sampling unit is connected with the in-phase end of the secondary coil of the transformer, and the output end of the voltage sampling unit is connected with the in-phase input end of the comparator and the first end of the asynchronous sampling and holding unit; the output end of the reference voltage unit is connected with the inverting input end of the comparator; the output end of the comparator is connected with the second end of the asynchronous sample hold unit; the third end of the asynchronous sample hold unit is connected with the input end of the analog-to-digital conversion unit. The sampling process does not need software participation, the sampling operation process is completed by hardware self-adaption, the complexity of the system is reduced, an asynchronous sampling and holding signal is adopted, higher sampling precision can be obtained, primary side information can be accurately obtained, complete primary side information is provided for an upper computer on a secondary side, and therefore the system decision requirement of the upper computer is met.

Description

Primary side information detection circuit and detection chip of transformer
Technical Field
The application relates to the field of power supplies, in particular to a primary side information detection circuit and a detection chip of a transformer.
Background
The secondary side PD controller is typically used to control a power transistor connected to a secondary winding of the power supply system to control the output voltage on the secondary winding. In applications, it is necessary to detect the switching frequency, on-time, off-time and line voltage effective values of the primary side controller.
However, in the prior art, the circuit used in the detection of the primary side information is relatively complex, the detection cost is high, and the detection precision is low.
In summary, the prior art has the problems of complex primary side information detection circuit and high detection cost.
Disclosure of Invention
An objective of the present invention is to provide a primary side information detection circuit and a primary side information detection chip for a transformer, so as to at least partially improve the above-mentioned problems.
In order to achieve the above purpose, the technical solution adopted in the embodiment of the present application is as follows:
in a first aspect, an embodiment of the present application provides a primary side information detection circuit of a transformer, where the detection circuit includes: the device comprises an upper computer, a reference voltage unit, a voltage sampling unit, a comparator, an asynchronous sample-hold unit and an analog-digital conversion unit;
the upper computer is respectively connected with the control end of the reference voltage unit, the output end of the comparator and the output end of the analog-to-digital conversion unit;
the input end of the voltage sampling unit is used for being connected with the in-phase end of the secondary coil of the transformer, and the output end of the voltage sampling unit is connected with the in-phase input end of the comparator and the first end of the asynchronous sampling and holding unit;
the output end of the reference voltage unit is connected with the inverting input end of the comparator;
the output end of the comparator is also connected with the second end of the asynchronous sample hold unit;
and the third end of the asynchronous sample and hold unit is connected with the input end of the analog-digital conversion unit.
Optionally, the upper computer is used for controlling the reference voltage unit to output a reference voltage;
the voltage sampling unit is used for sampling the voltage of the same phase end of the secondary coil so as to obtain and output a first sampling voltage;
the comparator is used for outputting an opening signal when the first sampling voltage is larger than the reference voltage;
the upper computer is used for carrying out statistical analysis on the starting signal to obtain the working frequency of the primary side, the on-time and the off-time of the primary side in each working period;
the asynchronous sample hold unit is used for sampling the output voltage of the voltage sampling unit when the comparator outputs an opening signal to obtain a second sampling voltage, and keeping the second sampling voltage unchanged when the comparator stops outputting the opening signal;
the analog-to-digital conversion unit is used for performing digital-to-analog conversion on the second sampling voltage and transmitting the converted voltage value to the upper computer;
the upper computer is used for acquiring the effective value of the primary line voltage based on the voltage value.
Optionally, the asynchronous sample hold unit includes a blanking module, a sampling module, a first inverter, a hold module, a first capacitor, a second capacitor, a first switching tube, and a second switching tube;
the first end of the first switch tube is used as the first end of the asynchronous sample-hold unit and is connected with the output end of the voltage sampling unit, the second end of the first switch tube is connected with the first end of the second switch tube, one end of the first capacitor is grounded, the other end of the first capacitor is connected between the first switch tube and the second switch tube, the second end of the second switch tube is connected with one end of the second capacitor, the other end of the second capacitor is grounded, a first wiring terminal is led out between the second switch tube and the second capacitor and is used as the third end of the asynchronous sample-hold unit, and the third end of the asynchronous sample-hold unit is connected with the input end of the analog-to-digital conversion unit;
the input end of the blanking module is used as a second end of the asynchronous sample hold unit and is connected with the output end of the comparator;
the output end of the blanking module is connected with the input end of the sampling module, the first output end of the sampling module is connected with the input end of the first phase inverter, and the second output end of the sampling module is connected with the control end of the first switching tube;
the output end of the first inverter is connected with the input end of the holding module, and the output end of the holding module is connected with the control end of the second switching tube.
Optionally, the detection circuit further includes a voltage division attenuation unit, and the voltage division attenuation unit includes an operational amplifier;
the in-phase input end of the operational amplifier is connected with the third end of the asynchronous sample hold unit, the reverse input end of the operational amplifier is connected with the output end of the operational amplifier, a second wiring terminal is led out of the output end of the operational amplifier, and the second wiring terminal is connected with the input end of the analog-digital conversion unit.
Optionally, the voltage division attenuation unit further comprises a first resistor and a second resistor;
one end of the first resistor is connected with the output end of the operational amplifier, the other end of the first resistor is connected with one end of the second resistor, and the other end of the second resistor is grounded;
and a third wiring terminal is led out between the first resistor and the second resistor, and is connected with the reference voltage unit.
Optionally, the reference voltage unit includes a third resistor, a fourth resistor, a bias power supply, a second inverter, a third switching tube and a fourth switching tube;
the first end of the third resistor is connected to the primary side of the primary coil of the transformer, the other end of the third resistor is connected to one end of the fourth resistor, and the other end of the fourth resistor is grounded;
the input end of the bias power supply is connected between the third resistor and the fourth resistor, the output end of the bias power supply is connected with the first end of the fourth switching tube, the second end of the fourth switching tube is connected with the second end of the third switching tube, and the first end of the third switching tube is connected with the third wiring terminal;
a fourth connecting terminal is led out between the third switching tube and the fourth switching tube and is used as the output end of the reference voltage unit and is connected with the inverting input end of the comparator;
the control end of the third switching tube is connected with the output end of the second inverter, the control end of the fourth switching tube is connected with the input end of the second inverter, a fifth connecting terminal is led out between the input end of the second inverter and the control end of the fourth switching tube and is used as the control end of the reference voltage unit to be connected with the upper computer.
Optionally, the voltage sampling unit includes a fifth resistor and a sixth resistor;
the first end of the fifth resistor is used as an input end of the voltage sampling unit and is connected with the same-phase end of the secondary coil of the transformer;
the second end of the fifth resistor is connected with the first end of the sixth resistor, and the second end of the sixth resistor is grounded;
and a sixth wiring terminal is led out between the fifth resistor and the sixth resistor, and the sixth wiring terminal is connected with the non-inverting input end of the comparator and the first end of the asynchronous sample hold unit.
Optionally, the voltage sampling unit further includes a seventh resistor, one end of the seventh resistor is connected to the sixth connection terminal, and the other end of the seventh resistor is connected to the non-inverting input end of the comparator and the first end of the asynchronous sample hold unit.
Optionally, the detection circuit further includes a third capacitor, one end of the third capacitor is connected to the input end of the analog-to-digital conversion unit, and the other end of the third capacitor is grounded.
In a second aspect, an embodiment of the present application provides a detection chip, including: the primary side information detection circuit of the transformer.
Compared with the prior art, the primary side information detection circuit and the primary side information detection chip of the transformer provided by the embodiment of the application comprise: the device comprises an upper computer, a reference voltage unit, a voltage sampling unit, a comparator, an asynchronous sample-hold unit and an analog-digital conversion unit; the upper computer is respectively connected with the control end of the reference voltage unit, the output end of the comparator and the output end of the analog-to-digital conversion unit; the input end of the voltage sampling unit is used for being connected with the same phase end of the secondary coil of the transformer, and the output end of the voltage sampling unit is connected with the same phase input end of the comparator and the first end of the asynchronous sampling and holding unit; the output end of the reference voltage unit is connected with the inverting input end of the comparator; the output end of the comparator is also connected with the second end of the asynchronous sample hold unit; the third end of the asynchronous sample hold unit is connected with the input end of the analog-to-digital conversion unit. The whole sampling operation process is completed completely by hardware self-adaption without software participation in the sampling process, the complexity of the system is reduced, an asynchronous sampling and holding unit adopts an asynchronous sampling and holding signal, higher sampling precision can be obtained, primary side information (comprising a primary side line voltage effective value, a primary side working frequency, and the on-time and off-time of the primary side in each working period) can be accurately obtained, and complete primary side information is provided for an upper computer of a secondary side, so that the system decision requirement of the upper computer is met.
In order to make the above objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered limiting in scope, and that other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a system diagram of a secondary side PD controller provided in an embodiment of the present application;
fig. 2 is one of connection schematic diagrams of a primary side information detection circuit of a transformer according to an embodiment of the present application;
fig. 3 is a second connection schematic diagram of the primary side information detection circuit of the transformer according to the embodiment of the present application;
fig. 4 is a primary side information detection waveform diagram provided in an embodiment of the present application;
fig. 5 is a schematic diagram of a voltage waveform of a VD stage of a secondary transformer of a transformer according to an embodiment of the present application.
In the figure: 110-an upper computer; 120-reference voltage unit; 130-a voltage sampling unit; 140-an asynchronous sample-and-hold unit; 141-a blanking module; 142-a sampling module; 143-a holding module; 150-an analog-to-digital conversion unit; 160-a partial pressure decay unit.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
In the description of the present application, it should be noted that, the terms "upper," "lower," "inner," "outer," and the like indicate an orientation or a positional relationship based on the orientation or the positional relationship shown in the drawings, or an orientation or a positional relationship conventionally put in use of the product of the application, merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element to be referred to must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the present application.
In the description of the present application, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "connected," and "connected" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art in a specific context.
Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.
As described in the background, the secondary side PD controller is typically used to control a power transistor connected to a secondary winding of a power supply system to control an output voltage on the secondary winding, and in application, the system diagram of the secondary side PD controller is shown in fig. 1, and fig. 1 is a system diagram of the secondary side PD controller provided in an embodiment of the present application.
As shown in fig. 1, the transformer includes a primary winding and a secondary winding, a first end of the primary winding is used for being connected to a primary line Voltage (VIN), the other end of the primary winding is connected to a first end of a third power transistor Q3, a second end of the third power transistor Q3 is grounded, and a third end of the third power transistor Q3 is connected to an output end of the AC/DC controller. The AC/DC controller may control the third power transistor Q3 to switch the switching state, where the AC/DC controller controls the switching frequency of the third power transistor Q3 to be the primary side working frequency of the transformer, the on duration of the third power transistor Q3 in a single working period is the on duration of the primary side in the working period, and the off duration of the third power transistor Q3 in the single working period is the off duration of the primary side in the working period.
As shown in fig. 1, the first end of the secondary winding is connected to the first end of the fourth transistor Q4, the second end of the fourth transistor Q4 is connected to the back end of VBUS, and the third end of the fourth transistor Q4 is connected to the GATE end of the secondary side PD controller; the first terminal of the secondary rectifying controller is connected between the first terminal of the secondary winding and the first terminal of the fourth transistor Q4.
The second end of the secondary coil is connected to the first end of the fifth transistor Q5, the second end of the fifth transistor Q5 is grounded, the third end of the fifth transistor Q5 is connected to the second end of the secondary rectifying controller, one end of the ninth resistor R9 is connected to the first end of the fifth transistor Q5, the other end of the ninth resistor R9 is connected to one pole of the fourth capacitor C4, and the other pole of the fourth capacitor C4 is connected to the second end of the fifth transistor Q5.
The third terminal of the secondary rectifying controller is connected to the first terminal of the fifth transistor Q5, and the VD terminal of the secondary side PD controller is connected to the first terminal of the fifth transistor Q5 through a tenth resistor R10. The VBUS end of the secondary side PD controller is connected to the VBUS back end through an eighth resistor R8.
As described in the background art, in application, the working frequency of the primary side, the on-time of the primary side in the working period, the off-time of the primary side in the working period, and the effective value of the primary side line voltage need to be detected.
As shown in fig. 1, the secondary side PD controller is connected to the secondary winding of the transformer, and by acquiring information on the secondary winding, the above information is detected, and the on-off state and the on-off frequency of the power transistor on the main circuit are controlled, so as to control the output voltage on the secondary winding.
However, the detection circuit in the related secondary side PD controller is complex, and in view of this, the embodiment of the present application provides a primary side information detection circuit of a transformer, which realizes detection of primary side information through a simpler circuit structure, and reduces the cost.
Referring to fig. 2, fig. 2 is a schematic connection diagram of a primary side information detection circuit of a transformer according to an embodiment of the present application. As shown in fig. 2, the detection circuit includes: the device comprises a host computer 110, a reference voltage unit 120, a voltage sampling unit 130, a comparator U1, an asynchronous sample-and-hold unit 140 and an analog-to-digital conversion unit 150.
The analog-to-digital conversion unit 150 may be an ADC, and the upper computer 110 may be a general-purpose processor, including a central processing unit (Central Processing Unit, abbreviated as CPU), a network processor (Network Processor, abbreviated as NP), and the like; but also digital signal processors (Digital Signal Processor, DSP for short), application specific integrated circuits (Application Specific Integrated Circuit, ASIC for short), field-programmable gate arrays (Field-Programmable Gate Array, FPGA for short), MCUs or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.
The upper computer 110 is connected to the control end of the reference voltage unit 120, the output end of the comparator U1, and the output end of the analog-to-digital conversion unit 150, respectively.
The input terminal of the voltage sampling unit 130 is used for connecting to the non-inverting terminal of the secondary winding of the transformer, which is also referred to as VDS terminal (which may be, but is not limited to, point B in fig. 1), and the output terminal of the voltage sampling unit 130 is connected to the non-inverting input terminal of the comparator U1 and the first terminal of the asynchronous sample-and-hold unit 140.
The output terminal of the reference voltage unit 120 is connected to the inverting input terminal of the comparator U1.
The output of the comparator U1 is also connected to a second terminal of the asynchronous sample hold unit 140.
A third terminal of the asynchronous sample hold unit 140 is connected to an input terminal of the analog-to-digital conversion unit 150.
Optionally, the upper computer 110 is configured to control the reference voltage unit 120 to output a reference voltage.
Alternatively, the upper computer 110 may send different types of trigger signals, such as a high level trigger signal or a low level trigger signal, to the reference voltage unit 120, and the reference voltage unit 120 may output different reference voltages under the different types of trigger signals.
The voltage sampling unit 130 is configured to sample a voltage at the non-inverting terminal of the secondary coil to obtain and output a first sampled voltage.
Optionally, the first sampled voltage is one-nth of the VD plateau voltage (voltage value at point B).
The comparator U1 is configured to output an on signal when the first sampling voltage is greater than the reference voltage.
Optionally, the comparator U1 is configured to compare the first sampling voltage with the reference voltage, and output an ON Signal (ON Signal), for example, a high level Signal "1", when the first sampling voltage is greater than the reference voltage, and output an ON Signal (ON Signal), for example, a low level Signal "0", when the first sampling voltage is less than the reference voltage.
The upper computer 110 is configured to perform statistical analysis on the on signal to obtain a primary working frequency, a turn-on duration and a turn-off duration of the primary in each working period.
Alternatively, a rising edge occurs in the ON Signal (ON Signal) when the AC/DC controller controls the third power transistor Q3 to switch to the ON state, and a falling edge occurs in the ON Signal when the AC/DC controller controls the third power transistor Q3 to switch to the off state. By carrying out statistical analysis on the starting signals of the continuous periods, the working frequency of the primary side corresponding to each working period and the on-time and off-time of the primary side in each working period can be determined.
The asynchronous sample hold unit 140 is configured to sample the output voltage of the voltage sampling unit 130 when the comparator U1 outputs the on signal, to obtain a second sampled voltage, and to keep the second sampled voltage unchanged when the comparator U1 stops outputting the on signal.
Optionally, the second sampled voltage is equal to the first sampled voltage.
Alternatively, the asynchronous sample-and-hold unit 140 may asynchronously generate the sample signal and the hold signal, so that sampling offset caused by mutual interference of the sample signal and the hold signal due to charge injection problem may be avoided, and sampling accuracy is greatly improved.
The analog-to-digital conversion unit 150 is configured to perform digital-to-analog conversion on the second sampled voltage, and transmit the converted voltage value to the host computer 110.
The upper computer 110 is configured to obtain a primary line voltage effective value based on the voltage value.
Optionally, the active value of the primary line voltage is the active value of the voltage VIN corresponding to the point a in fig. 1.
The primary side information detection circuit of the transformer has self-adaptive characteristics, the system architecture can be simplified, sampling and holding signals can be obtained only by one comparator U1, meanwhile, software is not required to adjust sampling time and holding time according to different working states, the whole sampling process is completed automatically by hardware, and the complexity of the system is greatly reduced.
The embodiment of the application also provides an alternative implementation manner for the structure of each module in the primary side information detection circuit of the transformer on the basis of fig. 2. Referring to fig. 3, fig. 3 is a second connection schematic diagram of a primary side information detection circuit of a transformer according to an embodiment of the present application.
As shown in fig. 3, in an alternative embodiment, the asynchronous sample-and-Hold unit 140 includes a Blanking module 141 (also called a Blanking Time module), a Sampling module 142 (also called a Sampling Time module), a first inverter F1, a holding module 143 (also called a Hold Time module), a first capacitor C1, a second capacitor C2, a first switching tube TG1, and a second switching tube TG2.
The first end of the first switch tube TG1 is used as the first end of the asynchronous sample hold unit 140 and is connected to the output end of the voltage sample unit 130, the second end of the first switch tube TG1 is connected to the first end of the second switch tube TG2, one end of the first capacitor C1 is grounded, the other end of the first capacitor C1 is connected between the first switch tube TG1 and the second switch tube TG2, the second end of the second switch tube TG2 is connected to one end of the second capacitor C2, the other end of the second capacitor C2 is grounded, a first connecting terminal is led out between the second switch tube TG2 and the second capacitor C2 and is used as the third end of the asynchronous sample hold unit 140 and is connected to the input end of the analog-to-digital conversion unit 150.
The input terminal of the blanking module 141 is connected to the output terminal of the comparator U1 as a second terminal of the asynchronous sample-and-hold unit 140.
The output end of the blanking module 141 is connected to the input end of the sampling module 142, the first output end of the sampling module 142 is connected to the input end of the first inverter F1, and the second output end of the sampling module 142 is connected to the control end of the first switching tube TG 1.
The output terminal of the first inverter F1 is connected to the input terminal of the holding module 143, and the output terminal of the holding module 143 is connected to the control terminal of the second switching tube TG2.
Referring to fig. 4, fig. 4 is a waveform diagram of primary side information detection according to an embodiment of the present application. Here, th_vd is a reference Voltage (also referred to as a VD Voltage comparison threshold), and Blanking Time represents a Blanking Time corresponding to the Blanking module 141, where the Blanking Time may be configured by an upper computer according to a system condition, VD Wave form represents a VD (platform) Voltage waveform, ON Signal is an ON Signal output by the comparator U1, sampling Signal is a Sampling Signal (also referred to as a Sampling Signal) output by the Sampling module 142, hold Signal is a holding Signal output by the holding module 143, and Hold Voltage is a holding Voltage, and optionally, since charging of the holding capacitor is required, the previous several periods are gradually increased.
In this embodiment, when the VD platform voltage increases, the ON Signal (ON Signal) output by the comparator U1 rises, and the ON Signal is transmitted to the sampling module 142 for sampling after being delayed by the blanking module 141 by the corresponding blanking time, and the sampling module 142 generates the sampling Signal Sample Signal. As can be seen from fig. 4, after the blanking module 141 performs the blanking process, the corresponding fluctuation space can be filtered, the signal after the blanking process is sampled, and the obtained sampled signal is more accurate and stable. The sampling module 142 transmits a sampling signal to a first switching tube TG1 (also referred to as a transmission gate TG 1), the first switching tube TG1 is switched to an on state, a first sampling voltage (one-nth of the VD platform voltage) output by the voltage sampling unit 130 is sampled to obtain a second sampling voltage, and the second sampling voltage is stored in the first capacitor C1, and at this time, the second switching tube TG2 (also referred to as a transmission gate TG 2) is in an off state.
When the VD platform voltage decreases, the sampling module 142 stops sending the sampling Signal Sample Signal, or sends a low level "0", the first switching tube TG1 is switched to an off state, the opening Signal (ON Signal) that the sampling module 142 transmits backward is processed by the first inverter F1 and then is transmitted to the holding module 143, the holding module 143 outputs the holding Signal Hold Signal at this time, controls the second switching tube TG2 to switch to an ON state, and transmits the second sampling voltage stored in the first capacitor C1 to the second capacitor C2, that is, the second sampling voltage ON the second capacitor C2 can be used by the analog-digital conversion unit 150 at the back end to perform digital-analog conversion.
It should be noted that, the second capacitor C2 is easily affected by the back-end ripple in the circuit, resulting in deviation of the conversion result of the analog-to-digital conversion unit 150. In order to avoid this problem, the embodiment of the present application further provides an alternative implementation, please continue to refer to fig. 3, where the detection circuit further includes a voltage division attenuation unit 160, and the voltage division attenuation unit 160 includes an operational amplifier U2.
The non-inverting input end of the operational amplifier U2 is connected to the third end of the asynchronous sample hold unit 140, the inverting input end of the operational amplifier U2 is connected to the output end of the operational amplifier U2, a second connecting terminal is led out from the output end of the operational amplifier U2, and the second connecting terminal is connected to the input end of the analog-digital conversion unit 150.
It should be noted that, the output voltage of the operational amplifier U2 is equal to the second sampling voltage on the second capacitor C2.
Referring to fig. 5, fig. 5 is a schematic diagram of a voltage waveform of a VD stage of a secondary transformer of a transformer according to an embodiment of the present application. When the transformer works normally, the VD platform voltage waveform at the SR (secondary) side changes according to the effective value of the primary line voltage VIN and the different loads connected at the back end of the VBUS. As shown in fig. 5, VIN is the equivalent value of the primary output ac power supply voltage, and NPS is the primary-secondary turn ratio (the turn ratio of the primary coil to the secondary coil) of the transformer.
Since the VD platform voltage waveform varies with the VIN effective value and the primary side operating frequency of the transformer, and there may be a resonance-like sinusoidal waveform (e.g., the resonance ripple in fig. 4) interfering with correctly sampling the line voltage information, in order to accurately detect the primary side information from the VD platform voltage waveform on the SR (secondary) side, an appropriate reference voltage (also referred to as a VD voltage comparison threshold) needs to be taken to compare with the VD platform voltage waveform, and correctly sample the VD platform voltage, where the VD platform voltage is equal to vbus+vin/NPS.
With continued reference to fig. 3, in an alternative embodiment, the voltage division attenuating unit 160 further includes a first resistor R1 and a second resistor R2.
One end of the first resistor R1 is connected to the output end of the operational amplifier U2, the other end of the first resistor R1 is connected to one end of the second resistor R2, and the other end of the second resistor R2 is grounded;
a third connection terminal is led out between the first resistor R1 and the second resistor R2, and is connected to the reference voltage unit 120.
Optionally, after the output voltage of the operational amplifier U2 is divided by the first resistor R1 and the second resistor R2, a reference voltage is provided to the reference voltage unit 120 through the third connection terminal, so that the reference voltage unit 120 adjusts the reference voltage, thereby avoiding the influence of resonant ripple.
With continued reference to fig. 3, in an alternative embodiment, the reference voltage unit 120 includes a third resistor R3, a fourth resistor R4, a bias power source osjvd, a second inverter F2, a third switching transistor TG3, and a fourth switching transistor TG4.
In an alternative embodiment, the ratio of the resistances of the third resistor R3 and the fourth resistor R4, the ratio of the resistances of the first resistor R1 and the second resistor R2, and the ratio of the resistances of the fifth resistor R5 and the sixth resistor R6 hereinafter may be the same, which are all 50:1, typically 120K/2.4K, where the first sampling voltage is 1 of 51 minutes of the VD stage voltage, that is, the value of N is 51.
The first end of the third resistor R3 is connected to the primary side of the primary winding of the transformer (e.g., point a in fig. 1, for accessing the primary line voltage VIN), and the other end of the third resistor R3 is connected to one end of the fourth resistor R4, and the other end of the fourth resistor R4 is grounded.
The input end of the bias power supply OS_VD is connected between the third resistor R3 and the fourth resistor R4, the output end of the bias power supply OS_VD is connected with the first end of the fourth switching tube TG4, the second end of the fourth switching tube TG4 is connected with the second end of the third switching tube TG3, and the first end of the third switching tube TG3 is connected with a third wiring terminal, namely, between the first resistor R1 and the second resistor R2.
A fourth connection terminal is led out between the third switching tube TG3 and the fourth switching tube TG4, and is connected to the inverting input terminal of the comparator U1 as the output terminal of the reference voltage unit 120.
The control end of the third switching tube TG3 is connected to the output end of the second inverter F2, the control end of the fourth switching tube TG4 is connected to the input end of the second inverter F2, and a fifth connection terminal is led out between the input end of the second inverter F2 and the control end of the fourth switching tube TG4, and is used as the control end of the reference voltage unit 120 to be connected to the upper computer 110.
In this embodiment, after the detection circuit is started and enabled, the upper computer 110 may output a Reset signal (reset_signal) to the fifth connection terminal, where the fourth switching tube TG4 is switched to the on state, and the third switching tube TG3 is switched to the off state due to the effect of the second inverter F2.
After the Vin voltage is sampled through the resistor network of the third resistor R3 and the fourth resistor R4, the bias voltage provided by the bias power source os_vd is superimposed, so as to obtain an initial reference voltage (also called VD voltage comparison threshold value), and the initial reference voltage is provided to the inverting input terminal of the comparator U1. The comparator U1 compares the reference voltage with the first sampling voltage output by the voltage sampling unit 130, so as to obtain an ON Signal (ON Signal), the upper computer 110 may calculate an interval time between two ON signals (ON Signal) to obtain a primary working frequency, and count a state duration of the ON Signal (ON Signal) to obtain a turn-ON duration and a turn-off duration of the primary in each working period.
Alternatively, after the Reset signal (reset_signal) is outputted for a preset period of time, the upper computer stops outputting the Reset signal (reset_signal), at this time, the fourth switching tube TG4 is switched to the off state, and the third switching tube TG3 is switched to the on state due to the second inverter F2.
The voltage division attenuating unit 160 supplies the reference voltage to the reference voltage unit 120 through the third connection terminal, and the reference voltage unit 120 supplies the reference voltage as a new reference voltage to the inverting input terminal of the comparator U1. The updated reference voltage can more accurately compare the waveforms of the VD platform voltage, and accurately acquire the starting signal so as not to receive the influence of resonance ripple waves.
In an alternative embodiment, when the upper computer 110 determines that the detection result (i.e. the primary side information) of the detection circuit is abnormal, a Reset Signal (reset_signal) may be output to Reset the detection circuit, so as to ensure that the rising edge Signal of the On Signal (On Signal) can be correctly compared.
With continued reference to fig. 3, in an alternative embodiment, the voltage sampling unit 130 includes a fifth resistor R5 and a sixth resistor R6.
The first terminal of the fifth resistor R5 is used as an input terminal of the voltage sampling unit 130 for connecting to the non-inverting terminal of the secondary winding of the transformer.
The second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6, and the second end of the sixth resistor R6 is grounded.
A sixth connection terminal is led out between the fifth resistor R5 and the sixth resistor R6, and is connected to the non-inverting input terminal of the comparator U1 and the first terminal of the asynchronous sample-and-hold unit 140 as an output terminal of the voltage sampling unit 130.
With continued reference to fig. 3, in an alternative embodiment, the voltage sampling unit 130 further includes a seventh resistor R7, one end of the seventh resistor R7 is connected to the sixth connection terminal, and the other end of the seventh resistor R7, as an output end of the voltage sampling unit 130, is connected to the non-inverting input end of the comparator U1 and the first end of the asynchronous sample hold unit 140.
With continued reference to fig. 3, in an alternative embodiment, the detection circuit further includes a third capacitor C3, one end of the third capacitor C3 is connected to the input end of the analog-to-digital conversion unit 150, and the other end of the third capacitor C3 is grounded.
The embodiment of the application also provides a detection chip, which comprises the primary side information detection circuit of the transformer.
The detection chip can be used as a PD controller of a secondary coil in a power supply network.
To sum up, the embodiment of the application provides a primary side information detection circuit and a detection chip of a transformer, including: the device comprises an upper computer, a reference voltage unit, a voltage sampling unit, a comparator, an asynchronous sample-hold unit and an analog-digital conversion unit; the upper computer is respectively connected with the control end of the reference voltage unit, the output end of the comparator and the output end of the analog-to-digital conversion unit; the input end of the voltage sampling unit is used for being connected with the same phase end of the secondary coil of the transformer, and the output end of the voltage sampling unit is connected with the same phase input end of the comparator and the first end of the asynchronous sampling and holding unit; the output end of the reference voltage unit is connected with the inverting input end of the comparator; the output end of the comparator is also connected with the second end of the asynchronous sample hold unit; the third end of the asynchronous sample hold unit is connected with the input end of the analog-to-digital conversion unit. The whole sampling operation process is completed completely by hardware self-adaption without software participation in the sampling process, the complexity of the system is reduced, an asynchronous sampling and holding unit adopts an asynchronous sampling and holding signal, higher sampling precision can be obtained, primary side information (comprising a primary side line voltage effective value, a primary side working frequency, and the on-time and off-time of the primary side in each working period) can be accurately obtained, and complete primary side information is provided for an upper computer of a secondary side, so that the system decision requirement of the upper computer is met.
The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the same, but rather, various modifications and variations may be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
It will be evident to those skilled in the art that the present application is not limited to the details of the foregoing illustrative embodiments, and that the present application may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.

Claims (7)

1. A primary side information detection circuit for a transformer, the detection circuit comprising: the device comprises an upper computer, a reference voltage unit, a voltage sampling unit, a comparator, an asynchronous sample-hold unit and an analog-digital conversion unit;
the upper computer is respectively connected with the control end of the reference voltage unit, the output end of the comparator and the output end of the analog-to-digital conversion unit;
the input end of the voltage sampling unit is used for being connected with the in-phase end of the secondary coil of the transformer, and the output end of the voltage sampling unit is connected with the in-phase input end of the comparator and the first end of the asynchronous sampling and holding unit;
the output end of the reference voltage unit is connected with the inverting input end of the comparator;
the output end of the comparator is also connected with the second end of the asynchronous sample hold unit;
the third end of the asynchronous sample hold unit is connected with the input end of the analog-to-digital conversion unit;
the upper computer is used for controlling the reference voltage unit to output reference voltage;
the voltage sampling unit is used for sampling the voltage of the same phase end of the secondary coil so as to obtain and output a first sampling voltage;
the comparator is used for outputting an opening signal when the first sampling voltage is larger than the reference voltage;
the upper computer is used for carrying out statistical analysis on the starting signal to obtain the working frequency of the primary side, the on-time and the off-time of the primary side in each working period;
the asynchronous sample hold unit is used for sampling the output voltage of the voltage sampling unit when the comparator outputs an opening signal to obtain a second sampling voltage, and keeping the second sampling voltage unchanged when the comparator stops outputting the opening signal;
the analog-to-digital conversion unit is used for performing digital-to-analog conversion on the second sampling voltage and transmitting the converted voltage value to the upper computer;
the upper computer is used for acquiring a primary line voltage effective value based on the voltage value;
the asynchronous sample-hold unit comprises a blanking module, a sampling module, a first inverter, a holding module, a first capacitor, a second capacitor, a first switching tube and a second switching tube;
the first end of the first switch tube is used as the first end of the asynchronous sample-hold unit and is connected with the output end of the voltage sampling unit, the second end of the first switch tube is connected with the first end of the second switch tube, one end of the first capacitor is grounded, the other end of the first capacitor is connected between the first switch tube and the second switch tube, the second end of the second switch tube is connected with one end of the second capacitor, the other end of the second capacitor is grounded, a first wiring terminal is led out between the second switch tube and the second capacitor and is used as the third end of the asynchronous sample-hold unit, and the third end of the asynchronous sample-hold unit is connected with the input end of the analog-to-digital conversion unit;
the input end of the blanking module is used as a second end of the asynchronous sample hold unit and is connected with the output end of the comparator;
the output end of the blanking module is connected with the input end of the sampling module, the first output end of the sampling module is connected with the input end of the first phase inverter, and the second output end of the sampling module is connected with the control end of the first switching tube;
the output end of the first inverter is connected with the input end of the holding module, and the output end of the holding module is connected with the control end of the second switching tube.
2. The transformer primary side information detection circuit of claim 1, wherein the detection circuit further comprises a voltage division attenuation unit comprising an operational amplifier;
the in-phase input end of the operational amplifier is connected with the third end of the asynchronous sample hold unit, the reverse input end of the operational amplifier is connected with the output end of the operational amplifier, a second wiring terminal is led out of the output end of the operational amplifier, and the second wiring terminal is connected with the input end of the analog-digital conversion unit.
3. The transformer primary side information detection circuit of claim 2, wherein the voltage division attenuating unit further comprises a first resistor and a second resistor;
one end of the first resistor is connected with the output end of the operational amplifier, the other end of the first resistor is connected with one end of the second resistor, and the other end of the second resistor is grounded;
a third wiring terminal is led out between the first resistor and the second resistor, and is connected to the reference voltage unit;
the reference voltage unit comprises a third resistor, a fourth resistor, a bias power supply, a second inverter, a third switching tube and a fourth switching tube;
the first end of the third resistor is connected to the primary side of the primary coil of the transformer, the other end of the third resistor is connected to one end of the fourth resistor, and the other end of the fourth resistor is grounded;
the input end of the bias power supply is connected between the third resistor and the fourth resistor, the output end of the bias power supply is connected with the first end of the fourth switching tube, the second end of the fourth switching tube is connected with the second end of the third switching tube, and the first end of the third switching tube is connected with the third wiring terminal;
a fourth connecting terminal is led out between the third switching tube and the fourth switching tube and is used as the output end of the reference voltage unit and is connected with the inverting input end of the comparator;
the control end of the third switching tube is connected with the output end of the second inverter, the control end of the fourth switching tube is connected with the input end of the second inverter, a fifth connecting terminal is led out between the input end of the second inverter and the control end of the fourth switching tube and is used as the control end of the reference voltage unit to be connected with the upper computer.
4. The transformer primary side information detection circuit of claim 1, wherein the voltage sampling unit comprises a fifth resistor and a sixth resistor;
the first end of the fifth resistor is used as an input end of the voltage sampling unit and is connected with the same-phase end of the secondary coil of the transformer;
the second end of the fifth resistor is connected with the first end of the sixth resistor, and the second end of the sixth resistor is grounded;
and a sixth wiring terminal is led out between the fifth resistor and the sixth resistor, and the sixth wiring terminal is connected with the non-inverting input end of the comparator and the first end of the asynchronous sample hold unit.
5. The primary side information detection circuit of claim 4, wherein the voltage sampling unit further comprises a seventh resistor, one end of the seventh resistor is connected to the sixth connection terminal, and the other end of the seventh resistor is connected to the non-inverting input terminal of the comparator and the first end of the asynchronous sample-and-hold unit.
6. The primary side information detection circuit of claim 1, further comprising a third capacitor, wherein one end of the third capacitor is connected to the input end of the analog-to-digital conversion unit, and the other end of the third capacitor is grounded.
7. A detection chip, comprising: the transformer primary side information detection circuit of any one of claims 1-6.
CN202311596378.8A 2023-11-28 2023-11-28 Primary side information detection circuit and detection chip of transformer Active CN117310262B (en)

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