CN117294549A - Half-duplex asynchronous serial communication receiving and transmitting control system - Google Patents
Half-duplex asynchronous serial communication receiving and transmitting control system Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
- H04L12/40013—Details regarding a bus controller
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L5/00—Arrangements affording multiple use of the transmission path
- H04L5/14—Two-way operation using the same type of signal, i.e. duplex
- H04L5/16—Half-duplex systems; Simplex/duplex switching; Transmission of break signals non-automatically inverting the direction of transmission
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Abstract
The invention discloses a half-duplex asynchronous serial communication receiving and transmitting control system, a communication processor; the programmable logic device comprises a resampling module, a resending module, a pulse sender, a register module and a counter; the resampling module and the register module are connected with the communication processor; the register module comprises a line control register, a DLL register and a DLM register; the asynchronous communication standard clock source is connected with the counter; the RS485 bus driver is connected with the retransmission module and the pulse transmitter; the system can provide a hardware automatic receiving and transmitting function for an RS485 interface realized by a general universal asynchronous communication controller; the RS485 bus realized by the system does not need to increase a pull-up resistor and a pull-down resistor, and can ensure that the bus has stronger driving capability. The automatic receiving and transmitting function channel has strong expandability, adopts digital synchronous logic control, and is accurate and reliable.
Description
Technical Field
The invention relates to the technical field of electronic information, in particular to a half-duplex asynchronous serial communication transceiving control system based on a CPLD.
Background
The asynchronous serial bus is typically implemented as an RS232, RS422 or RS485 level. And because RS485 only needs 3 signal lines to carry out differential transmission, has the characteristics of simple network wiring, low cost, strong anti-interference capability, long communication distance and high communication speed, and is widely applied.
RS485 is half duplex communication, and the bus node can only work in a certain state of receiving or transmitting, so that the transceiver driver needs to be controlled. The RS485 communication transceiving control mode is generally divided into 2 modes of software control and hardware automatic control.
The software control is to control the receiving and transmitting states of the RS485 bus driver through software, and a common method is to use a programmable GPIO to realize. Before the software transmits data, the GPIO is controlled to set the bus driver in a transmitting state, then the data transmission is started, and after the data transmission is completed, the bus driver is set in a receiving state. Software control may be accomplished in a serial driver or application.
The automatic control of the hardware is independent of the application software, and when the software starts to send data to the outside, the hardware circuit automatically generates a receiving and transmitting control signal to complete bus receiving and transmitting switching. The bus driver with automatic receiving and transmitting function and the additional control circuit are used, and the external bus pull-up and pull-down circuit is needed to assist in achieving the automatic receiving and transmitting function.
When a Universal Asynchronous Receiver Transmitter (UART) supports an RS485 function, the controller provides a transmission control signal for an RS485 bus driver, so that the UART can accurately ensure that the transmitter is opened only when transmitting data, and once the transmission is finished, the transmitter is immediately closed, and the communication node is switched to a receiving state.
Using a bus driver with automatic transmit/receive functionality, such as a MAX13487 chip, a state machine is designed inside the chip, which still requires bus pull-down circuit assistance, to control the transmitter according to the current bus state and TX signal conditions.
A control circuit is additionally arranged to invert the TX signal for receiving and transmitting control. When the TX signal is low, the transmitter is turned on, the bus is driven low, when the TX signal is high, the transmitter is turned off, the bus is not driven (high-impedance), and the bus state is restored to high by an external pull-up resistor. The control signal is generated by methods such as direct logic inversion of a TX signal, steady-state trigger delay, RC delay and the like.
When the software method is adopted for implementation, the program needs to read the UART to control the current state, the data is switched after being completely transmitted to the bus, the data is always in a waiting state during the data transmission period, the processor resource is occupied, and the system efficiency is reduced. In addition, if the software of the communication node runs abnormally when sending data, the bus is always abnormally driven, and the whole bus is invalid.
In the hardware automatic receiving and transmitting control method, except that the UART controller supports RS485, other methods all use TX signals to generate control signals, and only drive a bus when the data bit output is low, release the bus when the data bit output is high, and ensure the bus level by a pull-up circuit added on the bus, so that the bus driving capability is weaker, and the bus is limited in the long-distance and high-speed communication scene.
The method can increase the bus driving capability to a certain extent, but still can not fundamentally solve the problem of weakening of the driving capability, and the difference between the driving level and the pull-up level inevitably leads to the occurrence of steps of waveform change during the period of outputting the high level of the bus. Once the circuit is determined, the circuit is not easy to adjust, and has certain limitation in the occasion of changing the communication baud rate.
If the bus driving time is further extended to avoid the problem of the bus driving weakening, the bus driving time may exceed the length of 2 transmission data frames, and the node may not switch to the receiving state immediately after the data transmission is completed, which may cause a reception loss.
Disclosure of Invention
In view of the foregoing, the present invention provides a half-duplex asynchronous serial communication transceiving control system for overcoming or at least partially solving the foregoing problems.
The invention provides the following scheme:
a half-duplex asynchronous serial communication transceiving control system, comprising:
a communication processor;
the programmable logic device comprises a resampling module, a resending module, a pulse sender, a register module and a counter; the resampling module and the register module are connected with the communication processor; the register module comprises a line control register, a DLL register and a DLM register;
the asynchronous communication standard clock source is connected with the counter;
the RS485 bus driver is connected with the resending module and the pulse transmitter;
the communication processor is used for executing the following operations:
initializing a universal bus interface;
according to the baud rate of the programmable logic device, the calculation of the corresponding register parameters in the register module is completed by combining the frequency of the asynchronous communication standard clock source;
and writing the configuration values of the register parameters into corresponding registers of the register module.
Preferably: the communication processor comprises an asynchronous communication controller and a universal bus interface; the register module is connected with the asynchronous communication controller through the universal bus interface, so that the asynchronous communication controller writes the configuration value of each register parameter into a corresponding register of the register module through the universal bus interface.
Preferably: the register module is used for storing the communication format of the current asynchronous communication, and the communication format comprises the width information of the baud rate, the start bit, the data bit, the check bit and the stop bit.
Preferably: WLSB [1:0] in the line control register represents the data bit width, STB represents the width of the stop bit, and PEN represents whether a check bit exists or not; the DLL register and the DLM register are used for configuring the baud rate of the current asynchronous communication, and the written value corresponds to the clock frequency input into the asynchronous communication standard clock source.
Preferably: the universal bus interface comprises any one of an SPI interface, an I2C interface, a 1-Wire interface and a LocalBus interface.
Preferably: the resampling module is used for resampling the TXD signal by using the clock signal provided by the asynchronous communication standard clock source, the sampling clock is 16 times of the baud rate, and the data is sampled in the center of the data bit; when a high to low start bit change of the incoming TXD signal is detected, if the signal is still low at the sampling point, the start bit is asserted and a header indication signal is generated.
Preferably: and the retransmission module is used for starting the retransmission of the TXD signal after the valid start bit is determined, sampling the acquired signal at the center of the data bit, and outputting the signal again according to the baud rate by using the clock of the asynchronous communication standard clock source.
Preferably: the pulse transmitter is used for calculating the length of one frame of data according to the frame head indication signal and the content of the line control register, and using the counter to control the pulse width to generate a receiving and transmitting control pulse signal aligned with the edge of the retransmitted TX signal.
Preferably: the communication processor comprises any one of an embedded microprocessor or a single chip microcomputer.
Preferably: the frequencies of the asynchronous communication standard clock source comprise 1.8432MHz, 7.3728MHz and 14.7456 MHz.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the half-duplex asynchronous serial communication receiving and transmitting control system provided by the embodiment of the application can provide a hardware automatic receiving and transmitting function for an RS485 interface realized by a general universal asynchronous communication controller; the RS485 bus realized by the system does not need to increase a pull-up resistor and a pull-down resistor, and can ensure that the bus has stronger driving capability. The automatic receiving and transmitting function channel has strong expandability, adopts digital synchronous logic control, and is accurate and reliable.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments will be briefly described below. It is evident that the drawings in the following description are only some embodiments of the present invention and that other drawings may be obtained from these drawings by those of ordinary skill in the art without inventive effort.
Fig. 1 is a connection block diagram of a half-duplex asynchronous serial communication transceiving control system provided by an embodiment of the present invention;
FIG. 2 is a timing diagram of control pulse generation according to an embodiment of the present invention;
fig. 3 is a schematic diagram of an initialization process of a communication controller according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. It will be apparent that the described embodiments are only some, but not all, embodiments of the invention. All other embodiments, which are derived by a person skilled in the art based on the embodiments of the invention, fall within the scope of protection of the invention.
Referring to fig. 1, a half-duplex asynchronous serial communication transceiver control system provided in an embodiment of the present invention, as shown in fig. 1, may include:
a communication processor uC; in specific implementation, the communication processor uC includes any one of an embedded microprocessor or a single-chip microcomputer.
The programmable logic device CPLD comprises a resampling module (Resample), a retransmission module (RETransmit), a pulse transmitter pulseGen, a Register module (Ctrl Register) and a Counter; the resampling module and the register module are connected with the communication processor; the register module comprises a line control register, a DLL register and a DLM register; the resampling module is used for resampling the TXD signal by using the clock signal provided by the asynchronous communication standard clock source, the sampling clock is 16 times of the baud rate, and the data is sampled in the center of the data bit; when a high to low start bit change of the incoming TXD signal is detected, if the signal is still low at the sampling point, the start bit is asserted and a header indication signal is generated.
And the retransmission module is used for starting the retransmission of the TXD signal after the valid start bit is determined, sampling the acquired signal at the center of the data bit, and outputting the signal again according to the baud rate by using the clock of the asynchronous communication standard clock source.
The pulse transmitter is used for calculating the length of one frame of data according to the frame head indication signal and the content of the line control register, and using the counter to control the pulse width to generate a receiving and transmitting control pulse signal aligned with the edge of the retransmitted TX signal.
An asynchronous communication standard Clock source Clock, wherein the asynchronous communication standard Clock source is connected with the counter; specifically, the frequencies of the asynchronous communication standard clock source include 1.8432 megahertz (MHz), 7.3728 megahertz (MHz) and 14.7456 megahertz (MHz).
The RS485 bus driver MAX485, and the RS485 bus driver is connected with the resending module and the pulse transmitter;
the communication processor is used for executing the following operations:
initializing a universal bus interface;
according to the baud rate of the programmable logic device, the calculation of the corresponding register parameters in the register module is completed by combining the frequency of the asynchronous communication standard clock source;
and writing the configuration values of the register parameters into corresponding registers of the register module.
The half-duplex asynchronous serial communication receiving and transmitting control system provided by the embodiment of the application enables the half-duplex asynchronous bus to realize automatic switching of receiving and transmitting states under the condition that software is not interfered; under the condition that a Universal Asynchronous Receiver Transmitter (UART) does not have an RS485 control function, the accurate generation of a receiving and transmitting signal can be realized, and the conditions of weak bus driving capability and long driving time are avoided; the system realizes the automatic receiving and transmitting of RS485, and does not need to provide an extra pull-up resistor and a pull-down resistor for a bus; the programmable logic device (CPLD) logic digital method is used for realizing the circuit, the circuit works stably, the time sequence is accurate, the integration level is high, the instability of the RC delay circuit can be avoided, and the multichannel control can be realized easily. A configurable interface is provided that can accommodate various baud rate and frame format scenarios.
In order to better implement writing of register configuration, the embodiment of the application may provide that the communication processor includes an asynchronous communication controller and a universal bus interface; the register module is connected with the asynchronous communication controller through the universal bus interface, so that the asynchronous communication controller writes the configuration value of each register parameter into a corresponding register of the register module through the universal bus interface.
Further, the register module is used for storing the communication format of the current asynchronous communication, and the communication format comprises the width information of the baud rate, the start bit, the data bit, the check bit and the stop bit. WLSB [1:0] in the line control register represents the data bit width, STB represents the width of the stop bit, and PEN represents whether a check bit exists or not; the DLL register and the DLM register are used for configuring the baud rate of the current asynchronous communication, and the written value corresponds to the clock frequency input into the asynchronous communication standard clock source.
In order to provide rich interface styles, the embodiment of the application can also provide that the universal bus interface comprises any one of an SPI interface, an I2C interface, a 1-Wire interface and a LocalBus interface.
The following describes in detail a half-duplex asynchronous serial communication transceiver control system provided in an embodiment of the present application with reference to the accompanying drawings.
As shown in fig. 1, a system provided in an embodiment of the present application may include:
a. RS485 bus drivers with transmit-receive control, such as MAX485; the driving chip is not limited to the MAX485 chip, and may be any driving chip having the RS485 bus driving capability.
b. A programmable logic CPLD (programmable logic device) providing 3 GPIOs (general purpose input/output ports), 1 clock input and 1 universal bus interface pin resource; the programmable logic CPLD includes a resampling module ReSample, a resending module ReTransmit, a pulse transmitter PulseGen, a Register module Ctrl Register, and a Counter.
c. The standard Clock source Clock for asynchronous communication has the common frequency of 1.8432MHz, 7.3728MHz or 14.7456MHz;
d. the communication processor uC, such as an embedded microprocessor (SoC) or a singlechip, is provided with an asynchronous communication controller and a universal bus interface, and the bus interface can be an SPI interface, an I2C interface, a 1-Wire interface or a LocalBus interface and the like.
2. Control logic is implemented in the CPLD using a hardware description language.
The CPLD logic mainly realizes the functions of resampling TXD signals, frame header detection, TXD signal retransmission, control pulse generation, bus interface configuration, parameter register and the like.
A. And configuring a bus interface and a parameter register.
The part completes the configuration information interaction between the CPLD and the communication processor and mainly comprises a bus interface logic and a parameter register. The communication processor writes parameters into registers in the CPLD through the bus interface. The bus interface logic only needs to realize simple byte read-write function, and can ensure that parameters can be configured and checked. The register is mainly used for storing the communication format of the current asynchronous communication, and comprises width information of data bits, check bits and stop bits besides the baud rate.
Register definition references the 16550 standard serial port register format, 3 in total, corresponding to LCR, DLL, DLM registers.
TABLE 1 configuration registers
Wherein WLSB [1:0] in the Line Control Register (LCR) indicates the data bit width, STB indicates the width of the stop bit, and PEN indicates whether there is a check bit. The total number of bits of the data frame may be determined by the LCR controller.
The DLL register and DLM register are used to configure the baud rate of the current asynchronous communication, and the written value should correspond to the clock frequency Freq_cpld of the input CPLD. Divisor=Freq_cpld/(16. Times. Baud).
B. The TXD signal is resampled. (TXD signal means transmission data, RXD means reception data.)
The TXD signal is resampled using an externally supplied CPLD clock signal, with a sampling clock that is 16 times the baud rate and samples the data at the optimum point (center of the data bit) to eliminate cross-clock domain metastability effects. When detecting that the input TXD signal has a change from high to low start bit, if the signal is still low at the sampling point, the start bit is considered valid, and the method can be used for verifying the start bit to eliminate the interference caused by the signal in the transmission process.
C. The TXD signal is retransmitted.
The resampling process may detect the start bit of the data frame, thereby generating a frame header indication signal. At this time, retransmission of the TXD signal may be initiated, and the signal sampled at the optimum point may be output again at the baud rate using the clock of the CPLD.
D. Control pulse generation.
According to the contents of the LCR register, the accurate length of one frame of data can be calculated, and then the counter is used for controlling the width by taking the frame head indication signal as the starting point, so as to generate a receiving and transmitting control pulse signal aligned with the edge of the retransmitted TX signal. The control pulse generation timing is shown in fig. 2.
3. And performing software configuration preparation before communication.
When the communication processor needs to perform RS485 communication, the following operations need to be added in addition to completing the necessary initialization of the asynchronous communication controller (UART), as shown in fig. 3.
a. Initializing a universal bus interface;
b. according to the Baud rate of UART, combining the frequency of CPLD clock source to complete the corresponding LCR,
Calculating DLL and DLM parameters;
c. the configuration value LCR, DLL, DLM is written into the CPLD's corresponding register.
In a word, the half-duplex asynchronous serial communication receiving and transmitting control system can provide a hardware automatic receiving and transmitting function for an RS485 interface realized by a general universal asynchronous communication controller; the RS485 bus realized by the system does not need to increase a pull-up resistor and a pull-down resistor, and can ensure that the bus has stronger driving capability. The automatic receiving and transmitting function channel has strong expandability, adopts digital synchronous logic control, and is accurate and reliable.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
From the description of the embodiments above, it will be apparent to those skilled in the art that the present application may be implemented in software plus the necessary general hardware platform. Based on such understanding, the technical solutions of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product, which may be stored in a storage medium, such as a ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform the methods described in the embodiments or some parts of the embodiments of the present application.
In this specification, each embodiment is described in a progressive manner, and identical and similar parts of each embodiment are all referred to each other, and each embodiment mainly describes differences from other embodiments. In particular, for a system or system embodiment, since it is substantially similar to a method embodiment, the description is relatively simple, with reference to the description of the method embodiment being made in part. The systems and system embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention are included in the protection scope of the present invention.
Claims (10)
1. A half-duplex asynchronous serial communication transceiving control system, comprising:
a communication processor;
the programmable logic device comprises a resampling module, a resending module, a pulse sender, a register module and a counter; the resampling module and the register module are connected with the communication processor; the register module comprises a line control register, a DLL register and a DLM register;
the asynchronous communication standard clock source is connected with the counter;
the RS485 bus driver is connected with the resending module and the pulse transmitter;
the communication processor is used for executing the following operations:
initializing a universal bus interface;
according to the baud rate of the programmable logic device, the calculation of the corresponding register parameters in the register module is completed by combining the frequency of the asynchronous communication standard clock source;
and writing the configuration values of the register parameters into corresponding registers of the register module.
2. The half-duplex asynchronous serial communication transceiver control system of claim 1, wherein the communication processor comprises an asynchronous communication controller and a universal bus interface; the register module is connected with the asynchronous communication controller through the universal bus interface, so that the asynchronous communication controller writes the configuration value of each register parameter into a corresponding register of the register module through the universal bus interface.
3. The system of claim 2, wherein the register module is configured to store a communication format of the current asynchronous communication, the communication format including a baud rate, a start bit, a data bit, a check bit, and a stop bit.
4. A half duplex asynchronous serial communication transceiving control system according to claim 3, wherein WLSB [1:0] in said line control register indicates data bit width, STB indicates stop bit width, and PEN indicates whether there is a check bit; the DLL register and the DLM register are used for configuring the baud rate of the current asynchronous communication, and the written value corresponds to the clock frequency input into the asynchronous communication standard clock source.
5. The half-duplex asynchronous serial communication transceiver control system according to claim 2, wherein the universal bus interface comprises any one of an SPI interface, an I2C interface, a 1-Wire interface, and a LocalBus interface.
6. The half-duplex, asynchronous serial communication, transceiver control system of claim 1, wherein the resampling module is configured to resample the TXD signal using a clock signal provided by the asynchronous communication standard clock source, the sampling clock is 16 times the baud rate, and sample the data at the center of the data bit; when a high to low start bit change of the incoming TXD signal is detected, if the signal is still low at the sampling point, the start bit is asserted and a header indication signal is generated.
7. The half-duplex, asynchronous serial communication transmit-receive control system of claim 6 wherein the retransmission module is configured to initiate retransmission of the TXD signal after the start bit is asserted, the acquired signal is sampled at the center of the data bit and the signal is again output at the baud rate using the clock of the asynchronous communication standard clock source.
8. The half-duplex, asynchronous serial communication transmit/receive control system according to claim 6, wherein the pulse transmitter is configured to calculate a length of a frame of data based on the frame header indication signal and the line control register contents, and to use the counter to control the pulse width to generate a transmit/receive control pulse signal aligned with the edges of the retransmitted TX signal.
9. The half-duplex asynchronous serial communication transceiver control system of claim 1, wherein the communication processor comprises any one of an embedded microprocessor or a single chip microcomputer.
10. The half-duplex asynchronous serial communication transceiver control system of claim 1, wherein the frequency of the asynchronous communication standard clock source comprises 1.8432mhz, 7.3728mhz, 14.7456 mhz.
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