CN117294128A - Conductive power supply to ground clamp ESD circuit - Google Patents

Conductive power supply to ground clamp ESD circuit Download PDF

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Publication number
CN117294128A
CN117294128A CN202311246656.7A CN202311246656A CN117294128A CN 117294128 A CN117294128 A CN 117294128A CN 202311246656 A CN202311246656 A CN 202311246656A CN 117294128 A CN117294128 A CN 117294128A
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CN
China
Prior art keywords
delay
tube
circuit
power supply
ground
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Pending
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CN202311246656.7A
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Chinese (zh)
Inventor
乔仕超
牛义
武鹏
廖志凯
李永凯
沈堃
张靖
李向全
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Nanjing Mingxin Semiconductor Technology Co ltd
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Nanjing Mingxin Semiconductor Technology Co ltd
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Priority to CN202311246656.7A priority Critical patent/CN117294128A/en
Publication of CN117294128A publication Critical patent/CN117294128A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/28—Modifications for introducing a time delay before switching
    • H03K17/284—Modifications for introducing a time delay before switching in field effect transistor switches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02H—EMERGENCY PROTECTIVE CIRCUIT ARRANGEMENTS
    • H02H9/00—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection
    • H02H9/04—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage
    • H02H9/041—Emergency protective circuit arrangements for limiting excess current or voltage without disconnection responsive to excess voltage using a short-circuiting device
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
    • H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/0944—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors using MOSFET or insulated gate field-effect transistors, i.e. IGFET

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Physics & Mathematics (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A conductive power supply to ground clamp ESD circuit relates to electronic technology, in particular to integrated circuit technology. The invention comprises an ESD input end, a driving circuit and a switching tube, and is characterized by further comprising a delay circuit, wherein the ESD input end is connected with the input end of the driving circuit through the delay circuit. The invention solves the adverse effect caused by large current generated by the clamp structure from the conductive power supply to the ground when the chip is electrified quickly. By adopting the technology of the invention, the chip can simulate the discharge capacity of the chip in design and can be prevented from being damaged in power-on.

Description

Conductive power supply to ground clamp ESD circuit
Technical Field
The present invention relates to electronic technology, and more particularly to integrated circuit technology.
Background
ESD circuits are an important component in integrated circuits that directly determine the quality of the chip. It is possible to prevent the internal devices of the chip from being damaged when the respective ports of the chip are subjected to static electricity. However, in the past, SCR and GGMOS have been used as main discharge devices in integrated circuits. The turn-on voltage, the sustain voltage, and various discharge capability parameters of these devices when releasing ESD are TLP curves provided by the process plant, or measured parameters obtained through multiple flow sheets. More depends on experience of designers, and seriously affects success rate and design period of products. Some products also use diodes and cooperate with a clamp structure from a conductive power supply to ground as an ESD circuit, which can be simulated. In the circuit structure, when the power supply is positively charged to the ground, the switching tube is conducted, and a low-resistance discharging path is generated to discharge charges. When the power supply is negatively charged to ground, the diode parasitic by the drain and substrate of the switching tube is discharged forward to bleed the charge. However, the clamp structure from the conductive power supply to the ground has a disadvantage that when the chip is powered up quickly, the circuit itself can be mistaken for an ESD event, so that a large current path of an ampere level exists from the power supply to the ground, and the chip itself is burnt or a power supply chip for providing power for the system is burnt due to the fact that the power supply and the ground are both direct current voltages.
Fig. 1 shows a prior art circuit which is mainly divided into three modules, namely an RC delay circuit, a driving circuit and a switching tube module. Where M2 is an inverted tube with a particularly large channel length acting as a large resistor and M3 is a MOS capacitor. M5 and M6, M7 and M8 form a two-stage inverter, the size of which increases step by step, for driving M9. M9 is a PMOS switching transistor of very large size. The grid and the drain of M1 are short-circuited, and when VDD is electrified or an ESD event exists; in the initial stage, since M2 is off, M3 is a MOS capacitor. The N102 node is at a low level, and after passing through the two-stage inverter, N104 is also at a low level, and the driving capability becomes strong. When the power supply voltage is greater than the turn-on voltage of the PMOS transistor, M9 is turned on immediately, so that a current path is generated from VDD to GND. After the power supply voltage is higher than VGS1+VGS2, M2 is turned on. At this time, the voltage charges M3 through M2, and the N102 node increases continuously with time. When the voltage of the N102 node is higher than the threshold voltage of the inverter consisting of M5 and M6, the N104 node also becomes high, and M9 stops conducting. That is, the time required for VDD to change from VTHP to the N102 node voltage equal to the inverter threshold voltage consisting of M5 and M6 is the on time of M9. This time is entirely determined by the VDD rate of change. The power clamp structure shown in fig. 1 is simulated, and the simulation process mainly powers up VDD of a chip by one μs level to see whether M9 is turned on. As can be seen from fig. 2, M9 still has a region that is turned on for a short time when the chip is powered up on the order of μs. This can easily lead to burning out of the chip itself and possibly also the system power supply.
Disclosure of Invention
The invention aims to solve the technical problem of providing an ESD circuit which can solve the problem of large current generated when a chip is quickly electrified by a clamp structure from a conductive power supply to the ground.
The technical scheme adopted by the invention for solving the technical problems is that the conductive power supply to ground clamp ESD circuit comprises an ESD input end, a driving circuit and a switching tube, and is characterized by also comprising a delay circuit, wherein the ESD input end is connected with the input end of the driving circuit through the delay circuit.
Furthermore, the delay circuit comprises a delay inverter, a delay MOS tube group and a final stage MOS tube, wherein a high-level end is connected with the input end of the delay inverter through a first resistor R1, and the input end of the delay inverter is grounded through a first capacitor (C1); the output end of the delay inverter is grounded through a third resistor (R3) and is grounded through a second capacitor (C2);
the output end of the delay inverter is also connected with the control end of the delay MOS tube group,
the output end of the delay inverter is also connected with the control end of the last-stage MOS tube, and the drain end and the source end of the last-stage MOS tube are respectively connected with the output end of the driving circuit and the ground.
The delay inverter comprises a first PMOS tube (MP 1), a first NMOS tube (MN 1) and a sixth PMOS tube (MP 6); the grid electrodes of the first PMOS tube (MP 1) and the first NMOS tube (MN 1) are connected to the input end of the delay inverter, the drain electrode of the first PMOS tube (MP 1) and the drain electrode of the first NMOS tube (MN 1) are connected to the output end of the delay inverter, and the source electrode of the first NMOS tube (MN 1) is grounded;
the source electrode of the sixth PMOS tube (MP 6) is connected with the high level, and the drain electrode and the grid electrode are connected with the source electrode of the first PMOS tube (MP 1).
The delay MOS tube group comprises a second PMOS tube (MP 2) and a second NMOS tube (MN 2), the source electrode of the second PMOS tube (MP 2) is connected with a high level, the grid electrode is grounded through a second resistor R2, and the drain electrode is connected with the output end of the delay MOS tube group;
the source electrode of the second NMOS tube (MN 2) is grounded, the grid electrode is connected with the output end of the delay inverter, and the drain electrode is connected with the output end of the delay MOS tube group.
The final MOS tube is an NMOS tube, the grid electrode of the final MOS tube is connected with the output end of the delay MOS tube group, the drain electrode of the final MOS tube is connected with the output end of the driving circuit, and the source electrode of the final MOS tube is grounded.
The driving circuit includes two inverters connected in series.
The output end of the delay MOS tube group is connected with a high level through a third capacitor (C3).
In the driving circuit, a series connection point of the two inverters is grounded through a fourth capacitor (C4).
The invention solves the adverse effect caused by large current generated by the clamp structure from the conductive power supply to the ground when the chip is electrified quickly. By adopting the technology of the invention, the chip can simulate the discharge capacity of the chip in design and can be prevented from being damaged in power-on.
Drawings
Fig. 1 is a circuit diagram of a prior art power to ground clamp structure.
Fig. 2 is a schematic diagram of the transient simulation results of the prior art of fig. 1.
Fig. 3 is a circuit diagram of the present invention.
Fig. 4 is a graph of a 2KV phantom discharge waveform.
Fig. 5 is a simulated waveform diagram of each node of the present invention.
Fig. 6 is a waveform diagram of the E node of the circuit of the present invention at 500ns power up.
FIG. 7 is a waveform plot of the E node of the circuit of the present invention at 1 μs power up.
Fig. 8 is a graph of simulated waveforms for the circuit of the present invention under a 2KV HBM discharge model.
Fig. 9 is a circuit diagram of embodiment 2.
Fig. 10 is a simulated waveform diagram of example 2 under a 2KV HBM discharge model.
FIG. 11 is a waveform plot of node F at 1 μs power up for example 2.
Fig. 12 is a waveform plot of node F at 500ns power up for example 2.
Detailed Description
Example 1 see fig. 3.
The on-type power supply to ground clamp ESD circuit comprises an ESD input end, a driving circuit and a switching tube, and is characterized by further comprising a delay circuit, wherein the ESD input end is connected with the input end of the driving circuit through the delay circuit.
Furthermore, the delay circuit comprises a delay inverter, a delay MOS tube group and a final stage MOS tube, wherein a high-level end is connected with the input end of the delay inverter through a first resistor R1, and the input end of the delay inverter is grounded through a first capacitor (C1); the output end of the delay inverter is grounded through a third resistor (R3) and is grounded through a second capacitor (C2);
the output end of the delay inverter is also connected with the control end of the delay MOS tube group,
the output end of the delay inverter is also connected with the control end of the last-stage MOS tube, and the drain end and the source end of the last-stage MOS tube are respectively connected with the output end of the driving circuit and the ground.
The delay inverter comprises a first PMOS tube (MP 1), a first NMOS tube (MN 1) and a sixth PMOS tube (MP 6); the grid electrodes of the first PMOS tube (MP 1) and the first NMOS tube (MN 1) are connected to the input end of the delay inverter, the drain electrode of the first PMOS tube (MP 1) and the drain electrode of the first NMOS tube (MN 1) are connected to the output end of the delay inverter, and the source electrode of the first NMOS tube (MN 1) is grounded;
the source electrode of the sixth PMOS tube (MP 6) is connected with the high level, and the drain electrode and the grid electrode are connected with the source electrode of the first PMOS tube (MP 1).
The delay MOS tube group comprises a second PMOS tube (MP 2) and a second NMOS tube (MN 2), the source electrode of the second PMOS tube (MP 2) is connected with a high level, the grid electrode is grounded through a second resistor R2, and the drain electrode is connected with the output end of the delay MOS tube group;
the source electrode of the second NMOS tube (MN 2) is grounded, the grid electrode is connected with the output end of the delay inverter, and the drain electrode is connected with the output end of the delay MOS tube group.
The final MOS tube is an NMOS tube, the grid electrode of the final MOS tube is connected with the output end of the delay MOS tube group, the drain electrode of the final MOS tube is connected with the output end of the driving circuit, and the source electrode of the final MOS tube is grounded.
The driving circuit includes two inverters connected in series. The output end of the delay MOS tube group is connected with a high level through a third capacitor (C3). In the driving circuit, a series connection point of the two inverters is grounded through a fourth capacitor (C4).
For ease of understanding with reference to the drawings, the following references the device, for example, "MP2" for the second PMOS transistor MP2", and the other references are the same.
Referring to fig. 3, when the power supply is powered up at 500ns, the transient operation of the entire circuit is shown in fig. 5. MP5 in FIG. 3 is a switch tube, which is larger in size and is used for discharging charges. MP2 is a transistor with a larger channel length and acts as a resistor, and when the power supply voltage is larger than VTHP, MP2 is started to charge the C node. Focusing on node a in the figure, the ESD event on VCC remains low due to the presence of C1. Over time, the a node voltage is continuously charged up through resistor R1. When the VCC voltage is greater than 2VTHP, MP1 and MP6 are simultaneously turned on. Because node a charges slower, VTHN has not yet been reached. The node B is now charged by MP6 and MP1, due to the larger size of these two pipes. Node B is momentarily pulled to the supply voltage and MN2 and MN5 are simultaneously turned on. C2 is also charged to VCC, which, due to the presence of this capacitor, will maintain the B-point voltage at a high level for a period of time. MN5 pulls the E node momentarily low, at which point MP5 turns on. However, MN5 only plays an acceleration role, and actually plays a driving role as a two-stage inverter consisting of MN3 and MP3, MN4 and MP 4. When the voltage at point B increases, node C will be pulled down quickly because the aspect ratio of the MN2 tube is large. The phase of the E point and the phase of the C point are the same and are also in a low level, and MP5 is further kept on. That is, the MP5 rapidly discharges the charges between the VCC and GND points to play a role of ESD protection. As time goes by, point a rises continuously, and above VHN, point B is slowly pulled down due to the presence of C2, and MN2 and MN5 are turned off. MN2 loses the pull-down capability to point C, at which point MP2 slowly charges node C. After the voltage at point C is higher than the threshold of the inverter consisting of MP3 and MN3, the D node starts to discharge from high level through the MN3 tube, and it takes a certain time for the D node to drop due to the presence of C4. Until the voltage drops below the threshold of the inverter consisting of MP4 and MN4, the E node goes high, MP5 is turned off, and the discharge ends. The total discharge time is the MP2 to C3 charge time and MN3 tube to D point discharge time. This time must be greater than 100ns to drop the voltage at both ports to the proper voltage. After the discharge is finished, when the chip works normally, the node B is pulled to be at a low level due to the existence of R3, and MN2 and MN5 keep an off state. Node a is charged to VCC and MN1 is turned on, also pulling node B low. Node C is also charged to VCC, leaving MP5 in the off state. When the chip is powered up either fast or slow, MP5 will not be turned on. Whether MP5 is turned on is determined by the change speed of VCC completely, but the MP5 can be turned on only by setting a resistor and a capacitor to enable the whole circuit to change at the power supply voltage of less than 1 mu s. Neither fast (microsecond) nor slow (millisecond) power-up of the chip will turn on MP5. Therefore, the clamping structure for triggering the power supply to the ground by mistake can be well prevented in the power-on process of the chip. The simulation results are shown in fig. 6 and 7 by performing full burner simulation on the circuit. As can be seen from fig. 6, when VDD is powered up for 500ns, MP5 has a certain on time to drain the charge. 500ns is much longer than the voltage change time of the phantom, as is the time required to bleed off the charge. 500ns is also less than the fast power-up time (microsecond level) of the chip.
Referring to fig. 7, when VDD power-up time is 1 μs, the E node voltage always follows the power supply voltage variation, and MP5 is not turned on. Therefore, the clamping structure of the power supply to the ground can not be triggered by mistake when the chip is powered on quickly (microsecond level). The problem that when the chip is powered on quickly, the chip is burnt out due to the fact that a clamping structure from a power supply to the ground is triggered by mistake is solved well, or the system power supply is burnt out.
Referring to fig. 8, a full burner simulation waveform (positive discharge from VCC port to GND port in simulation) of the discharge charge in HBM model was simulated at 100pF discharge capacitance and 1.5kΩ discharge resistance at 2 KV. As can be seen from the figure, the maximum clamping voltage of VCC is 10V, which is a full protection for the internal circuit for the 5V process.
Example 2: see fig. 9.
Compared with embodiment 1, the switch tube of this embodiment is changed from the original PMOS tube to the NMOS tube. Because the driving tube is changed into an NMOS tube, a first-stage inverter is needed, and other circuits are unchanged. The simulation circuit is shown in fig. 10, 11 and 12. The achieved effect is consistent with that of the PMOS transistor, when the power-on time of the power supply voltage is more than 1 mu s, the simulation result is shown in figure 11, the grid voltage of the NMOS transistor is consistent and maintained at a low level, and the NMOS transistor cannot be triggered by mistake. That is to say, the NMOS tube will not be conducted when the chip is in normal use, and the chip will not be burnt out due to the large current path. For ESD event, the switch tube is turned on instantaneously to discharge charge.

Claims (8)

1. The on-type power supply to ground clamp ESD circuit comprises an ESD input end, a driving circuit and a switching tube, and is characterized by further comprising a delay circuit, wherein the ESD input end is connected with the input end of the driving circuit through the delay circuit.
2. The on-type power supply to ground clamp ESD circuit of claim 1 wherein said delay circuit comprises a delay inverter, a delay MOS stack and a final stage MOS transistor, the high level terminal being connected to the input of the delay inverter through a first resistor R1, the input of the delay inverter being further connected to ground through a first capacitor (C1); the output end of the delay inverter is grounded through a third resistor (R3) and is grounded through a second capacitor (C2);
the output end of the delay inverter is also connected with the control end of the delay MOS tube group,
the output end of the delay inverter is also connected with the control end of the last-stage MOS tube, and the drain end and the source end of the last-stage MOS tube are respectively connected with the output end of the driving circuit and the ground.
3. The on power to ground clamp ESD circuit of claim 2 wherein said delay inverter comprises a first PMOS transistor (MP 1), a first NMOS transistor (MN 1), and a sixth PMOS transistor (MP 6);
the grid electrodes of the first PMOS tube (MP 1) and the first NMOS tube (MN 1) are connected to the input end of the delay inverter, the drain electrode of the first PMOS tube (MP 1) and the drain electrode of the first NMOS tube (MN 1) are connected to the output end of the delay inverter, and the source electrode of the first NMOS tube (MN 1) is grounded;
the source electrode of the sixth PMOS tube (MP 6) is connected with the high level, and the drain electrode and the grid electrode are connected with the source electrode of the first PMOS tube (MP 1).
4. The on-type power supply to ground clamp ESD circuit of claim 2 wherein the delay MOS tube group comprises a second PMOS tube (MP 2) and a second NMOS tube (MN 2), the source of the second PMOS tube (MP 2) is connected to the high level, the gate is grounded through a second resistor R2, and the drain is connected to the output of the delay MOS tube group;
the source electrode of the second NMOS tube (MN 2) is grounded, the grid electrode is connected with the output end of the delay inverter, and the drain electrode is connected with the output end of the delay MOS tube group.
5. The on-type power supply to ground clamp ESD circuit of claim 2 wherein said last stage MOS transistor is an NMOS transistor having a gate connected to the output of the set of time-delay MOS transistors, a drain connected to the output of the drive circuit, and a source connected to ground.
6. The on power to ground clamp ESD circuit of claim 2 wherein the drive circuit comprises two inverters in series.
7. The on-state power supply to ground clamp ESD circuit of claim 2 wherein the output of the delay MOS bank is high through a third capacitor (C3).
8. The on power to ground clamp ESD circuit of claim 6 wherein in the drive circuit the series connection of the two inverters is grounded through a fourth capacitor (C4).
CN202311246656.7A 2023-09-25 2023-09-25 Conductive power supply to ground clamp ESD circuit Pending CN117294128A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311246656.7A CN117294128A (en) 2023-09-25 2023-09-25 Conductive power supply to ground clamp ESD circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311246656.7A CN117294128A (en) 2023-09-25 2023-09-25 Conductive power supply to ground clamp ESD circuit

Publications (1)

Publication Number Publication Date
CN117294128A true CN117294128A (en) 2023-12-26

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ID=89247520

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311246656.7A Pending CN117294128A (en) 2023-09-25 2023-09-25 Conductive power supply to ground clamp ESD circuit

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