CN117293116A - Semiconductor packaging structure capable of enhancing heat dissipation and production method - Google Patents
Semiconductor packaging structure capable of enhancing heat dissipation and production method Download PDFInfo
- Publication number
- CN117293116A CN117293116A CN202311516993.3A CN202311516993A CN117293116A CN 117293116 A CN117293116 A CN 117293116A CN 202311516993 A CN202311516993 A CN 202311516993A CN 117293116 A CN117293116 A CN 117293116A
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- China
- Prior art keywords
- chip
- lead frame
- base island
- chip base
- pcb
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 25
- 230000017525 heat dissipation Effects 0.000 title claims abstract description 22
- 230000002708 enhancing effect Effects 0.000 title claims abstract description 13
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 229920005989 resin Polymers 0.000 claims abstract description 36
- 239000011347 resin Substances 0.000 claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims description 12
- 239000002184 metal Substances 0.000 claims description 12
- 238000005520 cutting process Methods 0.000 claims description 6
- 238000009713 electroplating Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 claims description 5
- 238000003466 welding Methods 0.000 claims description 4
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 claims description 3
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- 239000012790 adhesive layer Substances 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 3
- 229910052737 gold Inorganic materials 0.000 claims description 3
- 239000010931 gold Substances 0.000 claims description 3
- 229910052741 iridium Inorganic materials 0.000 claims description 3
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 3
- 229910052709 silver Inorganic materials 0.000 claims description 3
- 239000004332 silver Substances 0.000 claims description 3
- 238000005538 encapsulation Methods 0.000 abstract description 5
- 238000010030 laminating Methods 0.000 abstract description 2
- JAYCNKDKIKZTAF-UHFFFAOYSA-N 1-chloro-2-(2-chlorophenyl)benzene Chemical compound ClC1=CC=CC=C1C1=CC=CC=C1Cl JAYCNKDKIKZTAF-UHFFFAOYSA-N 0.000 description 15
- 101100084627 Neurospora crassa (strain ATCC 24698 / 74-OR23-1A / CBS 708.71 / DSM 1257 / FGSC 987) pcb-4 gene Proteins 0.000 description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 11
- 229910052802 copper Inorganic materials 0.000 description 11
- 239000010949 copper Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 8
- 239000011295 pitch Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 6
- 239000004033 plastic Substances 0.000 description 4
- 230000005540 biological transmission Effects 0.000 description 2
- 230000001419 dependent effect Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000003292 glue Substances 0.000 description 2
- 238000000926 separation method Methods 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 239000012080 ambient air Substances 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
The invention discloses a semiconductor packaging structure for enhancing heat dissipation and a production method thereof, comprising the following steps: chip base island, chip, lead frame and resin encapsulation, the chip laminating is in the bottom surface of chip base island, the front of chip base island exposes from the resin encapsulation outside, lead frame welds on the PCB board, the chip base island contacts with the radiator from the resin encapsulation one side that exposes. In the semiconductor packaging structure provided by the invention, the side surface of the chip base island which is not contacted with the chip is exposed from the resin packaging part, so that the contact between the top surface of the chip base island and the radiator is facilitated, the heat generated during the operation of the chip is radiated directly through the chip base island and the radiator, the heat is effectively radiated into the external environment, and meanwhile, the bottom surface of the PCB is not limited by the radiator, therefore, components can be connected to the bottom surface of the PCB, the space of the two side surfaces of the PCB is fully utilized, and the miniaturization of the PCB is realized.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging structure capable of enhancing heat dissipation and a production method thereof.
Background
The heat dissipation path of the traditional power semiconductor on the PCB board is as follows: chip-bonding material-heat dissipation plate-PCB board-heat sink. Conventional lead frames (including bare drain pads) are soldered directly to copper-based surfaces on printed circuit boards. The copper-based surface provides electrical connection and thermal path from the chip to the PCB board. It is the only direct thermal connection to the printed circuit board because the rest of the device is encapsulated by the housing and can only release heat into the ambient air by convection.
In this method, the heat dissipation efficiency of the assembly is highly dependent on the characteristics of the PCB board, such as the size of the copper area, the weight and layout of the copper layer or copper. This is true whether the PCB board is connected to a heat sink or not. The low thermal conductivity of the printed circuit board limits heat dissipation and thus the maximum performance of the assembly. The bottom of the PCB needs to be connected with a radiator, and components and parts cannot be connected with the bottom of the PCB, so that the size of the PCB can be increased.
Meanwhile, the PCB is made of epoxy resin wrapped part of copper foil bonding pads, and the heat conductivity coefficient is as follows: the heat conductivity coefficient of the copper frame is 280W/mK about 15W/mK, and the heat conductivity of the copper frame and the copper frame are very different, so that the heat dissipation difficulty is relatively high.
Accordingly, the prior art has drawbacks and needs improvement.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a semiconductor packaging structure for enhancing heat dissipation and a production method thereof.
The technical scheme of the invention is as follows: provided is a semiconductor package structure for enhancing heat dissipation, including: the chip is attached to the bottom surface of the chip base island, the front surface of the chip base island is exposed out of the resin packaging side so as to be in contact with the radiator, and the lead frame is welded on the PCB.
Further, an insulating adhesive layer is arranged between the chip base island and the radiator.
Further, connecting rods are arranged on two sides of the chip base island, the resin package corresponds to the connecting rods to be concaved inwards to form a clearance groove, and the connecting rods are arranged in the clearance groove.
Further, the lead frame is exposed out of the resin package, and the lead frame is bent downwards to form a gull-wing structure, and the lead of the gull-wing structure is contacted with the bonding pad on the PCB.
Further, connecting ribs are arranged between the pin parts of the lead frame.
Further, the chip is electrically connected with the lead frame through metal wires.
Further, the length and width dimensions of the resin package are 3 x 3mm-12 x 12mm, and the step pitch of the lead frame is 0.5-5.5mm.
The invention also provides a production method of the semiconductor packaging structure for enhancing heat dissipation, which comprises the following steps:
step 1: placing a chip on the bottom surface of a chip base island of the lead frame and carrying out die bonding;
step 2: welding metal wires between the chip and the lead frame so as to electrically connect the chip and the lead frame;
step 3: packaging the chip base island and the chip, so that a part of one side surface of the chip base island, which is not contacted with the chip, is exposed out of the resin package;
step 4: electroplating the integral frame plate, and electroplating a tin layer on the outer side surface of the part of the lead frame and the chip base island, which is exposed out of the resin package;
step 5: and cutting ribs at the connection positions of the pins on the lead frame and the frame plate and between the pins and connecting rods.
Further, the metal wire is made of materials including: gold, silver, aluminum or iridium metal or alloy.
Further, one side of the chip base island, which is not contacted with the chip, is flush with the resin package.
By adopting the scheme, in the semiconductor packaging structure provided by the invention, one side surface of the chip base island, which is not contacted with the chip, is exposed from the resin packaging part, so that the top surface of the chip base island is conveniently contacted with the radiator, heat generated during the operation of the chip is radiated directly through the chip base island and the radiator, the heat is effectively radiated into the external environment, and meanwhile, the bottom surface of the PCB is not limited by the radiator, therefore, components can be connected to the bottom surface of the PCB, and the space on two side surfaces of the PCB is fully utilized, so that the miniaturization of the PCB is realized.
Drawings
FIG. 1 is a schematic cross-sectional view of the present invention.
Fig. 2 is a schematic structural view of the present invention.
Fig. 3 is a schematic structural diagram of the die bonding process.
Fig. 4 is a schematic structural diagram of a wire bonding process.
Fig. 5 is a schematic structural diagram of a resin encapsulation process.
Fig. 6 is a schematic structural diagram of a resin encapsulation process.
Fig. 7 is a schematic structural view of the electroplating process.
Fig. 8 is a schematic structural diagram of a rib cutting process.
Fig. 9 is a schematic structural diagram II of the rib cutting process.
Fig. 10 is a schematic diagram of different pin count.
Fig. 11 is a schematic diagram of a cut rib separation structure with different pin numbers.
Detailed Description
The invention will be described in detail below with reference to the drawings and the specific embodiments.
Referring to fig. 1 and 2, the present invention provides a semiconductor package structure for enhancing heat dissipation, comprising: chip base 1, with chip 2 that chip base 1 connects, with lead frame 11 that chip base 1 connects, and parcel part lead frame 11, chip base 1 and the resin package 3 of chip 2, chip 2 laminating is in the bottom surface of chip base 1, the front of chip base 1 is exposed from the resin package 3 outside to contact with radiator 5, lead frame 11 welds on PCB board 4.
The heat dissipation efficiency of conventional chip packages is highly dependent on the characteristics of the printed circuit board, such as the size of the copper area, the weight and layout of the copper layer or copper, and the low thermal conductivity of the printed circuit board limits the maximum heat dissipation performance. Moreover, the bottom of the printed circuit board needs to be contacted with the radiator, so that the bottom surface of the printed circuit board cannot be connected with components, and the whole area of the printed circuit board is difficult to reduce. In the semiconductor packaging structure provided by the invention, one side surface of the chip base island 1, which is not contacted with the chip 2, is exposed from the resin packaging 3, so that the contact between the top surface of the chip base island 1 and the radiator 5 is facilitated, heat generated during the operation of the chip 2 is directly radiated through the chip base island 1 and the radiator 5, the heat is effectively radiated into the external environment, and meanwhile, the bottom surface of the PCB 4 is not limited by the radiator 5, therefore, components can be connected to the bottom surface of the PCB 4, the space on two side surfaces of the PCB 4 is fully utilized, and the miniaturization of the PCB 4 is realized.
Because the heat dissipation path of the semiconductor package structure provided by the invention is upward, the radiator 5 is positioned above the resin package 3, and components such as a power device, a gate driver and other components can be placed in a release area at the bottom of the PCB 4, so that a smaller PCB 4 can be used. The top-cooled package provides better thermal response efficiency, lower temperature rise per watt of power consumption, and can operate at a higher power at a predetermined maximum temperature rise, thereby achieving higher current and performance capabilities than the same chip 2 of conventional package structure.
An insulating adhesive layer 51 is arranged between the chip base island 1 and the radiator 5, so that the circuit abnormality caused by the electric connection between the chip base island 1 and the radiator 5 is avoided, and the safety of the circuit is improved.
The two sides of the chip base island 1 are provided with connecting rods 12, the resin package 3 is inwards concave corresponding to the connecting rods 12 to form a clearance groove 31, and the connecting rods 12 are arranged in the clearance groove 31. The space avoidance grooves 31 are formed in the positions, corresponding to the connecting rods 12, on the two sides of the resin package 3, so that when the product is subjected to rib cutting and separation, the residual connecting rods 12 after cutting cannot exceed the maximum position of the resin package 3, and therefore, when the product is on a plate, the space between the products can be 0, and the minimization of the whole structure is achieved.
The lead frame 11 is exposed out of the resin package 3, and the pin part is bent downwards to form a gull-wing structure, and the pin of the gull-wing structure is contacted with the bonding pad on the PCB 4, so that the reliability of the welding of the upper plate of the product is improved, the situation that the pin is broken or is detached from the PCB 4 due to infirm welding is avoided, and the stability of the electrical connection between the pin and the PCB 4 is ensured.
And connecting ribs 111 are arranged between the pin parts of the lead frame 11 and are used for limiting the plastic package glue overflow. Referring to fig. 10 and 11, in the plastic packaging mold, since the connecting ribs 111 are present at the lead frames 11, no glue overflow preventing teeth can be made, so that the lead frames 11 with different pitches can share the same plastic packaging mold, and the lead frames 11 with different pin numbers can share the same plastic packaging mold due to the existence of the connecting ribs 111, so that the application breadth, development cost and development time of the product are improved.
The chip 2 is electrically connected with the lead frame 11 through the metal wire 21, so that the electric signal and current transmission requirements between the chip 2 and the lead frame 11 are ensured.
The length and width dimensions of the resin package 3 are 3 x 3mm-12 x 12mm, and the step pitch of the lead frame 11 is 0.5-5.5mm. In some embodiments, the length and width dimensions of the resin package 3 are 5.6x5.6mm, the step pitch of the lead frame 11 is 1.14mm, and the lead frame can be equivalently replaced by a T0252-3L type product, and can also be equivalently replaced by a PDFN-5X6-8L type product by a step pitch of 1.27.
In some embodiments, the lead frame 11 may refer TO a structure of a single/double island of a PDFN 5x6-8L and a TO252-3L/5L, kelvin, so that a package structure is implemented TO replace a plurality of products, thereby enhancing the application breadth of the products and improving the universality.
The invention also provides a production method of the semiconductor packaging structure for enhancing heat dissipation, which comprises the following steps:
step 1: referring to fig. 3, a chip 2 is placed on the bottom surface of a chip base 1 of a lead frame and die bonding is performed.
Step 2: referring to fig. 4, a metal wire 21 is soldered between the chip 2 and the lead frame 11, so as to electrically connect the chip 2 and the lead frame 11. The metal wires 21 are made of materials including: gold, silver, aluminum or iridium metal or alloy, and ensures the electric energy transmission effect.
Step 3: referring to fig. 5 and 6, the chip-based island 1 and the chip 2 are packaged such that a portion of a side surface of the chip-based island 1, which is not in contact with the chip 2, is exposed outside the resin package 3.
Step 4: referring to fig. 7, the entire frame plate is electroplated, and a tin layer is electroplated on the outer side of the lead frame 11 and the portion of the chip pad 1 where the resin package 3 is exposed.
Step 5: referring to fig. 8 and 9, the connection between the pins on the lead frame 11 and the frame plate, the connection bars 111 between the pins, and the connection bars 12 are cut and separated.
And one side surface of the chip base island 1, which is not contacted with the chip 2, is flush with the resin package 3, so that the heat dissipation effect is ensured, and the influence on the appearance caused by the fact that the chip base island 1 is higher than the resin package 3 is avoided.
In the semiconductor packaging structure provided by the invention, one side surface of the chip base island 1, which is not contacted with the chip 2, is exposed from the resin packaging 3, so that the contact between the top surface of the chip base island 1 and the radiator 5 is facilitated, heat generated during the operation of the chip 2 is directly radiated through the chip base island 1 and the radiator 5, the heat is effectively radiated into the external environment, and meanwhile, the bottom surface of the PCB 4 is not limited by the radiator 5, therefore, components can be connected to the bottom surface of the PCB 4, the space on two side surfaces of the PCB 4 is fully utilized, and the miniaturization of the PCB 4 is realized.
Because the heat dissipation path of the semiconductor package structure provided by the invention is upward, the heat sink 5 is positioned above the package structure, and components such as a grid driver and other components during power can be placed in a release area at the bottom of the PCB 4, so that a smaller PCB 4 can be used. The top-cooled package provides better thermal response efficiency, lower temperature rise per watt of power consumption, and can operate at a higher power at a predetermined maximum temperature rise, thereby achieving higher current and performance capabilities than the same chip 2 of conventional package structure.
The length and width dimensions of the semiconductor package structure provided by the invention are between 3mm and 12mm, and the step pitch of the lead frame 11 is between 0.5 and 5.5mm. In some embodiments, the length and width dimensions of the product are 5.6x5.6mm, the step pitch of the lead frame 11 is 1.14mm, and the product can be equivalently replaced by a TO252-3L product, and the product can be equivalently replaced by a PDFN-5X6-8L product by a step pitch of 1.27 mm. The lead frame 11 structure of the invention can replace a PDFN 5x6-8L single/double base island, TO252-3L/5L and Kelvin structure, thereby realizing that one packaging structure replaces a plurality of products, enhancing the application range of the products and improving the universality.
The foregoing description of the preferred embodiment of the invention is not intended to be limiting, but rather is intended to cover all modifications, equivalents, and alternatives falling within the spirit and principles of the invention.
Claims (10)
1. A semiconductor package structure for enhancing heat dissipation, comprising: the chip is attached to the bottom surface of the chip base island, the front surface of the chip base island is exposed out of the resin packaging side so as to be in contact with the radiator, and the lead frame is welded on the PCB.
2. The semiconductor package according to claim 1, wherein an insulating adhesive layer is provided between the chip-based island and the heat sink.
3. The semiconductor package structure according to claim 1, wherein the connecting rods are arranged on two sides of the chip base island, the resin package corresponds to the connecting rods to form a clearance groove in a concave manner, and the connecting rods are arranged in the clearance groove.
4. The semiconductor package according to claim 1, wherein the lead frame has a lead exposed outside the resin package and is bent downward to form a gull-wing structure, and the lead of the gull-wing structure is in contact with a pad on the PCB.
5. The semiconductor package according to claim 1, wherein the lead frame has a connecting rib between the lead portions.
6. The semiconductor package according to claim 1, wherein the chip and the lead frame are electrically connected by a metal wire.
7. The heat dissipation enhanced semiconductor package according to claim 1, wherein the resin package has a length-width dimension of 3 x 3mm to 12 x 12mm, and the lead frame has a pitch of 0.5 to 5.5mm.
8. The production method of the semiconductor packaging structure for enhancing heat dissipation is characterized by comprising the following steps:
step 1: placing a chip on the bottom surface of a chip base island of the lead frame and carrying out die bonding;
step 2: welding metal wires between the chip and the lead frame so as to electrically connect the chip and the lead frame;
step 3: packaging the chip base island and the chip, so that a part of one side surface of the chip base island, which is not contacted with the chip, is exposed out of the resin package;
step 4: electroplating the integral frame plate, and electroplating a tin layer on the outer side surface of the part of the lead frame and the chip base island, which is exposed out of the resin package;
step 5: and cutting ribs at the connection positions of the pins on the lead frame and the frame plate and between the pins and connecting rods.
9. The method of manufacturing a semiconductor package with enhanced heat dissipation according to claim 8, wherein the metal lines are made of a material comprising: gold, silver, aluminum or iridium metal or alloy.
10. The method of manufacturing a semiconductor package according to claim 8, wherein a side of the chip pad not contacting the chip is level with the resin package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311516993.3A CN117293116A (en) | 2023-11-15 | 2023-11-15 | Semiconductor packaging structure capable of enhancing heat dissipation and production method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311516993.3A CN117293116A (en) | 2023-11-15 | 2023-11-15 | Semiconductor packaging structure capable of enhancing heat dissipation and production method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117293116A true CN117293116A (en) | 2023-12-26 |
Family
ID=89248246
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311516993.3A Pending CN117293116A (en) | 2023-11-15 | 2023-11-15 | Semiconductor packaging structure capable of enhancing heat dissipation and production method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117293116A (en) |
-
2023
- 2023-11-15 CN CN202311516993.3A patent/CN117293116A/en active Pending
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