CN117290288B - IO grain and system-in-chip - Google Patents
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- CN117290288B CN117290288B CN202311584913.8A CN202311584913A CN117290288B CN 117290288 B CN117290288 B CN 117290288B CN 202311584913 A CN202311584913 A CN 202311584913A CN 117290288 B CN117290288 B CN 117290288B
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Classifications
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- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
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- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
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- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
- G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
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Abstract
The application provides an IO grain and system-in-chip, the IO grain is used for realizing the connection of system-in-chip and external equipment, includes: the UCIe interface IP set and the functional interface IP set which are interconnected with the UCIe interface IP set through an on-chip bus; the UCie interface IP set is matched with the functional interface IP set to realize the communication between the system-level chip and the external equipment; the types of each functional interface IP in the functional interface IP set are matched with the types of external equipment, the bandwidth of the UCie interface IP set is matched with the bandwidth of the functional interface IP set, the interface IP on the system-in-chip is decoupled through the IO crystal grains, the area occupation of the interface IP on the main crystal grain can be reduced, the scale of the system-in-chip is reduced, the yield of the large-scale chip is improved, meanwhile, the process decoupling of the main crystal grain and the IO crystal grain is realized, the advanced process utilization efficiency is improved, the interface IP cost and the whole research and development cost are reduced, and the research and development period of product iteration is shortened.
Description
Technical Field
The application relates to the technical field of semiconductors, in particular to an IO (input/output) crystal grain and a system-in-chip.
Background
With the continued development of artificial intelligence, autopilot, AIGC (Artificial Intelligence Generated Content, artificial intelligence generation content), etc., the computational effort and memory required for large-scale chips (e.g., AI chips) is increasing. However, the increase of the large-scale chip demand calculation force and the memory brings about a plurality of problems:
1. the area of single crystal grain (die) is increased, which results in reduced yield and waste of the area of the wafer edge;
2. in order to improve performance, the large-scale chip is continuously evolved to advanced technologies such as 5nm and 3nm, so that the cost is greatly increased, and meanwhile, the large-scale chip needs to integrate various interfaces IP (Intellectual Property core ) to expand performance and functions, so that the design complexity of the whole chip is improved, and larger expenditure is caused by IP purchase and integration in the prior technology.
3. Different application requirements lead to different specifications and performances of the same product, and chips with each specification need to be designed and manufactured, so that the research and development cost and the sheet-flowing cost are high, and the flexibility is low.
Disclosure of Invention
The application provides an IO grain and a system-in-chip, which are used for solving the problems of low yield, high cost and low flexibility of the existing large-scale chip.
The application provides an IO grain, IO grain is used for realizing the connection of system-in-chip and external equipment, includes:
the system comprises a UCIe interface IP set and a functional interface IP set which is interconnected with the UCIe interface IP set through an on-chip bus;
the UCie interface IP set is matched with the functional interface IP set to realize the communication between the system-level chip and the external equipment;
the types of the functional interface IPs in the functional interface IP set are matched with the types of the external equipment, and the bandwidth of the UCie interface IP set is matched with the bandwidth of the functional interface IP set.
According to the IO grain provided by the application, the UCie interface IP set comprises at least one group of UCie interface IPs, the function interface IP set comprises at least one function interface IP subset, the function interface IP subset comprises at least one group of target function interface IPs, and the target function interface IPs correspond to a target external device.
According to the IO grain provided by the application, for any subset of the function interfaces IP, the number of the target function interfaces IP is determined based on the number of the target external devices, the bandwidth of a single target external device and the bandwidth of a single group of target function interfaces IP; the number of UCIe interfaces IP in the UCIe interface IP set is determined based on the bandwidth of the functional interface IP set and the bandwidth of the single UCIe interface IP set.
According to the IO die provided by the application, the types of the target external device include: memory, high speed devices, and processors.
According to an IO die provided in the present application, the types of the target function interface IP include: a memory interface IP and a high-speed serial interface IP.
According to an IO die provided in the present application, the memory interface IP includes: DDR interface IP, LPDDR interface IP, and ONFI interface IP.
According to one of the IO dies provided in the present application, the high-speed serial interface IP includes: PCIe interface IP, serDes interface IP, and USB interface IP.
The present application also provides a system-on-chip comprising:
the main crystal grain and at least one IO crystal grain as described above, wherein the main crystal grain realizes communication with external equipment through each IO crystal grain;
the main crystal grains comprise a main UCIe interface IP set which is in communication connection with the UCIe interface IP set in each IO crystal grain, and the UCIe interfaces IP in the main UCIe interface IP set are in one-to-one correspondence with the UCIe interfaces IP in the UCIe interface IP set in each IO crystal grain.
According to the system-on-chip provided by the application, the UCie interface IP in the main UCie interface IP set is interconnected with the UCie interface IP in the UCie interface IP set in each IO grain through an organic substrate, a silicon intermediate layer, a rewiring layer or an embedded grain routing.
According to the system-on-chip provided by the application, the process nodes of the main crystal grain and the IO crystal grain are different.
The application provides an IO grain and system-in-chip, the IO grain is used for realizing the connection of system-in-chip and external equipment, includes: the system comprises a UCIe interface IP set and a functional interface IP set which is interconnected with the UCIe interface IP set through an on-chip bus; the UCie interface IP set is matched with the functional interface IP set to realize the communication between the system-level chip and the external equipment; the types of each functional interface IP in the functional interface IP set are matched with the types of external equipment, the bandwidth of the UCie interface IP set is matched with the bandwidth of the functional interface IP set, the interface IP on the system-in-chip is decoupled through the IO crystal grains, the area occupation of the interface IP to the main crystal grain can be reduced, the scale of the system-in-chip is reduced, the yield of the large-scale chip is improved, meanwhile, the process decoupling of the main crystal grain and the IO crystal grain is realized, the utilization efficiency of advanced processes is improved, the cost of the interface IP and the overall research and development cost are reduced, the research and development period of product iteration is shortened, and the flexibility of the product is improved.
Drawings
For a clearer description of the present application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description below are some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of the structure of an IO die provided herein;
FIG. 2 is a schematic diagram of the architecture of a system-on-chip provided herein;
FIG. 3 is a schematic diagram of an interconnection scheme between a SoC and an external device;
fig. 4 is a schematic diagram of an interconnection manner between an SoC and an external device provided in the present application;
FIG. 5 is a second schematic diagram of the interconnection between the SoC and the external device;
FIG. 6 is a second schematic diagram of an interconnection scheme between a SoC and an external device;
fig. 7 is a third schematic diagram of an interconnection manner between the SoC and the external device provided in the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the present application more apparent, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is apparent that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
Fig. 1 is a schematic structural diagram of an IO die provided in the present application, as shown in fig. 1, where the IO die is used to implement connection between a system-in-chip and an external device, and includes:
a uci (Universal Chiplet Interconnect Express, universal chiplet interconnect channel) interface IP set and a functional interface IP set interconnected with the uci interface IP set through an on-chip bus;
the UCie interface IP set is matched with the functional interface IP set to realize the communication between the system-level chip and the external equipment;
the types of the functional interface IPs in the functional interface IP set are matched with the types of the external equipment, and the bandwidth of the UCie interface IP set is matched with the bandwidth of the functional interface IP set.
Specifically, based on the foregoing, as the power and memory of the large-scale chip are increased, the area of a single die (die) is increased, which results in a reduced yield and a waste of the wafer edge area; in order to improve the performance, the large-scale chip is continuously evolved to advanced technologies such as 5nm and 3nm, the cost is greatly increased, and meanwhile, the large-scale chip needs to integrate various interfaces IP (Intellectual Property core ) to expand the performance and the functions, so that the design complexity of the whole chip is improved, and larger expenditure is caused by IP purchase and integration in the prior technology; in addition, different application requirements lead to different specifications and performances of the same product, and each specification of chip needs to be designed and manufactured, so that the research and development cost and the sheet-flowing cost are high, and the flexibility is low. The present application finds that the root cause of the above problem is that the existing AI SoC (System-on-a-Chip) is to integrate all functional interfaces IP on one SoC die to achieve connection with external devices. The design directly causes that the area of a single die can be continuously increased along with the increase of the demand calculation force and the memory of a large-scale chip, and meanwhile, all interfaces IP and SoC have to be kept in the same process, so that the problems of low yield, waste of the area of the wafer edge, improvement of the complexity of chip design, increase of the cost of IP purchase and integration in the prior process, high research and development cost and flow cost and low flexibility are caused. Furthermore, the above design method also leads to an increase in difficulty of product upgrade, because product upgrade means that the entire SoC die needs to be redesigned. Aiming at the problems, the embodiment of the application provides an IO grain through research, an interface IP conforming to the international standard UCie protocol (namely, UCie interface IP) is innovatively introduced, and the IO grain is combined with the functional interface IP of the AI SoC to prepare the IO grain, so that the functional interface IP of the AI SoC is decoupled from the SoC grain.
Further, the uci interface IP set includes at least one set of uci interface IPs, the function interface IP set includes at least one function interface IP subset, the function interface IP subset includes at least one set of target function interface IPs, and the target function interface IPs correspond to a target external device.
It is understood that any number of uci interfaces IP (together forming a uci interface IP set) and any number of functional interfaces IP (together forming a functional interface IP set) may be integrated in the IO die according to actual design needs. The uci interface IP set is interconnected with the functional interface IP set through an on-chip bus, where the on-chip bus may be any feasible on-chip bus in the prior art, such as an AMBA AXI (Advanced eXtensible Interface ) bus, which is not specifically limited in this embodiment of the present application. The functional interface IP set is interconnected with the external equipment, and the UCie interface IP set is interconnected with the system-level chip, so that the UCie interface IP set and the functional interface IP set can be matched to realize the communication between the system-level chip and the external equipment. In addition, since the types of the external devices are diverse, it is necessary to set a corresponding function interface IP (i.e., target function interface IP) for each external device (i.e., target external device), and thus each external device corresponds to one function interface IP subset. For any subset of functional interfaces IP, wherein the number of target functional interfaces IP is determined based on the number of target external devices, the bandwidth of a single target external device, and the bandwidth of a single set of target functional interfaces IP; the number of UCIe interfaces IP in the UCIe interface IP set is determined based on the bandwidth of the functional interface IP set and the bandwidth of the single UCIe interface IP set.
Based on the above, the type of each functional interface IP in the functional interface IP set can be ensured to be matched with the type of the external device, and meanwhile, the bandwidth of the UCie interface IP set is matched with the bandwidth of the functional interface IP set, so that the normal communication between the system-in-chip and the external device is ensured.
It is also understood that the types of the target external devices include, but are not limited to: memory and high-speed devices and processors, respectively, the types of target function interfaces IP include, but are not limited to: a memory interface IP and a high-speed serial interface IP. Meanwhile, according to actual design requirements, the memory interface IP includes, but is not limited to: DDR (Double Data Rate) interface IP, LPDDR (Low Power Double Data Rate ) interface IP, and ONFI interface (Open NAND Flash Interface ) IP, including but not limited to: PCIe (Peripheral Component Interconnect Express), peripheral component interconnect extensions) interface IP, serDes (Serializer/Deserializer), and USB (Universal Serial Bus ) interface IP. Based on the method, the design flexibility of the IO particles can be guaranteed to the greatest extent, and further the requirements of different application scenes can be flexibly adapted.
Fig. 2 is a schematic structural diagram of a system-on-chip provided in the present application, as shown in fig. 2, including:
a main die and at least one IO die as in the previous embodiments, the main die enabling communication with external devices through each IO die;
the main crystal grains comprise a main UCIe interface IP set which is in communication connection with the UCIe interface IP set in each IO crystal grain, and the UCIe interfaces IP in the main UCIe interface IP set are in one-to-one correspondence with the UCIe interfaces IP in the UCIe interface IP set in each IO crystal grain.
Specifically, on the basis of the IO die in the foregoing embodiment, the embodiment of the present application proposes a complete architecture of a system-on-chip. Unlike the prior art system-on-chip designs described above, the system-on-chip of the embodiments of the present application splits the raw chip into Main Die (i.e., the Main Die) and IO Die (i.e., the IO Die). The main crystal grains comprise a main UCIe interface IP set which is in communication connection with the UCIe interface IP set in each IO crystal grain, the UCIe interfaces IP in the main UCIe interface IP set are in one-to-one correspondence with the UCIe interfaces IP in the UCIe interface IP set in each IO crystal grain, and based on the main crystal grain, the main crystal grain can realize high-speed interconnection communication with external equipment through each IO crystal grain.
More specifically, the uci interface IP in the main uci interface IP set is interconnected with the uci interface IP in the uci interface IP set in each IO die through an organic substrate, a silicon interposer, a rewiring layer, or an embedded die trace. It is understood that the uci interface IP in the main uci interface IP set may also be interconnected with the uci interface IP in the uci interface IP set in each IO die through routing in any other feasible manner, which is not specifically limited in the embodiments of the present application. Based on the method, the function interface IP can be decoupled, the scale of the SoC is reduced, the overall yield is improved, the area occupation of the function interface IP to the Main die can be reduced, the key important logic can fully utilize the mean die area, and the advanced process utilization efficiency is improved. Meanwhile, the process decoupling of Main Die and IO Die is realized, in process selection, the IO Die can select other proper process nodes in consideration of cost, an IP supply chain and the like, namely, the process nodes of the Main Die and the IO Die can be different, and based on the process nodes, the cost of the functional interface IP can be further reduced. Furthermore, the improvement also enables the product upgrade or the design of products with different specifications to be more flexible, only the design of Main Die needs to be updated, the IO Die can only be increased or decreased according to the needs, and the design and the manufacture of the Main Die are kept unchanged, or the Main Die reserves enough UCIe interface IP at the initial stage of the design, only the need of deciding to be connected with the IO Die according to the needs at the later stage is avoided, and the Main Die does not need to be redesigned, so that the overall research and development cost can be reduced, and the product marketing time is shortened based on the design.
The structure and effects of the system-on-chip of the embodiment of the present application will be described below in conjunction with a comparative example. Fig. 3 is a schematic diagram of an interconnection manner between a conventional SoC and an external device, as shown in fig. 3, in the prior art, a 5nm SoC needs to be connected to 4 DRAMs (Dynamic Random Access Memory, dynamic random access memories), and every two sets of LPDDR5 interfaces IP are interconnected with one DRAM, so that 8 sets of 5nm LPDDR5 interfaces IP need to be integrated on a SoC die.
FIG. 4 is a drawing of the present applicationAs shown in fig. 4, the SoC in the embodiment of the present application splits the SoC into Main die and 4 IO die by using uci, each IO die includes a set of uci interfaces IP and 2 sets of LPDDR5 interfaces IP, and by using a 12nm technology, the Main die only needs to add 4 sets of uci interfaces IP, and maintains a 5nm technology, so that the use cost of the LPDDR5 interfaces IP can be saved. Meanwhile, if products with different specifications are required to be pushed out, the connection relation between the Main die and the IO die is only required to be adjusted according to the design of the Main die or under the condition that enough UCIe interfaces IP are reserved in the initial stage, and the parts of the IO die are used as interfaces without redesign and manufacture, so that the time for updating and iterating the products can be shortened, and the cost is reduced. From an area perspective, the size of a set of LPDDR5 interfaces IP is approximately 1.9mm 2 The occupied area of the SoC is 15mm 2 The size of a set of UCIe IPs is about 0.8mm 2 The area occupied by Main die is 3.2mm 2 This saves about 12mm for Main die 2 For other important logic, more efficiently utilizes the throughput utilization of advanced processes within a limited mask area.
Meanwhile, considering that the UCIe interface IP has the characteristic of flexibly supporting various bandwidths including 64/128/192/256/384/512Gpbs, the quantity of the UCIe interface IP and IO die can be flexibly adjusted according to design requirements in practical application. For the case shown in fig. 4, the bandwidth of one set of LPDDR5 is 120Gbps, and fig. 4 shows a case where one set of 256Gbps uci interfaces IP matches the bandwidth of two sets of LPDDR5 (240 Gbps). If the number of groups of uci interfaces IP and the number of IO die are considered to be reduced, a higher bandwidth uci interface IP may be selected, and fig. 5 is a second schematic diagram of an interconnection manner between the SoC and an external device provided in the present application, as shown in fig. 5, 1 group of uci interfaces IP with 512Gbps is adopted to match 4 groups of LPDDR5 (480 Gbps), so that Main die only needs to integrate 2 groups of uci interfaces IP, and peripheral only needs 2 IO die, based on which the area occupied by the uci interfaces IP can be further reduced, but the higher power consumption is brought by the higher bandwidth uci interfaces IP, so that flexible combination can be performed according to the required scene in the practical application process.
When the high-performance SoC needs to be connected with a large amount of memory, the DRAM needs to be placed around the SoC on physical realization and is as close to an interface IP at the edge of the SoC as possible, so that higher reliability and better performance are realized. Fig. 6 is a schematic diagram of a second interconnection manner between the conventional SoC and the external device, as shown in fig. 6, for the conventional SoC design manner, since the size and the side length of the DRAM die are about 12mm, and the long side length of the large SoC is about 30mm, when the number of DRAMs is up to ten or more, part of DRAM memory particles cannot be placed close to the interface IP, thereby affecting the reliability and performance of the chip. However, if the system-on-chip architecture of the embodiment of the present application is adopted, the problem can be solved, fig. 7 is a third schematic diagram of an interconnection manner between the SoC and the external device provided in the present application, and as shown in fig. 7, the UCIe interface IP is used to decouple the LPDDR5 interface IP to the IO die, and since the UCIe can support long-distance interconnection on the substrate up to 25mm, the placement of the IO die is more flexible, so that the short-distance reliable interconnection between the LPDDR5 interface IP on the IO die and the DRAM can be ensured.
The embodiment of the application provides an IO (input/output) die and a system-level chip, wherein the IO die is used for realizing connection between the system-level chip and external equipment, and comprises: the system comprises a UCIe interface IP set and a functional interface IP set which is interconnected with the UCIe interface IP set through an on-chip bus; the UCie interface IP set is matched with the functional interface IP set to realize the communication between the system-level chip and the external equipment; the types of each functional interface IP in the functional interface IP set are matched with the types of external equipment, the bandwidth of the UCie interface IP set is matched with the bandwidth of the functional interface IP set, the interface IP on the system-in-chip is decoupled through the IO crystal grains, the area occupation of the interface IP to the main crystal grain can be reduced, the scale of the system-in-chip is reduced, the yield of the large-scale chip is improved, meanwhile, the process decoupling of the main crystal grain and the IO crystal grain is realized, the utilization efficiency of advanced processes is improved, the cost of the interface IP and the overall research and development cost are reduced, the research and development period of product iteration is shortened, and the flexibility of the product is improved.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions.
Claims (8)
1. The IO grain is used for realizing the connection between a system-on-chip and external equipment, and comprises the following components:
the system comprises a UCIe interface IP set and a functional interface IP set which is interconnected with the UCIe interface IP set through an on-chip bus;
the UCie interface IP set is matched with the functional interface IP set to realize the communication between the system-level chip and the external equipment;
the types of the functional interface IPs in the functional interface IP set are matched with the types of the external equipment, and the bandwidth of the UCie interface IP set is matched with the bandwidth of the functional interface IP set;
the UCIe interface IP set comprises at least one group of UCIe interface IP, the function interface IP set comprises at least one function interface IP subset, the function interface IP subset comprises at least one group of target function interface IP, and the target function interface IP corresponds to one target external device;
for any subset of functional interfaces IP, wherein the number of target functional interfaces IP is determined based on the number of target external devices, the bandwidth of a single target external device, and the bandwidth of a single set of target functional interfaces IP; the number of UCIe interfaces IP in the UCIe interface IP set is determined based on the bandwidth of the functional interface IP set and the bandwidth of the single UCIe interface IP set.
2. The IO die of claim 1, wherein the type of the target external device comprises: memory, high speed devices, and processors.
3. The IO die of claim 2, wherein the type of target function interface IP comprises: a memory interface IP and a high-speed serial interface IP.
4. The IO die of claim 3 wherein the memory interface IP comprises: DDR interface IP, LPDDR interface IP, and ONFI interface IP.
5. The IO die of claim 4 wherein the high-speed serial interface IP comprises: PCIe interface IP, serDes interface IP, and USB interface IP.
6. A system-on-chip, comprising:
a main die and at least one IO die as claimed in claim 5, the main die enabling communication with external devices through each IO die;
the main crystal grains comprise a main UCIe interface IP set which is in communication connection with the UCIe interface IP set in each IO crystal grain, and the UCIe interfaces IP in the main UCIe interface IP set are in one-to-one correspondence with the UCIe interfaces IP in the UCIe interface IP set in each IO crystal grain.
7. The system-on-chip of claim 6, wherein the uci interface IP in the set of master uci interfaces IP is interconnected with the uci interface IP in the set of uci interfaces IP in each IO die through an organic substrate, silicon interposer, re-routing layer, or embedded die trace.
8. The system-on-chip of claim 7, wherein the process nodes of the primary die and the IO die are different.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311584913.8A CN117290288B (en) | 2023-11-24 | 2023-11-24 | IO grain and system-in-chip |
Applications Claiming Priority (1)
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