CN117290172A - High-speed bus verification board, system and method - Google Patents

Abstract

The invention provides a high-speed bus verification board, a system and a method, which belong to the technical field of communication and comprise the following steps: the base plate is integrated with different types of interface slots; different types of interface slots correspond to different types of auxiliary equipment; a first high-speed connector is arranged on the substrate; during testing, high-speed transmission signals of the equipment to be tested are sequentially transmitted to auxiliary equipment through the first high-speed connector and the interface slot; and/or, at least one high-speed connection chip and a second high-speed connector corresponding to each high-speed connection chip are arranged on the substrate; during testing, high-speed signals of the equipment to be tested are sequentially transmitted to the auxiliary equipment through the second high-speed connector, the high-speed connection chip and the interface slot. The high-speed bus verification board provided by the invention is applied to high-speed bus verification of the equipment to be tested, and can shorten the verification time of the equipment to be tested.

Description

High-speed bus verification board, system and method

Technical Field

The invention belongs to the technical field of communication, and particularly relates to a high-speed bus verification board, a system and a method.

Background

With the rapid development of the internet, the updating of the processor is also very rapid. The performance capabilities of each processor on the high-speed bus are also particularly important. At present, the verification work of the processor generally needs to develop a server or a PC machine which is adapted to the CPU, and the server or the PC machine is matched with different configurations to carry out system test. However, since the development cycle of the server or PC is long, the verification time of various configurations is different, and since the configuration support of the server or PC is limited due to the limitation of product requirements, the time and verification content of the test and verification operation of the processor high-speed bus are limited, and thus a flexible test system is needed to solve the above problems.

Disclosure of Invention

In view of the above, embodiments of the present application provide a high-speed bus validation board, system, and method to overcome or at least partially address the above.

In a first aspect of the embodiments of the present application, there is provided a high-speed bus verification board, including: the device comprises a substrate, wherein different types of interface slots are integrated on the substrate; wherein, the interface slots of different types correspond to the auxiliary devices of different types;

the substrate is provided with a first high-speed connector; each interface slot is correspondingly connected with at least one first high-speed connector, one end of each first high-speed connector is connected with the interface slot, the other end of each first high-speed connector is used for being connected with equipment to be tested, and when the equipment to be tested is tested, high-speed transmission signals of the equipment to be tested are sequentially transmitted to the auxiliary equipment through the first high-speed connectors, and the interface slots are used for transmitting the signals to be tested to the auxiliary equipment;

and/or, at least one high-speed connection chip and a second high-speed connector corresponding to each high-speed connection chip are arranged on the substrate; the input end of the high-speed connection chip is connected with a plurality of interface slots respectively, the output end of the high-speed connection chip is connected with one end of the second high-speed connector, and the other end of the second high-speed connector is used for being connected with the equipment to be tested, so that when the equipment to be tested is tested, high-speed signals of the equipment to be tested are sequentially transmitted to the auxiliary equipment through the second high-speed connector, the high-speed connection chip and the interface slots.

Optionally, an auxiliary signal module is further arranged on the substrate; the input end of the auxiliary signal module is used for being connected with the auxiliary signal generation module of the equipment to be tested, and the output end of the auxiliary signal module is respectively connected with the auxiliary signal pins of each interface slot;

the auxiliary signal module is used for acquiring auxiliary signals from the equipment to be tested so as to verify whether the auxiliary equipment functions normally.

Optionally, the auxiliary signal module includes: the device comprises an auxiliary signal connector, a power supply unit, a clock buffer, an I2C switch unit and a sideband signal unit;

one end of the auxiliary signal connector is used for connecting the equipment to be tested, and the other end of the auxiliary signal connector is respectively connected with one ends of the power supply unit, the clock buffer, the I2C switch unit and the sideband signal unit;

the other ends of the power supply unit, the clock buffer, the I2C switch unit and the sideband signal unit are respectively connected with corresponding auxiliary signal pins on each interface slot.

Optionally, the auxiliary signal module further comprises: the status indicator lamp is connected with the sideband signal unit;

the status indicator lamp is used for displaying the running status of the auxiliary equipment inserted into the interface slot.

Optionally, the interface slot includes: at least two types of OCP slots, PCIE slots, SFF 8639 slots, e3.S slots, e1.S slots, m.2 slots.

In a second aspect of the embodiment of the present application, a high-speed bus verification system is provided, including a high-speed bus verification board according to the first aspect of the embodiment of the present application, and a device to be tested connected to the high-speed bus verification board; the device to be tested comprises at least one processor, wherein at least one processor is respectively connected with a first high-speed connector on the high-speed bus verification board, or at least one processor is respectively connected with a second high-speed connector on the high-speed bus verification board.

Optionally, the device under test includes a processor, the processor having a plurality of interfaces; the interfaces are respectively connected with a first high-speed connector on the high-speed bus verification board, or respectively connected with a second high-speed connector on the high-speed bus verification board.

In a third aspect of the embodiments of the present application, a high-speed bus verification method is provided, which is applied to the high-speed bus verification system described in the second aspect of the embodiments of the present application, where the high-speed bus verification system includes: a high-speed bus verification board and a device to be tested connected with the high-speed bus verification board through a high-speed bus; the method comprises the following steps:

Step S1: inserting auxiliary equipment into a current interface slot on the high-speed bus verification board, and connecting current equipment to be tested with the current interface slot;

step S2: verifying whether the current equipment to be tested is normally connected with the auxiliary equipment or not;

step S3: under the condition that the auxiliary equipment is normally connected with the current equipment to be tested, acquiring high-speed bus resources of the current equipment to be tested;

step S4: based on the high-speed bus resource, verifying a high-speed bus on the current equipment to be tested;

after verifying the current device to be tested, inserting an auxiliary device into a target interface slot different from the current interface slot, switching the next device to be tested to be connected with the target interface slot, and executing the steps S2 to S4.

Optionally, before obtaining the high-speed bus resource of the current device under test under the condition that the auxiliary device is normally connected with the current device under test, the method further includes:

acquiring an in-place signal of the interface slot inserted by the auxiliary equipment;

and under the condition that the bit signal indicates that the auxiliary equipment is inserted correctly, a verification loop between the auxiliary equipment and the equipment to be tested is conducted.

Optionally, the verifying whether the current device under test and the auxiliary device are normally connected includes:

the auxiliary signal module acquires an auxiliary signal from the processor;

performing functional verification on the auxiliary equipment based on the auxiliary signal;

and under the condition that the function verification result passes, determining that the processor and the auxiliary equipment work normally.

The high-speed bus verification board provided by the embodiment of the application comprises: the base plate is integrated with different types of interface slots; different types of interface slots correspond to different types of auxiliary equipment;

a first high-speed connector is arranged on the substrate; each interface slot is correspondingly connected with at least one first high-speed connector, one end of each first high-speed connector is connected with the interface slot, and the other end of each first high-speed connector is connected with the equipment to be tested, so that high-speed transmission signals of the equipment to be tested are sequentially transmitted to auxiliary equipment through the first high-speed connectors and the interface slots during testing; and/or, at least one high-speed connection chip and a second high-speed connector corresponding to each high-speed connection chip are arranged on the substrate; the input end of the high-speed connection chip is connected with the interface slots respectively, the output end of the high-speed connection chip is connected with one end of the second high-speed connector, and the other end of the second high-speed connector is connected with the equipment to be tested, so that when the high-speed signal of the equipment to be tested is tested, the high-speed signal is transmitted to the auxiliary equipment through the second high-speed connector, the high-speed connection chip and the interface slots in sequence.

Through the high-speed bus verification board provided by the embodiment of the application, the high-speed bus verification board is applied to high-speed bus verification of equipment to be tested, and through integrating interface slots of different types on a substrate and matching with auxiliary equipment of different types, the high-speed bus verification board not only can be compatible with verification of equipment to be tested of different types, so that the verification of the equipment to be tested is more sufficient, but also can shorten the verification time of the equipment to be tested for high-speed bus verification in matching with various auxiliary equipment.

In addition, through the connected mode that every interface slot is connected with at least one first high-speed connector, when an interface slot corresponds to connect a plurality of equipment that awaits measuring, can realize the verification of a plurality of equipment that awaits measuring simultaneously, and can also pass through the connected mode that a second high-speed connector is connected through a high-speed connection chip and a plurality of interface slot, then when connecting the equipment that awaits measuring with the second high-speed connector, can save the quantity of second high-speed connector on the base plate, simplify the overall arrangement of base plate, when utilizing the equipment that awaits measuring of second high-speed connector connection to carry out the verification, can also select the auxiliary equipment on the interface slot that specifically corresponds through the high-speed connection chip voluntarily, insert the verification return circuit of equipment that awaits measuring, further shorten the verification time of high-speed bus.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments of the present application will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a high-speed bus verification board provided in an embodiment of the present application;

FIG. 2 is a schematic diagram of a first high-speed bus verification board structure provided in an embodiment of the present application;

FIG. 3 is a schematic diagram of a second high-speed bus verification board structure provided in an embodiment of the present application;

FIG. 4 is a schematic diagram of a third high-speed bus verification board structure provided in an embodiment of the present application;

FIG. 5 is a schematic diagram of a second high-speed bus validation board of FIG. 3 selecting a switch interface slot;

FIG. 6 is a schematic diagram of a first high-speed bus verification system according to an embodiment of the present application connected to a device under test;

FIG. 7 is a schematic diagram of a second high-speed bus verification system according to an embodiment of the present application connected to a device under test;

fig. 8 is a flowchart of steps of a high-speed bus verification method according to an embodiment of the present application.

Detailed Description

Exemplary embodiments of the present application will be described in more detail below with reference to the accompanying drawings in the embodiments of the present application. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

In the related technical scheme, the processor is fully verified at present, multiple servers and backplanes and the like matched with the device to be tested of the processor need to be developed, each server or the backplane supports one type of device, and the device to be tested of the processor needs to be matched with each server and the backplane to verify the supporting condition and performance of corresponding components. In general, the OCP, PCIE (Peripheral Component Interconnect Express slot, peripheral component interconnect express), SFF 8639 (Small Form Factor 8639slot, small size 8639), e3.s (Enterprise and Datacenter SSD Form Factor e3.s, solid state disk size standard e3.s for enterprises and data centers), e1.s (Enterprise and Datacenter SSD Form Factor e1.s, solid state disk size standard e1.s for enterprises and data centers), m.2 (Next Generation Form Factor m.2, next generation size standard m.2) and other interfaces are used to verify a variety of mainstream devices such as OCP, PCIE devices, u.2nvme (Non-Volatile Memory Express, nonvolatile memory expression) hard disks or SAS (Serial Attached SCSI )/SATA (Serial ATA) hard disks, E3.S, E1.S, NVME m.2 and SATA m.2 hard disks.

Because the verification work of each processor needs to design and develop multiple different kinds of Riser cards (expansion cards or lift cards) and back boards, the development period of the Riser cards and the back boards is long, and one type of device can be verified by one Riser or back board, so that the verification time of the processor matched with various types of devices is prolonged, and therefore the embodiment of the application provides a high-speed bus verification board, a high-speed bus verification system and a high-speed bus verification method, so that the problems are solved.

First, english present in FIGS. 2 to 6 will be explained:

different types of interface slots: OCP 4c+conn, PCIE X16 SLOT, e3.s 4C Conn, e1.s 4C Conn, SFF 8639Conn, M2 Conn.

High-speed connection chip: 4-Channel 3:1PCIe MUX.

First high-speed connector: HS ConnX4, SATAConn.

Second high-speed connector: HS ConnX4.

Auxiliary signal connector: auxiliary signal connector.

High speed bus: PCIEX4.

Auxiliary signal: CLK (Clock), I2C (Inter-Integrated Circuit, serial communication protocol), sidebandsignals (sideband signal, PERST, reset signal, WAKE, PRSNT, in-place signal), electrical signals (p12v_stby & p3v3_stby, standby voltage 12V and standby voltage 3.3V, P V & p3v3v & p3v3_stby, operating voltage 12V and operating voltage 3.3V and standby voltage 3.3V, P V & p3v3_stby, operating voltage 12V and standby voltage 3.3V, P V & p5v & p3v3_stby, operating voltage 12V and operating voltage 5V and standby voltage 3.3V, P3V & P1V8& p3v3_stby, operating voltage 3.3V and operating voltage 1.8V and standby voltage 3.3V).

And the device to be tested: MB.

A substrate: baseboard.

A processor: CPU, CPU0, CPU1, CPU2, CPU3.

Processor interface: PE0, PE1, PE2, PE3.

A power supply unit: efuse n.

Clock buffer: CLK Buffer.

I2C switching unit: I2C SWITCH.

Sideband signal unit: CPLD. The embodiment of the application firstly provides a high-speed bus verification board, which comprises the following components: the device comprises a substrate, wherein different types of interface slots are integrated on the substrate; wherein, the interface slots of different types correspond to the auxiliary devices of different types; the substrate is provided with a first high-speed connector; each interface slot is correspondingly connected with at least one first high-speed connector, one end of each first high-speed connector is connected with the interface slot, the other end of each first high-speed connector is used for being connected with equipment to be tested, and when the equipment to be tested is tested, high-speed transmission signals of the equipment to be tested are sequentially transmitted to the auxiliary equipment through the first high-speed connectors, and the interface slots are used for transmitting the signals to be tested to the auxiliary equipment; and/or, at least one high-speed connection chip and a second high-speed connector corresponding to each high-speed connection chip are arranged on the substrate; the input end of the high-speed connection chip is connected with a plurality of interface slots respectively, the output end of the high-speed connection chip is connected with one end of the second high-speed connector, and the other end of the second high-speed connector is used for being connected with the equipment to be tested, so that when the equipment to be tested is tested, high-speed signals of the equipment to be tested are sequentially transmitted to the auxiliary equipment through the second high-speed connector, the high-speed connection chip and the interface slots.

In this embodiment, referring to fig. 1, fig. 1 is a schematic diagram of a high-speed bus verification board provided in an embodiment of the present application, where the schematic diagram includes: the device comprises a substrate, different types of interface slots (interface slots 1-n), a first high-speed connector, a high-speed connection chip and a second high-speed connector, wherein different types of auxiliary devices (auxiliary devices 1-n) are integrated on the substrate, the different types of interface slots are generally interfaces such as OCP, PCIE slots, SFF 8639, E3.S, E1.S and M.2, and the different types of interface slots correspond to the different types of auxiliary devices, so after the interface slots are inserted into the corresponding auxiliary devices, development and verification of devices to be tested can be carried out by matching with various main devices, wherein the auxiliary devices refer to various main devices such as OCP, PCIe devices, U.2NVME hard disks or SAS/SATA hard disks, E3.S, E1.S, NVME M.2 and SATA M.2 hard disks, or CEM devices (PCIE devices).

The device to be tested can be a processor reference board, a server or a PC device to be tested, and also can comprise an SAS card, a RAID card and a Tri-mode card on the PC device to be tested. The Tri-mode card generally has the functions of hardware acceleration, high-performance cache and RAID (disk array), and can provide data protection, fault tolerance and optimized read-write performance.

The first high-speed connector refers to a high-speed connector directly connected to an interface slot on a substrate, and the first high-speed connector may be a high-speed connector corresponding to MCIO (Multi-Chip Module Carrier Input/Output), CDFP (Compact Form-factor plug and play), SATA, PCIe, or the like.

The second high-speed connector refers to a high-speed connector which can be connected with the interface slot through the high-speed connection chip, and the second high-speed connector can be the first high-speed connector which meets the requirement of being connected with the high-speed connection chip.

The first high-speed connector and the second high-speed connector can be connected with the equipment to be tested through the high-speed bus, and then the verification loop between the first high-speed connector and the auxiliary equipment is conducted to verify the equipment to be tested.

Referring to fig. 2, fig. 2 is a schematic diagram of a first high-speed bus verification board structure provided in this embodiment, fig. 2 is a high-speed bus verification board with only first high-speed connectors, HS Conn X4 and SATA Conn in fig. 2 are first high-speed connectors, OCP 4c+conn, PCIE X16 SLOT, e3 s4C Conn, e1 s4C Conn, SFF 8639Conn, M2 Conn are different types of interface SLOTs, since each interface SLOT is correspondingly connected with at least one first high-speed connector, it can be seen from fig. 2 that OCP 4c+conn, PCIE X16 SLOT, e3 s4C Conn, e1 s4C Conn are respectively connected with four first high-speed connectors, e1 s4C Conn are respectively connected with one high-speed connector, SFF 8639Conn and M2 Conn are respectively connected with two first high-speed connectors, and the number of channels of each interface SLOT is determined according to the number of first high-speed connectors, and the number of channels of each interface SLOT is not limited. The other end of the first high-speed connector is connected with equipment to be tested, the interface slot is used for inserting corresponding auxiliary equipment, and when in test, high-speed transmission signals of the equipment to be tested are sequentially transmitted to the auxiliary equipment through the first high-speed connector, so that one first high-speed connector can only serve one interface slot, but as one interface slot can be connected with a plurality of first high-speed connectors, the plurality of first high-speed connectors can be respectively connected with one equipment to be tested, and then the plurality of equipment to be tested can be verified simultaneously.

Referring to fig. 3, fig. 3 is a schematic diagram of a second high-speed bus verification board structure provided in the embodiment of the present application, fig. 3 is a high-speed bus verification board with only a second high-speed connector, fig. 3 is a high-speed bus verification board with HS Conn X4 as the second high-speed connector, 4-Channel 3:1PCIE MUX as the high-speed connection chip, OCP 4c+conn, PCIE X16 SLOT, e3.s 4C Conn, e1.s 4C Conn, SFF 8639Conn, M2 Conn are different types of interface SLOTs, one second high-speed connector is connected through one high-speed connection chip, and since one high-speed connection chip can be connected with a plurality of interface SLOTs, it can be seen from fig. 4 that OCP 4c+conn, PCIE X16 SLOT, e3.s 4C Conn are connected through 4 high-speed connection chips, e1.s 4C Conn, SFF 39Conn, M2 Conn are connected through one high-speed connection chip. During testing, high-speed signals of the device to be tested are sequentially transmitted to the auxiliary device through the second high-speed connector, the high-speed connection chip and the interface SLOTs, when the substrate is used for testing, only one interface SLOT is accessed into the verification loop at a time, if OCP 4C+Conn is inserted, PCIEX 16 SLOT and E3.S 4C Conn do not work, at the moment, 4-Channel 3:1PCIe MUX can select the auxiliary device inserted into the OCP 4C+Conn to access the substrate, and because one second high-speed connector is shared by a plurality of interface SLOTs, compared with the first high-speed bus verification board. The space of the substrate can be saved, wiring of each device on the substrate is facilitated, the rule size of the high-speed connection chip is smaller than that of the second high-speed connector, and the layout space of the substrate can be further saved.

Referring to fig. 4, fig. 4 is a schematic diagram of a third high-speed bus verification board structure provided in the embodiment of the present application, fig. 4 is a high-speed bus verification board with a first high-speed connector and a second high-speed connector, fig. 4 is a high-speed bus verification board with SATA Conn as the first high-speed connector, HS Conn X4 as the second high-speed connector, 4-Channel 3:1pcie MUX as the high-speed connection chip, OCP 4c+conn, PCIE X16SLOT, e3.s 4C Conn, e1.s 4C Conn, SFF 8639Conn, M2 Conn are different types of interface SLOTs, one second high-speed connector is connected to one high-speed connection chip through one high-speed connection chip, and since one high-speed connection chip can be connected to a plurality of interface SLOTs, from fig. 4, OCP 4c+conn, PCIE X16SLOT, e3.s 4C Conn are connected to four second high-speed connectors through 4 high-speed connection chips, e1.s 4C Conn, e 4C, SFF 8639Conn are simultaneously connected to one high-speed connection chip through one high-speed connection chip and SFF 8639, M2 Conn are connected to one high-speed connector through one high-speed connection chip. During testing, high-speed signals of the device to be tested are sequentially transmitted to the auxiliary device through the second high-speed connector, the high-speed connection chip and the interface SLOTs, when the substrate is used for testing, only one interface SLOT is accessed into the verification loop at a time, if OCP 4C+Conn is inserted, PCIEX 16SLOT and E3.S 4C Conn do not work, at the moment, 4-Channel 3:1PCIe MUX can select the auxiliary device inserted into OCP 4C+Conn to access the substrate, and because one second high-speed connector is shared by a plurality of interface SLOTs, compared with the first high-speed bus verification board and the second high-speed bus verification board. Besides the shared second high-speed connector, the first high-speed connector is also arranged, and on the basis of saving layout space, certain specific high-speed connector models are placed, so that different types of high-speed bus verification can be further met.

Through the high-speed bus verification board provided by the embodiment of the application, the high-speed bus verification board is applied to high-speed bus verification of equipment to be tested, and through integrating interface slots of different types on a substrate and matching with auxiliary equipment of different types, the high-speed bus verification board not only can be compatible with verification of equipment to be tested of different types, so that the verification of the equipment to be tested is more sufficient, but also can shorten the verification time of the equipment to be tested for high-speed bus verification in matching with various auxiliary equipment.

In addition, through the connection mode that each interface slot is connected with at least one first high-speed connector, when an interface slot is correspondingly connected with a plurality of devices to be tested, verification of the devices to be tested can be simultaneously achieved, and verification loops of the devices to be tested can be accessed through the connection mode that one second high-speed connector is connected with the plurality of interface slots through one high-speed connection chip, then when the second high-speed connector is connected with the devices to be tested, the number of the second high-speed connectors on a substrate can be saved, the layout of each device on the substrate is simplified, when the second high-speed connector is used for connecting the devices to be tested for verification, auxiliary devices on the interface slots which are specifically corresponding to the interface slots can be automatically selected through the high-speed connection chip, and verification time of a high-speed bus is further shortened.

In one embodiment, the substrate is further provided with an auxiliary signal module; the input end of the auxiliary signal module is used for being connected with the auxiliary signal generation module of the equipment to be tested, and the output end of the auxiliary signal module is respectively connected with the auxiliary signal pins of each interface slot; the auxiliary signal module is used for acquiring auxiliary signals from the equipment to be tested so as to verify whether the auxiliary equipment functions normally.

In this embodiment, referring to fig. 1, an auxiliary signal module is further provided on the substrate, where an input end of the auxiliary signal module is connected to an auxiliary signal generating module of the device to be tested, an output end of the auxiliary signal module is connected to an auxiliary signal pin of each interface slot, a plurality of auxiliary signal pins exist on each interface slot, one auxiliary signal pin corresponds to one auxiliary signal, the auxiliary signal module has a plurality of output ends, each output end corresponds to one auxiliary signal pin, an input end and an output end of the auxiliary signal module are connected to an auxiliary signal generating device of the device to be tested, and specifically, connection can be established between the auxiliary signal module and the auxiliary signal generating device through an auxiliary signal cable by connecting a high-speed connector of the device to be tested.

The auxiliary signal generating module is arranged in the equipment to be tested, and can provide auxiliary signals, such as I2C signals, clock signals, electric signals, sideband signals and the like, for the auxiliary signal module so as to verify whether the auxiliary equipment functions normally or not.

In addition, the auxiliary signal generating module can also be an external signal generator, and the auxiliary signal generating module is not required to be arranged in the equipment to be tested, so long as the auxiliary signal generating module can provide auxiliary signals for the auxiliary signal module, and the function of verifying the equipment to be tested is normal.

In one embodiment, the auxiliary signal module comprises: the device comprises an auxiliary signal connector, a power supply unit, a clock buffer, an I2C switch unit and a sideband signal unit; one end of the auxiliary signal connector is connected with the equipment to be tested, and the other end of the auxiliary signal connector is respectively connected with one ends of the power supply unit, the clock buffer, the I2C switch unit and the sideband signal unit; the other ends of the power supply unit, the clock buffer, the I2C switch unit and the sideband signal unit are respectively connected with corresponding auxiliary signal pins on each interface slot.

In this embodiment, referring to fig. 1, the auxiliary signal module of fig. 1 is described, where the auxiliary signal module of fig. 1 includes an auxiliary signal connector, a power supply unit, a clock Buffer, an I2C SWITCH unit, and a sideband signal unit, corresponding to fig. 2 and fig. 4, the auxiliary signal connector is Auxiliary signal connector, the power supply unit is efuse×n, the clock Buffer is CLK Buffer, the I2C SWITCH unit is I2C SWITCH, and the sideband signal unit is CPLD, and as can be seen from fig. 2 and fig. 4, the auxiliary signal connector is connected to one end of the power supply unit, the clock Buffer, the I2C SWITCH unit, and the sideband signal unit, respectively; the other ends of the power supply unit, the clock buffer, the I2C switch unit and the sideband signal unit are respectively connected with corresponding auxiliary signal pins on each interface slot, and the other ends of the auxiliary signals are connected with equipment to be tested.

The auxiliary signal connector is only a connecting device for receiving auxiliary signals, and the power supply unit is used for outputting electric signals with different voltages to each interface slot and supplying power to devices such as an IC (integrated circuit) on a substrate, interfaces such as a PCIe (peripheral component interconnect express) slot and the like; the clock buffer is used for outputting multiple clock signals to each interface slot, and is connected to the interfaces such as the OCP and PCIe slots on the substrate to serve as clock input for various high-speed components; the I2C switch unit is used for acquiring the component information of the auxiliary equipment inserted into each interface slot; the sideband signal unit is used for outputting sideband signals to each interface slot, and assisting normal communication between the device to be tested and the high-speed component on the substrate, wherein the sideband signals comprise: a PERST reset signal, a WAKE signal, a PRSNT bit signal, etc.

In one embodiment, the auxiliary signal module further comprises: the status indicator lamp is connected with the sideband signal unit; the status indicator lamp is used for displaying the running status of the auxiliary equipment inserted into the interface slot.

In this embodiment, referring to the setting of the status indicator lights in fig. 2 and 4, the auxiliary signal module further includes status indicator lights, where the status indicator lights are connected to the sideband signal unit, and the status indicator lights are used to show the operation status of the auxiliary device inserted into the interface slot, for example, only one status indicator light, and when the auxiliary device is correctly inserted into the interface slot, the status indicator lights display a green light to indicate that the auxiliary device is ready, and when the device to be tested interacts with the auxiliary device, the status indicator lights flash to indicate that the auxiliary device is in operation. In addition, a plurality of state signal indicating lamps can be arranged, and each signal lamp can be provided with different colors to replace different states of auxiliary equipment.

In addition, a selection pin can be arranged on the high-speed connection chip and connected with the sideband signal unit; the selection pin is used for conducting a verification loop between the auxiliary equipment and the equipment to be tested, wherein the auxiliary equipment and the equipment to be tested are correctly inserted into the interface slot.

Referring to fig. 5, fig. 5 is a schematic diagram of a second high-speed bus verification board option switching interface slot of fig. 4, and it can be seen from the drawing that a selection pin, that is, SEL, is disposed on a high-speed connection chip, and a plurality of interface pins are disposed on the high-speed connection chip, so that a defined function can be implemented by defining a function of each pin and connecting it to a corresponding device. The bit signals of the various interface sockets are connected to a sideband signal unit (CPLD chip) on the substrate. When the corresponding component device is inserted into the interface slot, the corresponding bit signal is pulled low. For the SFF 8639 interface and the M.2 interface, the CPLD judges the on-site type and whether the hard disk is on-site or not through the on-site signal and the IFDET signal. When the CPLD receives that a certain in-place signal is pulled down and recognizes the SFF 8639 interface and the M.2 interface as NVME equipment, the CPLD controls the corresponding selection signal SEL to enable, and automatically switches the high-speed connection chip access to the slot interface, thereby ensuring the normal operation of equipment inserted by the interface.

For example, in fig. 5, the e 1.s4cconn, SFF 8639Conn, and M2 Conn are connected to a second high-speed connector through a high-speed connection chip, and since a selection pin is disposed on the high-speed connection chip and is connected to the sideband signal unit, when the auxiliary device is not inserted into the interface slot, the bit pin of each interface slot is in a suspended state and is also in a high-level state, so when the auxiliary device is inserted into the corresponding interface slot, the level state of the bit pin of the interface slot becomes a low-level state, and if the auxiliary device is correspondingly inserted into the e 1.s4cconn, the level state of the e 1.s4cconn becomes a low level, and the high-speed connection chip is controlled to be turned on, and since the second high-speed connector is connected to the device to be tested, the second high-speed connector is turned on, and is equivalent to the verification loop between the auxiliary device and the device to be tested.

In one embodiment, the interface slot includes: at least two types of OCP slots, PCIE slots, SFF 8639 slots, e3.S slots, e1.S slots, m.2 slots.

In this embodiment, referring to fig. 2 and 4, different types of interface slots include at least two types of interface slots of OCP slot, PCIE slot, SFF 8639 slot, e3 s slot, e1 s slot, and m.2 slot, and the different types of interface slots are integrated on a substrate, so that a high-speed verification bus board can be used to fully verify supporting conditions and performance of various mainstream devices.

Illustratively, the use of the high-speed bus validation board provided in this application will be described in detail below in conjunction with FIGS. 4 and 5:

firstly, integrating different types of interface SLOTs on a substrate in fig. 4, integrating the different types of interface SLOTs on one substrate through the different types of interface SLOTs, connecting the different types of interface SLOTs with different interface SLOTs through a high-speed connection chip, connecting the different types of interface SLOTs with a second high-speed connector through a high-speed signal bus, connecting an auxiliary signal connector with equipment to be tested through an auxiliary signal cable, acquiring an I2C signal, a clock signal, an electric signal, a sideband signal and the like from the equipment to be tested through the auxiliary signal connector, then transmitting the acquired I2C signal to the different types of interface SLOTs through the power supply unit, the clock buffer, the I2C switch unit and the sideband signal unit, and then transmitting the acquired I2C signal to the different types of interface SLOTs through the different interfaces to be used as input devices of the different types of interface SLOTs, and providing different types of clock signals to the different interfaces; the sideband signals are distributed through the sideband signal unit and sent to auxiliary equipment on different types of interface slots according to different requirements, and particularly can comprise a PERST reset signal, a WAKE WAKE signal, a PRSNT in-place signal and the like, normal communication between equipment to be tested and the auxiliary equipment is guaranteed, and the first high-speed connector and the second high-speed connector can be MCIO, CDFP, slimline and other types of high-speed connectors.

With continued reference to fig. 5, when the high-speed bus verification board provided in fig. 4 is applied, after the high-speed bus verification board has been connected to a device to be tested through the first high-speed connector or the second high-speed connector, at this time, the auxiliary device is inserted into the corresponding type of interface SLOT on the high-speed bus verification board, and it is assumed that the interface SLOT into which the auxiliary device is inserted is OCP 4c+conn, as can be seen from fig. 4, the three interface SLOTs OCP 4c+conn, PCIE X16 SLOT, and e3.s4C Conn are connected to the same high-speed connection chip, at this time, only the auxiliary device is present on the OCP 4c+conn, at this time, the PCIE X16 SLOT and e3.s4C Conn are not used, at this time, and at this time, the sideband signal unit controls the high-speed connection chip to automatically turn on the auxiliary loop between the OCP 4c+conn and the device to be tested according to the in-place signal on the OCP 4c+conn, PCIE X16 SLOT, e3.s4C Conn. And when the equipment to be tested is verified in the later period, the auxiliary equipment inserted in the OCP 4C+Conn is selected to interact with the equipment to be tested, the high-speed bus connected with the high-speed bus verification board is verified, if the equipment to be tested is verified, the connection of the equipment to be tested can be maintained unchanged, the OCP 4C+Conn is removed, corresponding auxiliary equipment is inserted in other interface slots, and the interaction of the auxiliary equipment on other interface slots is continued. Of course, the auxiliary equipment can be kept unchanged, and the other type of equipment to be tested is accessed for verification, so that different high-speed cable connection modes can be selected, the high-speed links to be verified with different channel numbers and different links are connected to different types of equipment to be tested, or the same equipment to be tested is connected with different types of auxiliary equipment, and further the high-speed bus can be verified flexibly and fully.

Based on the same inventive concept, the present application also provides a high-speed bus verification system, which includes the high-speed bus verification board described in the first aspect of the embodiments of the present application, and a device to be tested connected to the high-speed bus verification board; the device to be tested comprises at least one processor, wherein at least one processor is respectively connected with a first high-speed connector on the high-speed bus verification board, or at least one processor is respectively connected with a second high-speed connector on the high-speed bus verification board.

In this embodiment, the high-speed bus verification system includes a high-speed bus verification board of the embodiment of the present application, and a device to be tested connected to the high-speed bus verification board, an interface slot, a first high-speed connector, a second high-speed connector, and a high-speed connection chip; the device to be tested comprises at least one processor, wherein the at least one processor is respectively connected with a first high-speed connector on the high-speed bus verification board, or the at least one processor is respectively connected with a second high-speed connector on the high-speed bus verification board.

By way of example, referring to fig. 6, fig. 6 is a schematic diagram of a first high-speed bus verification system provided in the embodiment of the present application for connecting a device to be tested, and fig. 6 is an illustration taking one OCP interface slot in a high-speed bus verification board as an example, it can be seen from the figure that there are 4 processors (CPU 0, CPU1, CPU2, CPU 3) in the device to be tested, each processor corresponds to a high-speed connector, and the high-speed connectors respectively correspond to each second high-speed connector on a substrate to be connected, by which the high-speed bus verification board can be verified to connect different processor test devices, and support conditions and performance of the device can be verified. The connection with the first high-speed connector refers to the connection manner of the second high-speed connector, and will not be described herein.

Further, when 4 high-speed connectors of X4 are used with respect to the substrate to connect to the high-speed device slots of X16. Because PCIE is downward compatible, when X8 devices are used on the corresponding high-speed device slots, only two low-level X4 high-speed connectors are connected to the devices to be tested; similarly, when using X4 or X1 devices, only one X4 high-speed connector in the lower position needs to be connected to the device under test; the support of the corresponding equipment can be realized only by using the number of connectors and cables of the high-speed bus resources corresponding to the equipment bandwidth, so that the occupation of the high-speed resources and cable resources of the equipment to be tested is reduced. In addition, 4X 4 high-speed connectors are placed on the substrate and can be connected to the server to-be-tested equipment in a matched mode of different cables, so that support and verification of an OCP network card or a PCIe network card of Multi host (also called Dual host) or Quad host are realized. Then the performance and support of a plurality of different types of host devices can be verified.

In one embodiment, the device under test includes a processor having a plurality of interfaces; the interfaces are respectively connected with a first high-speed connector on the high-speed bus verification board, or respectively connected with a second high-speed connector on the high-speed bus verification board.

In this embodiment, the device under test includes only one processor, where the processor includes a plurality of interfaces corresponding to one interface slot, and in order to ensure that the processor is connected to a plurality of first high-speed connectors or a plurality of second high-speed connectors on the interface slot, the processor may be connected to a plurality of first high-speed connectors or a plurality of second high-speed connectors through a plurality of interfaces, so as to connect to the high-speed bus verification board.

Referring to fig. 7, fig. 7 is a schematic diagram of a second high-speed bus verification system according to an embodiment of the present application connected to a device under test; fig. 7 is an illustration of an OCP interface slot in a high-speed bus validation board, and it can be seen from fig. 7 that the four high-speed connectors of X4 on the substrate can be connected to at most 4 interfaces (PE 0, PE1, PE2, and PE 3) of the same CPU by different cable connection methods, so as to validate that different RCs (Root Complex) of the CPU are connected to the same multi-host device, and support conditions and performance of the device are shown.

Based on the same inventive concept, there is also provided a high-speed bus verification method, including the high-speed bus verification system according to the second aspect of the present embodiment, the high-speed bus verification system including: a high-speed bus verification board and a device to be tested connected with the high-speed bus verification board through a high-speed bus; referring to fig. 8, fig. 8 is a step flowchart of a high-speed bus verification method according to an embodiment of the present application, where the method includes:

Step S1: inserting auxiliary equipment into a current interface slot on the high-speed bus verification board, and connecting current equipment to be tested with the current interface slot.

Firstly, the auxiliary equipment is inserted into an interface slot corresponding to the auxiliary equipment, and whether the processor of the equipment to be tested and the auxiliary equipment work normally or not is verified.

It is assumed that the substrate inserted in fig. 4 is connected to the device under test of fig. 6 through a high-speed bus, and the auxiliary signal module is connected to the device under test of fig. 6 through an auxiliary signal connector. The insertion of auxiliary devices into the OCP slot of fig. 4 is illustrated:

first, the Quad host OCP network card of the auxiliary device X16 is inserted into the OCP slot OCP 4c+conn on the substrate. After power-on, the CPLD automatically detects the type of the inserted device and automatically switches the PCIe MUX channel to the OCP slot to ensure the normal work of the OCP network card, and then inserts the auxiliary signal cable and connectors at the two ends of the high-speed signal cable into 4X 4 high-speed connectors corresponding to the OCP slot and 4X 4 high-speed connectors of the device to be tested to be verified; for example, the X4 high-speed connector HS CONN0 corresponding to the lower position [3:0] of the OCP slot is connected to the X4 high-speed connector of the CPU0, the X4 high-speed connector HS CONN1 corresponding to the lower position [7:4] of the OCP slot is connected to the X4 high-speed connector of the CPU1, the X4 high-speed connector HS CONN2 corresponding to the lower position [11:8] of the OCP slot is connected to the X4 high-speed connector of the CPU2, the X4 high-speed connector HS CONN3 corresponding to the lower position [15:12] of the OCP slot is connected to the X4 high-speed connector of the CPU3, and the verification of whether the processor and the auxiliary equipment work normally is started.

Step S2: verifying whether the current equipment to be tested is normally connected with the auxiliary equipment or not;

after the device to be tested and the auxiliary device are normally connected with the high-speed bus verification board, whether the current device to be tested and the auxiliary device are normally connected or not is verified, the auxiliary device can acquire the auxiliary signal through the auxiliary signal connector on the high-speed bus verification board, and if the auxiliary signal can be successfully acquired, the auxiliary device is normally connected with the processing.

In this embodiment, under the condition that the auxiliary device and the processor work normally, it may be indicated that each line on the substrate is normal, and since the first high-speed connector and the second high-speed connector are connected with the device to be tested, the high-speed bus resources of the device to be tested may be obtained through the first high-speed connector and the second high-speed connector, where the high-speed bus resources refer to various resources and components used for high-speed data transmission and communication in the computer system, and these resources and components include a physical interface, a controller, a bus protocol, a bandwidth, a frame structure and the like, which together form a high-speed bus in the computer system.

Step S3: and under the condition that the auxiliary equipment is normally connected with the current equipment to be tested, acquiring the high-speed bus resource of the current equipment to be tested.

In this embodiment, under the condition that the auxiliary device and the processor work normally, it may be indicated that each line on the substrate is normal, and since the first high-speed connector and the second high-speed connector are connected with the device to be tested, the high-speed bus resources of the device to be tested may be obtained through the first high-speed connector and the second high-speed connector, where the high-speed bus resources refer to various resources and components used for high-speed data transmission and communication in the computer system, and these resources and components include a physical interface, a controller, a bus protocol, a bandwidth, a frame structure and the like, which together form a high-speed bus in the computer system.

Step S4: based on the high-speed bus resource, verifying a high-speed bus on the current equipment to be tested; after verifying the current device to be tested, inserting an auxiliary device into a target interface slot different from the current interface slot, switching the next device to be tested to be connected with the target interface slot, and executing the steps S802 to S804.

In this embodiment, the auxiliary device and the device to be tested can interact with each other through the high-speed bus resource, so as to verify the signal integrity, protocol consistency, bandwidth, performance and compatibility of the high-speed bus. Through the verification, the signal can be ensured to be transmitted and analyzed correctly, the possibility of data transmission errors is reduced, each device to be tested can communicate and interact correctly on the bus, the high-speed bus can support high-bandwidth application and data transmission requirements in the system, and the high-speed bus can be connected and communicated with other devices correctly. The related test may be a PCIe lane margin test.

When the high-speed bus verification board in fig. 2 is used for verifying the high-speed bus of the device to be tested, since only the first high-speed connector is connected with the device to be tested, the first high-speed connector is directly connected between the interface slot and the device to be tested, after the high-speed bus of the device to be tested is verified by using the auxiliary equipment corresponding to one interface slot, if the high-speed bus of the device to be tested is verified by using the auxiliary equipment of the next target interface slot, the device to be tested can only be manually reconnected to the first high-speed connector corresponding to the next target interface slot for verification.

When the high-speed bus verification board in fig. 3 is used for verifying the high-speed bus of the device to be tested, since only the second high-speed connector is connected with the device to be tested and one second high-speed connector is connected with a plurality of interface slots through one high-speed connection chip, which is equivalent to the sharing of one second high-speed connector by a plurality of interface slots, since the high-speed connection chip is provided with the selection pins, after the high-speed bus of the device to be tested is verified by using the auxiliary equipment corresponding to one interface slot, if the high-speed bus of the device to be tested is verified by using the auxiliary equipment of the next target interface slot, the verification loop between the auxiliary equipment on the target interface slot and the device to be tested is conducted only by controlling the high-speed connection chip, and the verification by manually reconnecting the device to be tested to the first high-speed connector corresponding to the next target interface slot is not needed.

When the high-speed bus of the device to be tested is verified by using the high-speed verification board in fig. 4, because PCIE can be downward compatible, some interface slots may also connect a second high-speed connector by using a high-speed connection chip, but in an actual verification process, there may be some high-speed connectors that cannot connect the second high-speed connector by using the high-speed connection chip, and only connect by using a specific first high-speed connector, so that the requirement of fig. 1 can be satisfied by using the high-speed bus verification board in fig. 4, and the requirement of fig. 2 can also be satisfied.

In one embodiment, before acquiring the high-speed bus resource of the current device under test, in a case that the auxiliary device is normally connected with the current device under test, the method further includes: acquiring an in-place signal of the interface slot inserted by the auxiliary equipment; and under the condition that the bit signal indicates that the auxiliary equipment is inserted correctly, a verification loop between the auxiliary equipment and the equipment to be tested is conducted.

In this embodiment, before performing function verification on the auxiliary device, it is further required to verify whether the auxiliary device is correctly inserted into the corresponding interface slot, and in this way, a loop between the correct device to be tested and the auxiliary device can be selectively conducted, so that a verification loop for conducting the device to be tested and other interface slots not inserted into the auxiliary device is avoided, and accuracy is improved and time is saved.

In one embodiment, the verifying whether the current device under test and the auxiliary device are normally connected includes: the auxiliary signal module acquires an auxiliary signal from the processor; performing functional verification on the auxiliary equipment based on the auxiliary signal; and under the condition that the function verification result passes, determining that the processor and the auxiliary equipment work normally.

In the embodiment, the substrate acquires an electric signal from the equipment to be tested through the auxiliary signal connector, and a plurality of Efuses on the substrate convert the electric signal into electric signals required by the work of each device on the substrate, so that the normal power-on of each device on the substrate is ensured; the substrate also acquires a clock signal from the device to be tested through the auxiliary signal connector, the clock signal is used as the clock input of the CLK Buffer, the CLK Buffer output is connected to each high-speed interface slot on the substrate, and the clock is provided for the normal operation of the components inserted in the slots; the substrate also acquires PCIe reset signals from the device to be tested through the auxiliary signal connector for resetting the high-speed device, and then the device can be powered on and work normally. In addition, the device to be tested can acquire the component information of the inserted device through the I2C signal on the auxiliary signal connector, and if the auxiliary signals can successfully carry out the auxiliary device, the processor and the auxiliary device are indicated to work normally.

In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.

Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, systems according to embodiments of the invention. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the invention.

Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or terminal device comprising the element.

The foregoing has described in detail a high-speed bus verification board, system and method provided by the present invention, and specific examples have been used herein to illustrate the principles and embodiments of the present invention, the above examples being provided only to assist in understanding the method and core idea of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.

Claims (10)

1. A high-speed bus validation board, comprising: the device comprises a substrate, wherein different types of interface slots are integrated on the substrate; wherein, the interface slots of different types correspond to the auxiliary devices of different types;

the substrate is provided with a first high-speed connector; each interface slot is correspondingly connected with at least one first high-speed connector, one end of each first high-speed connector is connected with the interface slot, the other end of each first high-speed connector is used for being connected with equipment to be tested, and when the equipment to be tested is tested, high-speed transmission signals of the equipment to be tested are sequentially transmitted to the auxiliary equipment through the first high-speed connectors, and the interface slots are used for transmitting the signals to be tested to the auxiliary equipment;

And/or, at least one high-speed connection chip and a second high-speed connector corresponding to each high-speed connection chip are arranged on the substrate; the input end of the high-speed connection chip is connected with a plurality of interface slots respectively, the output end of the high-speed connection chip is connected with one end of the second high-speed connector, and the other end of the second high-speed connector is used for being connected with the equipment to be tested, so that when the equipment to be tested is tested, high-speed signals of the equipment to be tested are sequentially transmitted to the auxiliary equipment through the second high-speed connector, the high-speed connection chip and the interface slots.

2. The high-speed bus validation board of claim 1, wherein the substrate is further provided with an auxiliary signal module; the input end of the auxiliary signal module is used for being connected with the auxiliary signal generation module of the equipment to be tested, and the output end of the auxiliary signal module is respectively connected with the auxiliary signal pins of each interface slot;

the auxiliary signal module is used for acquiring auxiliary signals from the equipment to be tested so as to verify whether the auxiliary equipment functions normally.

3. The high-speed bus validation board of claim 2, wherein the auxiliary signal module comprises: the device comprises an auxiliary signal connector, a power supply unit, a clock buffer, an I2C switch unit and a sideband signal unit;

One end of the auxiliary signal connector is used for connecting the equipment to be tested, and the other end of the auxiliary signal connector is respectively connected with one ends of the power supply unit, the clock buffer, the I2C switch unit and the sideband signal unit;

the other ends of the power supply unit, the clock buffer, the I2C switch unit and the sideband signal unit are respectively connected with corresponding auxiliary signal pins on each interface slot.

4. A high speed bus validation board in accordance with claim 3 wherein said auxiliary signal module further comprises: the status indicator lamp is connected with the sideband signal unit;

the status indicator lamp is used for displaying the running status of the auxiliary equipment inserted into the interface slot.

5. The high-speed bus validation board of claim 1, wherein the interface slot comprises: at least two of an OCP slot, a PCIE slot, an SFF 8639 slot, an e3.S slot, an e1.S slot, an m.2 slot.

6. A high-speed bus verification system comprising the high-speed bus verification board of any one of claims 1-5, and a device under test connected to the high-speed bus verification board;

The device to be tested comprises at least one processor, wherein at least one processor is respectively connected with a first high-speed connector on the high-speed bus verification board, or at least one processor is respectively connected with a second high-speed connector on the high-speed bus verification board.

7. The high-speed bus validation system of claim 6, wherein the device under test comprises a processor, the processor having a plurality of interfaces; the interfaces are respectively connected with a first high-speed connector on the high-speed bus verification board, or respectively connected with a second high-speed connector on the high-speed bus verification board.

8. A high-speed bus verification method, applied to the high-speed bus verification system according to any one of claims 6 to 7, comprising: a high-speed bus verification board and a device to be tested connected with the high-speed bus verification board through a high-speed bus; the method comprises the following steps:

step S1: inserting auxiliary equipment into a current interface slot on the high-speed bus verification board, and connecting current equipment to be tested with the current interface slot;

Step S2: verifying whether the current equipment to be tested is normally connected with the auxiliary equipment;

step S3: under the condition that the auxiliary equipment is normally connected with the current equipment to be tested, acquiring high-speed bus resources of the current equipment to be tested;

step S4: based on the high-speed bus resource, verifying a high-speed bus on the current equipment to be tested;

after verifying the current device to be tested, inserting an auxiliary device into a target interface slot different from the current interface slot, switching the next device to be tested to be connected with the target interface slot, and executing the steps S2 to S4.

9. The method according to claim 8, wherein before acquiring the high-speed bus resource of the current device under test in the case where the auxiliary device is normally connected to the current device under test, the method further comprises:

acquiring an in-place signal of the interface slot inserted by the auxiliary equipment;

and under the condition that the bit signal indicates that the auxiliary equipment is inserted correctly, a verification loop between the auxiliary equipment and the equipment to be tested is conducted.

10. The high-speed bus verification method according to claim 8, wherein the verifying whether the current device under test and the auxiliary device are normally connected comprises:

The auxiliary signal module acquires an auxiliary signal from the processor;

performing functional verification on the auxiliary equipment based on the auxiliary signal;

and under the condition that the function verification result passes, determining that the processor and the auxiliary equipment work normally.