CN117289974A - FPGA programming file trusted update loading system and method for DCS controller - Google Patents
FPGA programming file trusted update loading system and method for DCS controller Download PDFInfo
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- 238000000034 method Methods 0.000 title claims abstract description 29
- 238000012795 verification Methods 0.000 claims abstract description 49
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/60—Software deployment
- G06F8/65—Updates
- G06F8/654—Updates using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44505—Configuring for program initiating, e.g. using registry, configuration files
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
- Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
Abstract
The invention discloses a system and a method for reliably updating and loading FPGA programming files for a DCS controller, wherein the loaded programming files are stored into a memory and are communicated with the FPGA through a host interface; acquiring a programming file from a memory, performing trusted computing, sending a trusted result obtained by computing to a trusted chip for trusted recalculation, and storing the trusted recalculation result; the FPGA sends the programming file obtained from the memory into the FLASH, reads the programming file sent into the FLASH into the memory for hash operation, sends the hash operation result into the trusted chip for recalculation, compares the recalculation result with the recalculation result stored by the trusted chip, and if the two results are equal, passes the trusted verification, the invention performs the trusted verification of the data in the updating and loading processes, ensures the correct reliability of the data, and further ensures the correct operation of the system; if the influence of external factors on the file in FLASH changes, the mechanism can effectively detect the problem.
Description
Technical Field
The invention belongs to the technical field of Field Programmable Gate Array (FPGA) programming file trusted updating and loading, and particularly relates to an FPGA programming file trusted updating and loading system and method for a Distributed Control System (DCS) controller.
Background
In the field of industrial control DCS, a DCS (distributed control system) controller is used as a 'brain' of the DCS to intensively complete the control function of the whole system, and in order to improve the flexibility of adapting to different working scenes, the DCS controller is often realized by adopting a CPU+FPGA architecture, so that when a programming file of the FPGA is in error or tampered, the function of the controller is possibly lost or even equipment is damaged, and great economic loss is brought; therefore, the reliability of the programming file in updating and loading is required to be improved, so that the functional correctness of the controller is improved, and the safety of the DCS and industrial equipment is ensured. At present, in the updating process, a CPU (central processing unit) directly writes data into a FLASH (FLASH memory unit) without verification; in the loading process, the CPU (central processing unit) directly reads the data in the FLASH (FLASH memory unit) and transmits the data to the FPGA (field programmable gate array), so that the updating and loading of the FPGA programming file are not checked in the updating and loading processes, and a direct mode is adopted, so that the accuracy and the safety of the data cannot be ensured.
Disclosure of Invention
The invention aims to provide a system and a method for trusted updating and loading of FPGA programming files of a DCS controller, which are used for solving the problem that the accuracy and the safety of data cannot be ensured in the process of loading and updating the data of the existing DCS controller.
The FPGA programming file trusted updating and loading system for the DCS controller comprises a CPU, a memory, an FPGA, a FLASH and a trusted chip;
the CPU is used for loading the programming file and storing the loaded programming file into the memory, and the CPU is communicated with the FPGA (field programmable gate array) through the host interface;
the FPGA is used for acquiring a programming file from the memory and performing trusted computing, sending a trusted result obtained by computing to the trusted chip for trusted recalculation, and storing the trusted recalculation result; the FPGA sends the programming files obtained from the memory into the FLASH, the CPU reads the programming files sent into the FLASH into the memory for hash operation, then sends the hash operation result into the trusted chip for recalculation, compares the recalculation result with the recalculation result stored by the trusted chip, if the two are equal, the two are verified by trust, the programming files are updated according to the verified programming files, and otherwise, the program files are not verified by trust.
Preferably, the FPGA firstly acquires a programming file from the memory, and then writes the programming file into the FLASH; the FPGA performs trusted computing on the programming file obtained from the memory, sends the trusted result obtained by computing to a trusted chip for trusted recalculation, and stores the trusted recalculation result; the FLASH carries out hash calculation on the obtained programming file, sends the calculation result to a trusted chip for recalculation, compares the recalculation result with the recalculation result stored by the trusted chip, if the calculation result and the recalculation result are equal, the trusted verification is carried out, the programming file is trusted, and the programming file is updated according to the programming file; otherwise, the trusted verification is not passed.
Preferably, the FPGA comprises a control register set, a data acquisition unit and a trusted unit;
the control register set is used for storing control instructions and feedback information of the CPU, and comprises a selection circuit control register, a programming file memory address register, a programming file length register, a programming file FLASH address register and a programming file updating completion register;
the data acquisition unit reads the programming file from the memory to the trusted unit of the FPGA according to the values of the memory address register and the length register of the programming file, simultaneously transmits the acquired programming file to the FLASH, and the trusted unit performs trusted calculation on the acquired programming file and sends the trusted result obtained by calculation to the trusted chip.
Preferably, bit0, bit1 and bit2 of the selection circuit control register are correspondingly connected with the first selection circuit, the second selection circuit and the third selection circuit respectively, and control signals of bit0, bit1 and bit2 of the selection circuit control register, which are correspondingly connected with the first selection circuit, the second selection circuit and the third selection circuit, are read and written by the CPU;
the memory address register of the programming file stores a 32-bit byte address, which represents the initial address stored in the memory of the programming file;
the programming file length register stores a 32bit byte length representing the actual length of the programming file;
the programming file FLASH address register stores a 32bit byte address representing the starting address of the programming file stored in FLASH.
Preferably, the FLASH writes the obtained programming file into a FLASH region with the value of the FLASH address register of the programming file as a starting address.
An FPGA programming file trusted updating method for a DCS controller comprises the following steps:
s1, a CPU reads a programming file to be updated into a memory;
s2, the CPU writes a selection circuit control register, and the FLASH and the trusted chip are controlled by the FPGA;
s3, the CPU writes the address of the programming file to be updated in the memory, the file length and the address of the area for storing the FPGA programming file into a programming file memory address register, a programming file length register and a programming file FLASH address register respectively;
s4, a data acquisition unit in the FPGA reads a programming file to be updated from the memory;
s5, the trusted unit in the FPGA performs trusted calculation on the read programming file, and the FPGA simultaneously sends the read programming file into an area for storing the FPGA programming file in the FLASH;
s6, the trusted unit sends the calculated trusted result to a trusted chip for trusted recalculation, and stores the trusted recalculation result;
s7, the CPU reads the programming files in the area for storing the FPGA programming files in the FLASH into the memory to perform hash operation; the CPU sends the hash operation result to a trusted chip for recalculation;
s8, the CPU compares the obtained recalculation result with the recalculation result stored in the trusted chip, if the recalculation result is equal to the recalculation result, the trusted verification is passed, and if the recalculation result is not equal to the trusted chip, the trusted verification is not passed.
Preferably, the FPGA sends the read programming file into one area for storing the FPGA programming file in FLASH at the same time, if the programming file fails to pass the trusted verification, 1 is added to record the failed times, and the steps S2-S8 are repeated until the failed times are equal to five, so that the programming file is in error and reported; ending the update.
Preferably, if one of the areas for storing the FPGA programming file passes the trusted verification, the written FLASH address is adjusted to be the other area for storing the FPGA programming file, if the other area for storing the FPGA programming file passes the trusted verification, the updating is finished, otherwise, the updating is reported.
A method for trusted loading of FPGA programming files for a DCS controller comprises the following steps:
s1, a CPU reads a programming file in one area for storing FPGA programming files in a FLASH into a memory to perform hash operation; and the CPU sends the hash operation result to the trusted chip for recalculation.
S2, the CPU reads out the recalculation result from the trusted chip and compares the recalculation result with the recalculation result stored by the trusted chip, and if the comparison result is equal to the recalculation result, the CPU passes the trusted verification; loading the FPGA by using a programming file of an area for storing the FPGA programming file in the FLASH; after loading is finished, if the FPGA ready signal is detected within 1ms, the loading is finished; if the FPGA ready signal is not detected within 1ms, ending the loading; if the verification is not passed, the programming file in another area of the FPGA programming file is read into the memory to carry out hash operation, and the hash operation is sent to the trusted chip to be recalculated.
S3, the CPU reads out the recalculation result from the trusted chip and compares the recalculation result with the recalculation result stored by the trusted chip, and if the comparison result is equal to the recalculation result, the CPU passes the trusted verification; loading the FPGA by using a programming file of an area passing through the programming file in the FLASH; after loading is finished, if the FPGA ready signal is detected within 1ms, the loading is finished; if the FPGA ready signal is not detected within 1ms, ending the loading; if the loaded file stored in the second block area does not pass the trusted verification, ending the loading.
Preferably, the trusted recalculation is performed by adopting one of the programming files of the area for storing the FPGA programming files, if the programming file of the area for storing the FPGA programming files does not pass the trusted verification, the trusted recalculation is performed by adopting the other programming file of the area for storing the FPGA programming files, and if the programming file of the area for storing the FPGA programming files passes the trusted verification, the loading is performed by adopting the programming file of the area for storing the FPGA programming files.
Compared with the prior art, the invention has the following beneficial technical effects:
the invention provides an FPGA programming file trusted updating and loading system for a DCS controller, which comprises a CPU, a memory, an FPGA, a FLASH and a trusted chip; the CPU is used for loading the programming file and storing the loaded programming file into the memory, and the CPU is communicated with the FPGA (field programmable gate array) through the host interface; the FPGA is used for acquiring a programming file from the memory and performing trusted computing, sending a trusted result obtained by computing to the trusted chip for trusted recalculation, and storing the trusted recalculation result; the FPGA sends the programming file obtained from the memory into the FLASH, the CPU reads the programming file sent into the FLASH into the memory for hash operation, then sends the hash operation result into the trusted chip for recalculation, compares the recalculation result with the recalculation result stored by the trusted chip, if the two are equal, the program file is updated according to the trusted verification, otherwise, the program file is not verified, the invention performs the trusted verification of the data in the updating and loading processes, ensures the correct reliability of the data, and further ensures the correct operation of the system; if the influence of external factors on the file in FLASH changes, the mechanism can effectively detect the problem.
The trusted chip is utilized to perform trusted calculation and verification on the programming file, so that the reliability of updating and loading the programming file is improved; the method for updating the programming file by the FPGA effectively reduces the load of the CPU and reduces the influence of the updating operation on other running tasks.
The method for trusted loading of the FPGA programming files for the DCS controller can ensure that the FPGA failure cannot be caused by updating failure by performing trusted verification on two different areas for storing the FPGA programming files.
Drawings
FIG. 1 is a schematic diagram of an FPGA programming file trusted update loading system for a DCS controller in an embodiment of the invention.
FIG. 2 is a flowchart of a method for trusted updating of FPGA programming files for a DCS controller in an embodiment of the invention.
FIG. 3 is a flowchart of a method for trusted loading of FPGA programming files for a DCS controller in an embodiment of the invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
As shown in FIG. 1, the invention provides a FPGA programming file trusted update loading system for a DCS controller, which comprises a CPU (central processing unit), a memory, an FPGA (field programmable gate array), a FLASH (FLASH memory unit) and a trusted chip;
the CPU is used for loading the programming file and storing the loaded programming file into the memory, and the CPU is communicated with the FPGA (field programmable gate array) through the host interface;
the FPGA is used for acquiring a programming file from the memory and performing trusted computing, sending a trusted result obtained by computing to the trusted chip for trusted recalculation, and storing the trusted recalculation result; the FPGA sends the programming files obtained from the memory into the FLASH, the CPU reads the programming files sent into the FLASH into the memory for hash operation, then sends the hash operation result into the trusted chip for recalculation, compares the recalculation result with the recalculation result stored by the trusted chip, if the two are equal, the two are verified by trust, the programming files are updated according to the verified programming files, and otherwise, the program files are not verified by trust.
The CPU is connected with the FLASH through a first selection circuit, the default CPU is connected with the FLASH through the first selection circuit after power-on, and then the CPU controls the FPGA to select.
The CPU is connected with the FPGA through a second selection circuit, the CPU controls the FPGA to be connected with the FLASH through the second selection circuit, the default CPU is connected with the FPGA through the second selection circuit after power-on, and then the CPU controls the FPGA to select.
The CPU is connected with the trusted chip through a third selection circuit, the CPU controls the FPGA to be connected with the trusted chip through the third selection circuit, the CPU is connected with the trusted chip by default after power-on, and then the CPU controls whether the FPGA is connected with the trusted chip or not.
The CPU controls the FPGA to complete the credible updating specific process of the programming file comprises the following steps: the FPGA firstly acquires a programming file from the memory, and then writes the programming file into the FLASH; the FPGA performs trusted computing on the programming file obtained from the memory, sends the trusted result obtained by computing to a trusted chip for trusted recalculation, and stores the trusted recalculation result; the FLASH carries out hash calculation on the obtained programming file, sends the calculation result to a trusted chip for recalculation, compares the recalculation result with the recalculation result stored by the trusted chip, if the calculation result and the recalculation result are equal, the trusted verification is carried out, the programming file is trusted, and the programming file is updated according to the programming file; otherwise, the trusted verification is not passed;
the memory is used to store data used by the CPU, including but not limited to programming files.
The FPGA acquires a programming file from a memory connected with the CPU according to the configuration of the host computer, and the acquisition mode is according to an interactive interface protocol between the CPU and the FPGA; and writing the programming file which passes the trusted verification into the FLASH to finish updating the programming file.
The FPGA comprises a control register group, a data acquisition unit, a trusted unit, a nonvolatile storage unit and a FLASH interface unit; the control register set is used for storing control instructions and feedback information of the CPU, and comprises a selection circuit control register, a programming file memory address register, a programming file length register, a programming file FLASH address register and a programming file updating completion register; wherein,
bit0, bit1 and bit2 of the selection circuit control register are correspondingly connected with the first selection circuit, the second selection circuit and the third selection circuit respectively, and control signals of bit0, bit1 and bit2 of the selection circuit control register are correspondingly connected with the first selection circuit, the second selection circuit and the third selection circuit and read and write by the CPU, namely the CPU controls the FPGA to be connected with the trusted chip and the FLASH respectively.
The programming file memory address register stores a 32bit byte address representing the starting address of the programming file stored in the memory, which is read and written by the CPU.
The program file length register stores a 32bit byte length representing the actual length of the program file, which is read and written by the CPU.
The FLASH address register of the programming file stores a 32-bit byte address, which represents the initial address of the programming file stored in the FLASH, and is read and written by the CPU, and the register writing operation enables the FPGA to start the updating of the programming file;
bit0 of the programming file updating completion register indicates whether the programming file updating is completed or not, 1 indicates completion, 0 indicates incompletion, 1 is arranged after the updating is completed by the FPGA, the CPU acquires the completion state by reading the programming file updating completion register, and 1 clear 0 is required to be written before the next updating.
The data acquisition unit reads the programming file from the memory to the trusted unit of the FPGA according to the values of the memory address register and the length register of the programming file, simultaneously transmits the acquired programming file to the FLASH, the trusted unit performs trusted computing on the acquired programming file, sends the trusted result obtained by computing to the trusted chip for trusted recalculation, and stores the trusted recalculated result in the nonvolatile storage unit.
Writing the obtained programming file into a FLASH area taking the value of a FLASH address register of the programming file as a starting address by the FLASH;
the area for storing the FPGA programming files of the FLASH comprises a programming file area 1 and a programming file area 2, and can store a complete FPGA programming file.
In the above scheme, the loading of the FPGA programming file adopts a mode that the CPU writes the FPGA.
As shown in fig. 2, the invention provides a method for updating the credibility of an FPGA programming file of a DCS controller, comprising the following steps:
s1, a CPU reads a programming file to be updated into a memory;
s2, the CPU writes a selection circuit control register, and the FLASH and the trusted chip are controlled by the FPGA;
s3, the CPU writes the address of the programming file to be updated in the memory, the file length and the address of the area for storing the FPGA programming file into a programming file memory address register, a programming file length register and a programming file FLASH address register respectively;
s4, a data acquisition unit in the FPGA reads a programming file to be updated from the memory;
s5, the trusted unit in the FPGA performs trusted calculation on the read programming file, and the FPGA simultaneously sends the read programming file into an area for storing the FPGA programming file in the FLASH;
s6, the trusted unit sends the calculated trusted result to a trusted chip for trusted recalculation, and stores the trusted recalculation result;
s7, the CPU reads the programming files in the area for storing the FPGA programming files in the FLASH into the memory to perform hash operation; the CPU sends the hash operation result to a trusted chip for recalculation;
s8, the CPU compares the obtained recalculation result with the trusted recalculation, if the recalculation result is equal to the trusted recalculation result, the trusted verification is passed, and otherwise, the trusted verification is not passed.
In step S5, the FPGA sends the read programming file into one area for storing the FPGA programming file in the FLASH at the same time, if the programming file fails the trusted verification, the number of times of failed times is recorded and is increased by 1, steps S2-S8 are repeated until the number of times of failed times is equal to five, and the programming file is in error and reported; ending the update.
And if one area for storing the FPGA programming file passes the trusted verification, the written FLASH address is adjusted to be the other area for storing the FPGA programming file, if the other area for storing the FPGA programming file passes the trusted verification, the updating is finished, and otherwise, the updating is reported.
As shown in fig. 3, the invention provides a method for trusted loading of FPGA programming files for a DCS controller, comprising the steps of:
s11, the CPU reads the programming files in one area of the FLASH for storing the FPGA programming files into the memory for hash operation; and the CPU sends the hash operation result to the trusted chip for recalculation.
S12, the CPU reads out the recalculation result from the trusted chip and compares the recalculation result with the recalculation result stored by the trusted chip, and if the comparison result is equal to the recalculation result, the CPU passes the trusted verification; loading the FPGA by using a programming file of an area for storing the FPGA programming file in the FLASH; after loading is finished, if the FPGA ready signal is detected within 1ms, the loading is finished; if the FPGA ready signal is not detected within 1ms, ending the loading; if the verification is not passed, the programming file in another area of the FPGA programming file is read into the memory to carry out hash operation, and the hash operation is sent to the trusted chip to be recalculated.
S13, the CPU reads out the recalculation result from the trusted chip and compares the recalculation result with the recalculation result stored by the trusted chip, and if the comparison result is equal to the recalculation result, the CPU passes the trusted verification; loading the FPGA by using a programming file of an area passing through the programming file in the FLASH; after loading is finished, if the FPGA ready signal is detected within 1ms, the loading is finished; if the FPGA ready signal is not detected within 1ms, ending the loading; if the loaded file stored in the second block area does not pass the trusted verification, ending the loading.
In step S13, a plurality of areas for storing the FPGA programming files are first used for trusted recalculation, if the programming file of one area for storing the FPGA programming files fails to pass the trusted verification, the other area for storing the FPGA programming files is used for trusted recalculation, and if the programming file of the other area for storing the FPGA programming files passes the trusted verification, the area for storing the FPGA programming files is used for loading.
The invention provides a FPGA programming file trusted updating and loading system for a DCS controller, which utilizes a trusted chip to perform trusted calculation and verification on the programming file, thereby improving the reliability of updating and loading the programming file; the method has the advantages that the FPGA is adopted to update the programming file, so that the CPU load is effectively reduced, and the influence of the updating operation on other running tasks is reduced; by performing the trusted verification on the two different areas for storing the FPGA programming files, the failure of updating can be ensured not to cause the failure of the FPGA.
Claims (10)
1. The FPGA programming file trusted updating and loading system for the DCS controller is characterized by comprising a CPU, a memory, an FPGA, a FLASH and a trusted chip;
the CPU is used for loading the programming file, storing the loaded programming file into the memory, and communicating with the FPGA through the host interface;
the FPGA is used for acquiring a programming file from the memory and performing trusted computing, sending a trusted result obtained by computing to the trusted chip for trusted recalculation, and storing the trusted recalculation result; the FPGA sends the programming files obtained from the memory into the FLASH, the CPU reads the programming files sent into the FLASH into the memory for hash operation, then sends the hash operation result into the trusted chip for recalculation, compares the recalculation result with the recalculation result stored by the trusted chip, if the two are equal, the two are verified by trust, the programming files are updated according to the verified programming files, and otherwise, the program files are not verified by trust.
2. The system for trusted updating and loading of FPGA programming files for DCS controllers of claim 1, wherein the FPGA obtains the programming files from memory and then writes the programming files into FLASH; the FPGA performs trusted computing on the programming file obtained from the memory, sends the trusted result obtained by computing to a trusted chip for trusted recalculation, and stores the trusted recalculation result; the FLASH carries out hash calculation on the obtained programming file, sends the calculation result to a trusted chip for recalculation, compares the recalculation result with the recalculation result stored by the trusted chip, if the calculation result and the recalculation result are equal, the trusted verification is carried out, the programming file is trusted, and the programming file is updated according to the programming file; otherwise, the trusted verification is not passed.
3. The FPGA programming file trusted update loading system for a DCS controller of claim 1, wherein the FPGA comprises a control register set, a data acquisition unit and a trusted unit;
the control register set is used for storing control instructions and feedback information of the CPU, and comprises a selection circuit control register, a programming file memory address register, a programming file length register, a programming file FLASH address register and a programming file updating completion register;
the data acquisition unit reads the programming file from the memory to the trusted unit of the FPGA according to the values of the memory address register and the length register of the programming file, simultaneously transmits the acquired programming file to the FLASH, and the trusted unit performs trusted calculation on the acquired programming file and sends the trusted result obtained by calculation to the trusted chip.
4. The FPGA programming file trusted updating and loading system for the DCS controller according to claim 3, wherein bit0, bit1 and bit2 of the selection circuit control register are correspondingly connected with the first selection circuit, the second selection circuit and the third selection circuit respectively, and control signals of bit0, bit1 and bit2 of the selection circuit control register are correspondingly connected with the first selection circuit, the second selection circuit and the third selection circuit and are read and written by the CPU;
the memory address register of the programming file stores a 32-bit byte address, which represents the initial address stored in the memory of the programming file;
the programming file length register stores a 32bit byte length representing the actual length of the programming file;
the programming file FLASH address register stores a 32bit byte address representing the starting address of the programming file stored in FLASH.
5. An FPGA programming file trusted upgrade loading system for DCS controllers as claimed in claim 1, wherein the FLASH writes the acquired programming file into a FLASH area with the value of the programming file FLASH address register as the starting address.
6. The FPGA programming file trusted updating method for the DCS controller is characterized by comprising the following steps of:
s1, a CPU reads a programming file to be updated into a memory;
s2, the CPU writes a selection circuit control register, and the FLASH and the trusted chip are controlled by the FPGA;
s3, the CPU writes the address of the programming file to be updated in the memory, the file length and the address of the area for storing the FPGA programming file into a programming file memory address register, a programming file length register and a programming file FLASH address register respectively;
s4, a data acquisition unit in the FPGA reads a programming file to be updated from the memory;
s5, the trusted unit in the FPGA performs trusted calculation on the read programming file, and the FPGA simultaneously sends the read programming file into an area for storing the FPGA programming file in the FLASH;
s6, the trusted unit sends the calculated trusted result to a trusted chip for trusted recalculation, and stores the trusted recalculation result;
s7, the CPU reads the programming files in the area for storing the FPGA programming files in the FLASH into the memory to perform hash operation; the CPU sends the hash operation result to a trusted chip for recalculation;
s8, respectively sending the FPGA and the CPU into the result of the recalculation of the trusted chip for comparison, if the result is equal, passing the trusted verification, otherwise, not passing the trusted verification.
7. The method for updating the FPGA programming file of the DCS controller according to claim 6, wherein the FPGA sends the read programming file into one area for storing the FPGA programming file in FLASH at the same time, if the read programming file fails the trusted verification, the number of failed times is increased by 1, the steps S2-S8 are repeated until the number of failed times is equal to five, the programming file is in error, and the report is performed; ending the update.
8. The method for updating the reliability of the FPGA programming file of the DCS controller according to claim 6, wherein if one area for storing the FPGA programming file passes the reliability verification, the written FLASH address is adjusted to be the other area for storing the FPGA programming file, if the other area for storing the FPGA programming file passes the reliability verification, the updating is finished, otherwise, the updating is reported.
9. The FPGA programming file trusted loading method for the DCS controller is characterized by comprising the following steps of:
s1, a CPU reads a programming file in one area for storing FPGA programming files in a FLASH into a memory to perform hash operation; the CPU sends the hash operation result to a trusted chip for recalculation;
s2, the CPU reads out the recalculation result from the trusted chip and compares the recalculation result with the recalculation result stored by the trusted chip, and if the comparison result is equal to the recalculation result, the CPU passes the trusted verification; loading the FPGA by using a programming file of an area for storing the FPGA programming file in the FLASH; after loading is finished, if the FPGA ready signal is detected within 1ms, the loading is finished; if the FPGA ready signal is not detected within 1ms, ending the loading; if the verification is not passed, reading the programming file in another area of the FPGA programming file into the memory to perform hash operation, and sending the hash operation to a trusted chip to perform recalculation;
s3, the CPU reads out the recalculation result from the trusted chip and compares the recalculation result with the recalculation result stored by the trusted chip, and if the comparison result is equal to the recalculation result, the CPU passes the trusted verification; loading the FPGA by using a programming file of an area passing through the programming file in the FLASH; after loading is finished, if the FPGA ready signal is detected within 1ms, the loading is finished; if the FPGA ready signal is not detected within 1ms, ending the loading; if the loaded file stored in the second block area does not pass the trusted verification, ending the loading.
10. The method for trusted loading of FPGA programming files for DCS controllers of claim 9, wherein the trusted recalculation is performed using one of the programming files for the region storing FPGA programming files, and if the programming file for the region storing FPGA programming files fails the trusted verification, the trusted recalculation is performed using another one of the programming files for the region storing FPGA programming files, and if the programming file for the region storing FPGA programming files fails the trusted verification, the trusted recalculation is performed using the programming file for the region storing FPGA programming files.
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