CN117289641A - Signal synchronous control circuit and wafer test system of optical chip - Google Patents
Signal synchronous control circuit and wafer test system of optical chip Download PDFInfo
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- CN117289641A CN117289641A CN202311585602.3A CN202311585602A CN117289641A CN 117289641 A CN117289641 A CN 117289641A CN 202311585602 A CN202311585602 A CN 202311585602A CN 117289641 A CN117289641 A CN 117289641A
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- 230000003287 optical effect Effects 0.000 title claims abstract description 152
- 238000012360 testing method Methods 0.000 title claims abstract description 139
- 230000001360 synchronised effect Effects 0.000 title claims abstract description 17
- 239000013307 optical fiber Substances 0.000 claims abstract description 278
- 238000013519 translation Methods 0.000 claims abstract description 69
- 238000004891 communication Methods 0.000 claims abstract description 54
- 230000008878 coupling Effects 0.000 claims abstract description 21
- 238000010168 coupling process Methods 0.000 claims abstract description 21
- 238000005859 coupling reaction Methods 0.000 claims abstract description 21
- 230000010287 polarization Effects 0.000 claims description 15
- 238000000034 method Methods 0.000 abstract description 5
- 230000008569 process Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 8
- 239000000835 fiber Substances 0.000 description 5
- 238000001228 spectrum Methods 0.000 description 5
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
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- 230000008859 change Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01M—TESTING STATIC OR DYNAMIC BALANCE OF MACHINES OR STRUCTURES; TESTING OF STRUCTURES OR APPARATUS, NOT OTHERWISE PROVIDED FOR
- G01M11/00—Testing of optical apparatus; Testing structures by optical methods not otherwise provided for
- G01M11/02—Testing optical properties
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01M—TESTING STATIC OR DYNAMIC BALANCE OF MACHINES OR STRUCTURES; TESTING OF STRUCTURES OR APPARATUS, NOT OTHERWISE PROVIDED FOR
- G01M11/00—Testing of optical apparatus; Testing structures by optical methods not otherwise provided for
- G01M11/02—Testing optical properties
- G01M11/0207—Details of measuring devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/0014—Measuring characteristics or properties thereof
- H01S5/0042—On wafer testing, e.g. lasers are tested before separating wafer into chips
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/24—Pc safety
- G05B2219/24215—Scada supervisory control and data acquisition
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- Optics & Photonics (AREA)
- Testing Of Optical Devices Or Fibers (AREA)
Abstract
The invention discloses a signal synchronous control circuit and a wafer test system of an optical chip, wherein the signal synchronous control circuit comprises: the device comprises a control module, a communication input port, a communication output port, a signal acquisition port and a pulse signal output port; the control module is respectively connected with the communication input port, the communication output port, the signal acquisition port and the pulse signal output port; the control module is used for receiving a first control instruction transmitted by the communication input port, sending a driving control instruction to the communication output port according to the control instruction, receiving a feedback signal acquired by the signal acquisition port in real time, and sending a pulse trigger signal to the pulse signal output port according to the feedback signal. According to the technical scheme, the scanning speed of two-dimensional light intensity coupling is improved, and the accumulated error in the moving process of the optical fiber translation table is reduced.
Description
Technical Field
The invention relates to the technical field of optical chip testing, in particular to a signal synchronous control circuit and a wafer testing system of an optical chip.
Background
The optical chip greatly increases the integration level of the optical module by integrating optical devices such as a laser, an optical waveguide, an optical parametric amplifier (Optical parametric amplification, OPA) and the like on the same substrate. In the field of optical chips, before a wafer is cut into a plurality of optical chips, the optical chips need to be tested to ensure the quality of the optical chips.
The test of the optical chip is a non-contact test, so before the optical chip is tested, an optimal coupling point between the test end of the optical chip and the test optical fiber needs to be found. At present, when searching the best coupling point, two-dimensional scanning is mostly adopted, specifically: the optical fiber moves a small distance, and the light receiver collects light intensity, so that the optical fiber reciprocates until the light receiver collects light intensity of all scanning points. In addition, the scanning speed of the method is slower, and the actual moving distance of the optical fiber has errors, and the scanning points of two-dimensional scanning often have hundreds of scanning points, so that the accumulated errors generated when the optical fiber moves are larger, the optimal coupling point is inaccurate, and the accuracy of the optical chip test is affected.
Disclosure of Invention
The invention provides a signal synchronous control circuit and a wafer test system of an optical chip, which are used for solving the problems existing in the prior art and improving the test efficiency and the test accuracy of the optical chip.
In a first aspect, the present invention provides a signal synchronization control circuit, comprising: the device comprises a control module, a communication input port, a communication output port, a signal acquisition port and a pulse signal output port;
the control module is respectively connected with the communication input port, the communication output port, the signal acquisition port and the pulse signal output port;
the communication output port and the signal acquisition port are both connected with external equipment; the pulse signal output port is connected with the optical receiver;
the control module is used for receiving a first control instruction transmitted by the communication input port, sending a driving control instruction to the communication output port according to the first control instruction so as to drive the external equipment to move, receiving a feedback signal of the external equipment collected by the signal collection port in real time, and sending a pulse trigger signal to the pulse signal output port according to the feedback signal so that the optical receiver can collect an optical signal according to the pulse trigger signal.
Optionally, the signal synchronization control circuit further includes: a switch module;
the switch module is connected between the control module and the pulse signal output port;
the switch module is used for conducting the control module and the pulse signal output port when receiving the first control instruction.
Optionally, the signal synchronization control circuit further includes: a pulse signal input port;
the pulse signal input port is connected with the pulse signal output port through the switch module;
the switch module is further used for disconnecting the control module and the pulse signal output port when receiving a second control instruction, and conducting the pulse signal input port and the pulse signal output port;
the pulse signal output port is also used for receiving the pulse synchronous signal sent by the pulse signal receiving input port.
In a second aspect, the present invention further provides a wafer testing system for optical chips, where at least one optical chip is disposed in a wafer to be tested; the optical chip comprises at least one test incident end and at least one test emergent end; the wafer test system of the optical chip comprises:
the test platform comprises a bearing surface for loading the wafer to be tested; the test platform is used for bearing and driving the wafer to be tested to move;
a light emitter for providing incident light;
a light receiver for receiving the outgoing light;
at least one first optical fiber; one end of the first optical fiber is coupled with the light emergent end of the light emitter, and the other end of the first optical fiber is positioned on the bearing surface side of the test platform; the first optical fiber is used for coupling the incident light provided by the light emitter onto the wafer to be tested so that the incident light is transmitted from the test incident end to the test emergent end;
at least one second optical fiber; one end of the second optical fiber is coupled to the light receiving end of the light receiver, and the other end of the second optical fiber is positioned on the bearing surface side; the second optical fiber is used for coupling emergent light emergent from the test emergent end to the optical receiver;
the signal synchronization control circuit according to any one of the above; the signal synchronization control circuit is used for controlling the test platform, the first optical fiber and/or the second optical fiber to move; and controlling the light receiver to receive the outgoing light.
Optionally, the wafer testing system of the optical chip further includes: the first optical fiber support is fixed on the first optical fiber translation stage; at least part of the first optical fiber is fixed on the first optical fiber bracket, and the first optical fiber and the wafer to be tested form a first preset angle;
the second optical fiber bracket is fixed on the second optical fiber translation stage; at least part of the second optical fiber is fixed on the second optical fiber bracket, and the second optical fiber and the wafer to be tested form a second preset angle;
the first optical fiber translation stage is used for driving the first optical fiber to move so as to enable the first optical fiber to be positioned at an optimal optical coupling position; the second optical fiber translation stage is used for driving the second optical fiber to move so as to enable the second optical fiber to be positioned at an optimal optical coupling position;
the signal synchronization control circuit is used for controlling the first optical fiber translation stage to drive the first optical fiber to move and controlling the second optical fiber translation stage to drive the second optical fiber to move.
Optionally, the wafer test system for optical chips is characterized by an optical fiber translation stage driver;
the optical fiber translation stage driver is respectively connected with the first optical fiber translation stage and the second optical fiber translation stage; the optical fiber translation stage driver is used for driving the first optical fiber translation stage and the second optical fiber translation stage to move;
the signal synchronization control circuit is used for driving the first optical fiber translation stage and/or the second optical fiber translation stage to move through the optical fiber translation stage driver.
Optionally, the wafer testing system of the optical chip further includes: a polarization module;
the first optical fiber is connected with the light emitter through the polarization module; the polarization module is used for controlling the polarization state of the incident light.
Optionally, the wafer testing system of the optical chip further includes: an optical path switching module;
the first optical fiber comprises a first optical fiber part and a second optical fiber part; the second optical fiber comprises a third optical fiber part and a fourth optical fiber part;
the optical path switching module comprises at least one first incident end, at least one first emergent end, at least one first switching end and at least one second switching end;
one end of the first optical fiber part is coupled with the light emergent end of the light emitter, and the other end of the first optical fiber part is correspondingly connected with the first incident end;
one end of the second optical fiber part is correspondingly connected with the first switching end, and the other end of the second optical fiber part is positioned on the bearing surface side;
one end of the third optical fiber part is coupled with the light receiving end of the light receiver, and the other end of the third optical fiber part is correspondingly connected with the first emergent end;
one end of the fourth optical fiber part is correspondingly connected with the second switching end, and the other end of the fourth optical fiber part is positioned on the bearing surface side;
the optical path switching module is used for controlling the communication relation between the first optical fiber part and the third optical fiber part and the second optical fiber part and the fourth optical fiber part respectively.
According to the technical scheme, a control module in the signal synchronous control circuit is respectively connected with a communication input port, a communication output port, a signal acquisition port and a pulse signal output port; the control module receives a first control instruction transmitted by the communication input port, and sends a driving control instruction to the communication output port according to the control instruction, so that external equipment connected with the communication output port is driven to move, meanwhile, feedback signals acquired by the signal acquisition port are received in real time, and pulse trigger signals are sent to the pulse signal output port according to the feedback signals, so that the control module can receive the feedback signals of the external equipment, and when the external equipment moves, the control module can send the pulse trigger signals to the pulse signal output port, so that the pulse trigger signals can control the light receiver connected with the pulse signal output port to acquire light signals, and in the moving process of the external equipment, the light receiver can acquire the light signals according to the pulse trigger signals, so that the scanning speed can be improved, meanwhile, the accumulated error generated when the external equipment moves can be reduced, the accuracy of an optimal coupling point is improved, and the efficiency and the accuracy of the light chip test are further improved.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a signal synchronization control circuit according to an embodiment of the present invention;
fig. 2 is a schematic structural diagram of a wafer testing system for optical chips according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another wafer testing system for optical chips according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a wafer testing system for optical chips according to another embodiment of the present invention.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein.
The embodiment provides a signal synchronization control circuit, fig. 1 is a schematic structural diagram of the signal synchronization control circuit provided by the embodiment of the invention, and referring to fig. 1, the signal synchronization control circuit 140 includes a control module 1, a communication input port 2, a communication output port 3, a signal acquisition port 4, and a pulse signal output port 5; the control module 1 is respectively connected with the communication input port 2, the communication output port 3, the signal acquisition port 4 and the pulse signal output port 5; the communication output port 3 and the signal acquisition port 4 are connected with external equipment; the pulse signal output port 5 is connected with the optical receiver; the control module 1 is configured to receive a first control instruction transmitted by the communication input port, send a driving control instruction to the communication output port 3 according to the first control instruction, so as to drive the external device to move, simultaneously receive, in real time, a feedback signal of the external device collected by the signal collection port 4, and send a pulse trigger signal to the pulse signal output port 5 according to the feedback signal, so that the optical receiver collects an optical signal according to the pulse trigger signal.
The communication input port 2 is used for receiving a first control instruction sent by the upper computer; the host computer may include, but is not limited to, a computer capable of sending control instructions, such as a computer, a cell phone, a tablet, a panel, a touch screen, and the like. The communication output port 3 is used for sending a drive control instruction to the external device so as to enable the external device to move; the external device may include, but is not limited to, a test platform including an optical chip test system, an incident optical fiber or an exit optical fiber, etc.; the first control instruction can be an optical intensity scanning instruction of an optical chip test system and the like; the drive control instructions may include, but are not limited to, a movement path, a movement distance, and/or a movement speed of the external device, etc. The signal acquisition port 4 is used for acquiring feedback signals of external equipment; the feedback signal may, but is not limited to, a signal including a motion state of an external device. The pulse signal output port 5 is used for sending a pulse trigger signal to the optical receiver so that the optical receiver can collect an optical signal according to the pulse trigger signal.
Specifically, the communication input port receives a first control instruction sent by the upper computer and transmits the first control instruction to the control module 1, so that the control module 1 sends a driving control instruction to the communication output port 3 according to the first control instruction to enable the external equipment to move; meanwhile, the signal acquisition port 4 acquires feedback signals such as the motion state of the external equipment and sends the feedback signals to the control module 1, so that the control module 1 sends pulse trigger signals to the pulse signal output port 5 according to the feedback signals, and the optical receiver connected with the pulse signal output port 5 acquires optical signals according to the pulse trigger signals.
In the embodiment, a control module in the signal synchronization control circuit is respectively connected with a communication input port, a communication output port, a signal acquisition port and a pulse signal output port; the control module receives a first control instruction transmitted by the communication input port, and sends a driving control instruction to the communication output port according to the control instruction, so that the external equipment is driven to move, meanwhile, a feedback signal acquired by the signal acquisition port is received in real time, a pulse trigger signal is sent to the pulse signal output port according to the feedback signal, so that the control module can receive the feedback signal of the external equipment, and when the external equipment moves, the control module can send the pulse trigger signal to the pulse signal output port, so that the pulse trigger signal can control the light receiver connected with the pulse signal output port to acquire the light signal, and in the moving process of the external equipment, the light receiver can acquire the light signal according to the pulse trigger signal, so that the scanning speed can be improved, meanwhile, the accumulated error generated when the external equipment moves can be reduced, the accuracy of an optimal coupling point is improved, and the efficiency and the accuracy of the light chip test are further improved.
Optionally, with continued reference to fig. 1, the signal synchronization control circuit 140 further includes a switch module 6; the switch module 6 is connected between the control module 1 and the pulse signal output port 5; the switch module 6 is configured to, when receiving the first control instruction, turn on the control module 1 and the pulse signal output port 5, so that the control module 1 can send a pulse trigger signal to the pulse signal output port 5 through the switch module 6, so that the optical receiver collects an optical signal according to the pulse trigger signal.
The switch module may include, but is not limited to, a semiconductor switch, a mechanical switch, and the like, and on the premise of being capable of implementing the core invention point of the embodiment of the present invention, the switch type included in the switch module is not specifically limited.
In an exemplary embodiment, the switch module includes an analog switch chip, in an exemplary embodiment, the switch module is a single pole double throw analog switch chip, the first control command includes a high level signal, and when the first control command is received, a port connected to the control module 1 and the pulse signal output port 5 in the single pole double throw analog switch chip is turned on, so that the control module 1 can send a pulse trigger signal to the pulse signal output port 5 through the switch module 6.
In an alternative embodiment, with continued reference to FIG. 1, the signal synchronization control circuit 140 further includes a pulse signal input port 7; the pulse signal input port 7 is connected with the pulse signal output port 5 through the switch module 6; the pulse signal output port 5 is also used for receiving the pulse synchronous signal sent by the pulse signal input port 7; the switch module 6 is further configured to disconnect the control module 1 and the pulse signal output port 5 when receiving the second control instruction, and turn on the pulse signal input port 7 and the pulse signal output port 5, so that the pulse signal input port 7 can send a pulse synchronization signal to the pulse signal output port 5 through the switch module 6, so that the optical receiver can collect an optical signal according to the pulse synchronization signal.
The pulse signal input port 7 is used for receiving a pulse synchronous signal sent by the optical transmitter; the pulse synchronization signal may be a pulse signal emitted while the light emitter emits incident light. The second control instruction may be a spectrum test instruction of the optical chip test system, or the like.
In an exemplary embodiment, when the switch module is a single pole double throw analog switch chip, the second control command may include a low level signal, and when the second control command is received, a port connected to the pulse signal input port 7 and the pulse signal output port 5 in the single pole double throw analog switch chip is turned on, so that a pulse synchronization signal received by the pulse signal input port can be sent to the pulse signal output port through the switch module 6, and thus the light emitter can collect an optical signal according to the pulse synchronization signal to complete the spectrum test.
In an exemplary embodiment, taking the communication output port 3 and the signal acquisition port 4 are both connected to the optical fiber translation stage, the pulse signal input port 7 receives the pulse signal sent by the optical transmitter, and the pulse signal output port 5 sends the pulse trigger signal to the optical receiver as an example, when the communication output port 3 receives the first control instruction, the communication output port 3 transmits the first control instruction to the control module 1, so that the control module 1 sends the driving control instruction to the communication output port 3 according to the first control instruction to drive the optical fiber translation stage to move according to the driving control instruction, and meanwhile, the signal acquisition port 4 acquires a feedback signal such as a motion state of the test platform and sends the feedback signal to the control module 1, so that the control module 1 generates the pulse trigger signal according to the feedback signal, at this time, the switch module 6 receives the first control instruction, the control module 1 and the pulse signal output port 5 are turned on, and the control module 1 sends the pulse trigger signal to the pulse signal output port 5 through the switch module 6, so that the optical receiver connected to the pulse signal output port 5 acquires the optical signal according to the pulse trigger signal; when receiving the second control instruction, the switch module 6 disconnects the control module 1 and the pulse signal output port 5, and turns on the pulse signal input port 7 and the pulse signal output port 5, so that the pulse synchronous signal sent by the optical transmitter is transmitted to the pulse signal output port 5 through the pulse signal input port 7 and the switch module 6, and the optical receiver acquires the optical signal according to the pulse synchronous signal.
Optionally, with continued reference to fig. 1, the switch module 6 includes a selection switch 61; the selection switch 61 includes a first stationary contact a, a second stationary contact B, and a movable contact C; the movable contact C is connected with the pulse signal output port; the first stationary contact A is connected with the control module 1; the second stationary contact B is electrically connected with the pulse signal input port 7; when the switch module 6 receives a first control signal, the first stationary contact A is communicated with the movable contact C, so that the control module 1 is communicated with the pulse signal output port 5; when the switch module 6 receives the second control signal, the second stationary contact B is connected to the movable contact C, so that the control module 1 is disconnected from the pulse signal output port 5, and the pulse signal input port 7 is connected to the pulse signal output port 5, thereby simplifying the structure of the signal synchronization control circuit.
Based on the same inventive concept, the embodiment also provides a wafer testing system of the optical chip, which is used for testing the wafer to be tested. Fig. 2 is a schematic structural diagram of a wafer testing system for optical chips according to an embodiment of the present invention, and referring to fig. 2, the testing system includes a testing platform 010, an optical transmitter 020, an optical receiver 030, at least one first optical fiber 040, at least one second optical fiber 050, and a signal synchronization control circuit 140 according to any of the foregoing embodiments. The test platform 010 includes a load surface 011 for loading a wafer to be tested; the test platform 010 is used for carrying and driving the wafer 060 to be tested to move; the light emitter is used for providing incident light; the light receiver 030 is for receiving outgoing light; one end of the first optical fiber 040 is coupled to the light emergent end of the light emitter 020, and the other end of the first optical fiber 040 is positioned on the side of the bearing surface 011 of the test platform 100; the first optical fiber 040 is used for coupling incident light provided by the light emitter 020 to the wafer 060 to be tested, so that the incident light is transmitted from the test incident end to the test emergent end; one end of the second optical fiber 050 is coupled to the light receiving end of the light receiver 030, and the other end of the second optical fiber 050 is located at the bearing surface 011 side; the second optical fiber 050 is used for coupling emergent light emergent from the test emergent end to the optical receiver 030; the signal synchronization control circuit 140 is used for controlling the test platform 010, the first optical fiber 040 and/or the second optical fiber 050 to move; and controls the light receiver 030 to receive the outgoing light.
Wherein, at least one optical chip is arranged in the wafer 060 to be tested; each optical chip comprises at least one test incident end and at least one test emergent end. It should be noted that fig. 1 only illustrates a case where the optical chip includes one test incident end and one test exit end, and the number of the test incident ends and the test exit ends in the optical chip is not limited. It will be appreciated that optical devices including, but not limited to, optical waveguides, lasers, optical couplers and splitters may be provided in each optical chip, each optical device including a test point, each set of test points including at least one test entry end and at least one test exit end, e.g., each optical waveguide including one test entry end and one test exit end, each optical coupler including two test entry ends and one test exit end.
The test platform 010 is configured to carry and drive the wafer to be tested 060 to move, in an alternative embodiment, the test platform 010 can complete loading, unloading, leveling, and the like of the wafer to be tested 060, and can also complete distributed scanning of the wafer to be tested 060, set test points of the wafer to be tested 060, drive the wafer to be tested 060 to move according to the test points, drive the wafer to be tested 060 to move according to optical chips, and the like. In this embodiment, the test platform 010 can drive the wafer 060 to be tested to move to the target position accurately, and can also drive the wafer to move to the coordinate position accurately according to the input coordinates.
The light emitter 020 can emit light with different wavelengths or different frequencies according to test requirements, and the light emitter 020 can emit sweep light with a fixed rule. The optical transmitter 020 is used for providing corresponding incident light according to the test requirement of the wafer 060 to be tested, and the optical transmitter 020 can send out pulse synchronous signals while providing the incident light. It should be noted that fig. 1 only illustrates a case where the light emitter 020 includes one light emitting end, and in an alternative embodiment, the light emitter 020 may further include a plurality of light emitting ends, and in this embodiment, the number of light emitting ends of the light emitter 020 is the same as the number of test incident ends.
The light receiver 030 is configured to receive the outgoing light, and test optical signal parameters such as optical power, optical intensity, etc. of the outgoing light according to a test requirement of the wafer 060 to be tested. The light receiver 030 can collect the optical signal parameter according to the collection instruction such as the pulse trigger signal or pulse synchronization signal received; in an exemplary embodiment, the light receiver 030 may complete a single light signal acquisition according to a received acquisition instruction and output light signal parameter data of the single acquisition after the acquisition is completed, and in another exemplary embodiment, the light receiver 030 may complete a plurality of light signal acquisitions according to a received acquisition instruction and output light signal parameter data of the plurality of acquisitions after the acquisition is completed or reset. It should be noted that fig. 1 illustrates a case where the light receiver 030 includes one light receiving end, and in an alternative embodiment, the light receiver 030 may further include a plurality of light receiving ends, and in this embodiment, the number of light receiving ends of the light receiver 030 is the same as the number of test exit ends.
It should be noted that fig. 1 only illustrates a case where the test system includes one first optical fiber 040 and one second optical fiber 050, and the number of the first optical fibers 040 and the second optical fibers 050 is not limited, and in this embodiment, the number of the first optical fibers 040 is the same as the number of the test incident ends, and the number of the second optical fibers 050 is the same as the number of the test exit ends. The first optical fiber 040 and the second optical fiber 050 are used for transmitting an optical signal.
The first optical fiber 040 one end is coupled in the light emergent end of the optical transmitter 020, and the other end is located in the bearing surface 011 side of the test platform 010, so that the first optical fiber 040 can provide the incident light provided by the optical transmitter 020 to the bearing surface 011 side of the test platform 010, when the bearing surface 011 of the test platform 010 bears the wafer 060 to be tested and the other end of the first optical fiber 040 is coupled with the test incident end of the wafer 060 to be tested, the incident light provided by the optical transmitter 020 can be coupled to the wafer 060 to be tested through the first optical fiber 040, and the incident light can be transmitted to the test emergent end by the test incident end of the wafer 060 to be tested.
One end of the second optical fiber 050 is coupled to the light receiving end of the light receiver 030, and the other end is located at the bearing surface 011 side, so when the other end of the second optical fiber 050 is coupled to the test emission end of the wafer 060 to be tested, the emitted light emitted from the test emission end can be transmitted to the light receiver 030 through the second optical fiber 050.
The communication input port 2 of the signal synchronization control circuit 140 is configured to receive a control instruction and send the control instruction to the control module 1, so that the control module 1 generates a driving control signal when receiving a first control instruction; the communication output port 3 is connected with the test platform 010, the first optical fiber 040 and/or the second optical fiber 050, and the communication output port 3 is used for providing a driving control instruction sent by the control module 1 to the test platform 010, the first optical fiber 040 and/or the second optical fiber 050 to connect so that the test platform 010, the first optical fiber 040 and/or the second optical fiber 050 move according to the driving control instruction; the signal acquisition port 4 is connected with the test platform 010, the first optical fiber 040 and/or the second optical fiber 050, and the signal acquisition port 4 is used for acquiring feedback signals such as the motion state of the test platform 010, the first optical fiber 040 and/or the second optical fiber 050 and sending the feedback signals to the control module 1 so that the control module 1 sends pulse trigger signals to the pulse signal output end according to the feedback signals; the pulse signal output end is connected with the light receiver 030, and the pulse signal output end is used for providing a pulse trigger signal to the light receiver 030, so that the light receiver 030 collects an optical signal according to the pulse trigger signal.
In an alternative embodiment, the optical transmitter 020 is connected to the pulse signal input port 7, and when the control module 1 receives the second control instruction, the pulse signal input port 7 is connected to the pulse signal output port 5, the control module 1 is disconnected from the pulse signal output port 5, and the pulse synchronization signal sent by the optical transmitter 020 is transmitted to the pulse signal output port 5 through the pulse signal input port 7, so that the pulse signal output port 5 provides the pulse synchronization signal to the optical receiver 030, so that the optical receiver 030 collects the optical signal according to the pulse synchronization signal.
In an exemplary embodiment, taking the first control signal as the light intensity scanning signal and the second control signal as the spectrum test signal as an example, when the control module 1 receives the light intensity scanning signal, a driving control instruction is sent to the communication output port 3, so that the communication output port 3 provides the driving control instruction to the test platform 010, the first optical fiber 040 and/or the second optical fiber 050, where the driving control instruction may include a moving path, a moving distance, a moving speed and the like of the test platform 010, the first optical fiber 040 and/or the second optical fiber 050, and the test platform 010, the first optical fiber 040 and/or the second optical fiber 050 move according to the driving control instruction; meanwhile, the control module 1 generates a frequency of transmitting the effective level of the pulse trigger signal according to the first control instruction, for example, the effective level of the pulse trigger signal is transmitted once every 1 ms; the signal collection port 4 collects feedback signals of the test platform 010, the first optical fiber 040 and/or the second optical fiber 050, and sends the feedback signals to the control module 1, when the test platform 010, the first optical fiber 040 and/or the second optical fiber 050 start to move according to the movement of the driving control instruction, the control module 1 starts to send a pulse trigger signal for enabling the light receiver 030 to collect light signals to the pulse signal output end, and accordingly the light receiver 030 collects the light signals when receiving the effective level of the pulse trigger signal, and light intensity scanning is completed. When the control module 1 receives the spectrum test signal, the control module 1 and the pulse signal output port 5 are disconnected, the pulse signal input port 7 and the pulse signal output port 5 are connected, the optical transmitter 020 provides light with different wavelengths, the optical transmitter 020 provides light with each wavelength, and simultaneously, the effective level of a primary pulse synchronous signal is sent out, and the pulse synchronous signal is transmitted to the pulse signal output port 5 through the pulse signal input port 7 and then provided to the optical receiver 030, so that when the optical receiver 030 receives the effective level of the pulse synchronous signal, the optical signal is collected, and the spectrum test of the optical chip is completed.
In this embodiment, the optical transmitter of the wafer test system of the optical chip provides incident light, the optical receiver receives emergent light, one end of the first optical fiber is coupled to the light emergent end of the optical transmitter, the other end of the first optical fiber is located on the bearing surface side of the test platform, one end of the second optical fiber is coupled to the light receiving end of the optical receiver, the other end of the second optical fiber is located on the bearing surface side of the test platform, the movement of the test platform, the first optical fiber and/or the second optical fiber is controlled by the signal synchronization control circuit 1, and the optical receiver is controlled to receive the emergent light, so that in the movement process of the test platform, the first optical fiber and/or the second optical fiber, the optical receiver can acquire optical signals according to pulse trigger signals, thereby improving the scanning speed, reducing accumulated errors generated when external equipment moves, improving the accuracy of an optimal coupling point, and further improving the efficiency and accuracy of the optical chip test.
Optionally, the wafer testing system of the optical chip further includes a first optical fiber translation stage 070, a second optical fiber translation stage 080, a first optical fiber support 090 and a second optical fiber support 100; the first fiber support 090 is fixed to the first fiber translation stage 070; at least part of the first optical fiber 040 is fixed on a first optical fiber bracket 090, and the first optical fiber 040 and a wafer 060 to be tested form a first preset angle; the second fiber support 100 is fixed to a second fiber translation stage 080; at least part of the second optical fiber 050 is fixed on the second optical fiber support 100, and the second optical fiber 050 and the wafer 060 to be tested form a second preset angle; the first optical fiber translation stage 070 is used for driving the first optical fiber 040 to move so that the first optical fiber 040 is positioned at an optimal optical coupling position; the second optical fiber translation stage 080 is used for driving the second optical fiber 050 to move so as to enable the second optical fiber 050 to be located at an optimal optical coupling position; the signal synchronization control circuit 140 controls the first optical fiber translation stage to drive the first optical fiber to move, and controls the second optical fiber translation stage to drive the second optical fiber to move.
Wherein the first optical fiber translation stage 070 and the second optical fiber translation stage 080 are located around the test platform 010, and the communication output port 3 of the signal synchronization control circuit 140 is connected with the first optical fiber translation stage 070 and/or the second optical fiber translation stage 080, so as to drive the first optical fiber 040 to move by controlling the first optical fiber translation stage 070 to move, and drive the second optical fiber 050 to move by controlling the second optical fiber translation stage 080 to move. In an alternative embodiment, the wafer test system for optical chips may further include a fiber translation stage driver 110; the optical fiber translation stage driver 110 is connected with the first optical fiber translation stage 070 and the second optical fiber translation stage 080 respectively, and the communication output port 3 of the signal synchronization control circuit 140 is connected with the optical fiber translation stage driver 110 so as to drive the first optical fiber translation stage 070 and/or the second optical fiber translation stage 080 to move through the optical fiber translation stage driver 110, thereby being capable of improving the accuracy of the first optical fiber translation stage 070 and the second optical fiber translation stage 080 and improving the accuracy of test results.
The optical fiber translation stage can be, but is not limited to, a triaxial optical fiber translation stage, and the triaxial optical fiber translation stage can drive the optical fiber to move in the X direction, the Y direction and the Z direction, so that the optical fiber can move in the horizontal and vertical directions. According to the test requirement, the optical fiber translation stage may also be a two-axis optical fiber translation stage, a six-axis optical fiber translation stage, etc., which is not limited in this embodiment.
The first preset angle and the second preset angle are determined according to the test requirement of the wafer 060 to be tested, and the first preset angle and the second preset angle may be the same or different, which is not limited in this embodiment.
At least a portion of the first optical fiber 040 is fixed to the first optical fiber support 090, that is, an end of the first optical fiber 040 away from the optical transmitter 020 is fixed to the first optical fiber support 090, and the first optical fiber support 090 is fixed to the first optical fiber translation stage 070, so that when the first optical fiber translation stage 070 moves, the first optical fiber 040 can be driven to move, so that the first optical fiber 040 can move to an optimal optical coupling position; similarly, at least a portion of the second optical fiber 050 is fixed to the second optical fiber support 100, that is, an end of the second optical fiber 050 away from the optical receiver 030 is fixed to the second optical fiber support 100, and the second optical fiber support 100 is fixed to the second optical fiber translation stage 080, so that when the second optical fiber translation stage 080 moves, the second optical fiber 050 can be driven to move, so that the second optical fiber 050 can move to an optimal optical coupling position.
Optionally, fig. 3 is a schematic structural diagram of another wafer testing system for optical chips according to an embodiment of the present invention, and referring to fig. 3, the wafer testing system for optical chips further includes a polarization module 120; the first optical fiber 040 is connected with the light emitter 020 through the polarization module 120; the polarization module 120 is configured to control the polarization state of incident light, so that when the optical chip sensitive to the characteristic polarization state is tested, the polarization module 120 can convert the incident light provided by the optical transmitter 020 into polarized light with a specific polarization state according to a corresponding instruction.
Optionally, fig. 4 is a schematic structural diagram of a wafer testing system for an optical chip according to another embodiment of the present invention, and referring to fig. 4, the wafer testing system for an optical chip further includes an optical path switching module 130; the first optical fiber 040 includes a first optical fiber portion 041 and a second optical fiber portion 042; the second optical fiber 050 includes a third optical fiber part 051 and a fourth optical fiber part 052; the optical path switching module 130 includes at least one first incident end 131, at least one first exit end 132, at least one first switching end 133, and at least one second switching end 134; one end of the first optical fiber portion 041 is coupled to the light emitting end of the light emitter 020, and the other end of the first optical fiber portion 041 is correspondingly connected to the first incident end 131; one end of the second optical fiber portion 042 is correspondingly connected with the first switching end 133, and the other end of the second optical fiber portion 042 is positioned on the side of the carrying surface 011; one end of the third optical fiber portion 051 is coupled to the light receiving end of the light receiver 030, and the other end of the third optical fiber portion 051 is correspondingly connected with the first emitting end 132; one end of the fourth optical fiber portion 052 is correspondingly connected with the second switching end 134, and the other end of the fourth optical fiber portion 052 is located at the bearing surface 011 side; the optical path switching module 130 is configured to control the communication relationship between the first optical fiber portion 041 and the third optical fiber portion 051 and the second optical fiber portion 042 and the fourth optical fiber portion 052, respectively.
The connection relationship between the optical path switching module 130 and the second optical fiber 042 and the third optical fiber 051 may be that the optical path switching module 130 controls the first optical fiber 041 to be connected to the second optical fiber 042 and the third optical fiber 051 to be connected to the fourth optical fiber 052, or the optical path switching module 130 controls the first optical fiber 041 to be connected to the fourth optical fiber 052 and the third optical fiber 051 to be connected to the second optical fiber 042, so that when the wafer 060 to be tested includes multiple groups of test points, if the positions of the test incident ends and the test emergent ends of the adjacent two groups of test points are opposite, after the previous group of test points are tested, the optical path switching module 130 is controlled to change the connection relationship between the first optical fiber 041 and the third optical fiber 051 and the second optical fiber 042, and the next group of test points can be tested, so that the positions of the first optical fiber 040 and the second optical fiber 050 are not required to be manually changed, thereby further improving the test efficiency of the wafer 060 to be tested.
The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.
Claims (8)
1. A signal synchronization control circuit, comprising: the device comprises a control module, a communication input port, a communication output port, a signal acquisition port and a pulse signal output port;
the control module is respectively connected with the communication input port, the communication output port, the signal acquisition port and the pulse signal output port;
the communication output port and the signal acquisition port are both connected with external equipment; the pulse signal output port is connected with the optical receiver;
the control module is used for receiving a first control instruction transmitted by the communication input port, sending a driving control instruction to the communication output port according to the first control instruction so as to drive the external equipment to move, receiving a feedback signal of the external equipment collected by the signal collection port in real time, and sending a pulse trigger signal to the pulse signal output port according to the feedback signal so that the optical receiver can collect an optical signal according to the pulse trigger signal.
2. The signal synchronization control circuit of claim 1, further comprising: a switch module;
the switch module is connected between the control module and the pulse signal output port;
the switch module is used for conducting the control module and the pulse signal output port when receiving the first control instruction.
3. The signal synchronization control circuit of claim 2, further comprising: a pulse signal input port;
the pulse signal input port is connected with the pulse signal output port through the switch module;
the switch module is further used for disconnecting the control module and the pulse signal output port when receiving a second control instruction, and conducting the pulse signal input port and the pulse signal output port;
the pulse signal output port is also used for receiving the pulse synchronous signal sent by the pulse signal input port.
4. A wafer test system of optical chips is characterized in that at least one optical chip is arranged in a wafer to be tested; the optical chip comprises at least one test incident end and at least one test emergent end; the wafer test system of the optical chip comprises:
the test platform comprises a bearing surface for loading the wafer to be tested; the test platform is used for bearing and driving the wafer to be tested to move;
a light emitter for providing incident light;
a light receiver for receiving the outgoing light;
at least one first optical fiber; one end of the first optical fiber is coupled with the light emergent end of the light emitter, and the other end of the first optical fiber is positioned on the bearing surface side of the test platform; the first optical fiber is used for coupling the incident light provided by the light emitter onto the wafer to be tested so that the incident light is transmitted from the test incident end to the test emergent end;
at least one second optical fiber; one end of the second optical fiber is coupled to the light receiving end of the light receiver, and the other end of the second optical fiber is positioned on the bearing surface side; the second optical fiber is used for coupling emergent light emergent from the test emergent end to the optical receiver;
a signal synchronization control circuit according to any one of claims 1-3; the signal synchronization control circuit is used for controlling the test platform, the first optical fiber and/or the second optical fiber to move; and controlling the light receiver to receive the outgoing light.
5. The wafer testing system of optical chips of claim 4, further comprising: the first optical fiber support is fixed on the first optical fiber translation stage; at least part of the first optical fiber is fixed on the first optical fiber bracket, and the first optical fiber and the wafer to be tested form a first preset angle;
the second optical fiber bracket is fixed on the second optical fiber translation stage; at least part of the second optical fiber is fixed on the second optical fiber bracket, and the second optical fiber and the wafer to be tested form a second preset angle;
the first optical fiber translation stage is used for driving the first optical fiber to move so as to enable the first optical fiber to be positioned at an optimal optical coupling position; the second optical fiber translation stage is used for driving the second optical fiber to move so as to enable the second optical fiber to be positioned at an optimal optical coupling position;
the signal synchronization control circuit is used for controlling the first optical fiber translation stage to drive the first optical fiber to move and controlling the second optical fiber translation stage to drive the second optical fiber to move.
6. The wafer testing system of optical chips of claim 5, further comprising: an optical fiber translation stage driver;
the optical fiber translation stage driver is respectively connected with the first optical fiber translation stage and the second optical fiber translation stage; the optical fiber translation stage driver is used for driving the first optical fiber translation stage and the second optical fiber translation stage to move;
the signal synchronization control circuit is used for driving the first optical fiber translation stage and/or the second optical fiber translation stage to move through the optical fiber translation stage driver.
7. The wafer testing system of optical chips of claim 4, further comprising: a polarization module;
the first optical fiber is connected with the light emitter through the polarization module; the polarization module is used for controlling the polarization state of the incident light.
8. The wafer testing system of optical chips of claim 4, further comprising: an optical path switching module;
the first optical fiber comprises a first optical fiber part and a second optical fiber part; the second optical fiber comprises a third optical fiber part and a fourth optical fiber part;
the optical path switching module comprises at least one first incident end, at least one first emergent end, at least one first switching end and at least one second switching end;
one end of the first optical fiber part is coupled with the light emergent end of the light emitter, and the other end of the first optical fiber part is correspondingly connected with the first incident end;
one end of the second optical fiber part is correspondingly connected with the first switching end, and the other end of the second optical fiber part is positioned on the bearing surface side;
one end of the third optical fiber part is coupled with the light receiving end of the light receiver, and the other end of the third optical fiber part is correspondingly connected with the first emergent end;
one end of the fourth optical fiber part is correspondingly connected with the second switching end, and the other end of the fourth optical fiber part is positioned on the bearing surface side;
the optical path switching module is used for controlling the communication relation between the first optical fiber part and the third optical fiber part and the second optical fiber part and the fourth optical fiber part respectively.
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