CN117280459A

CN117280459A - Chip packaging structure, preparation method thereof and electronic equipment

Info

Publication number: CN117280459A
Application number: CN202180044498.XA
Authority: CN
Inventors: 江宇; 赵南; 洪瑞斌; 蒋尚轩; 张童龙
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2021-12-29
Filing date: 2021-12-29
Publication date: 2023-12-22
Also published as: WO2023123106A1

Abstract

The embodiment of the application provides a chip packaging structure, a preparation method thereof and electronic equipment, and can solve the problems of layering of a rewiring layer and cracking of a packaging layer between two adjacent bare chips in the chip packaging structure. The chip packaging structure comprises: a substrate, at least one bare chip, a rewiring layer, a reinforcing structure and a packaging layer; the rewiring layer is used for bearing at least one bare chip; the rewiring layer is arranged between the at least one bare chip and the substrate; the reinforcement structure is arranged between the rewiring layer and the substrate and comprises a dielectric layer, an interconnection line penetrating through the dielectric layer and a columnar and/or grid-shaped support structure in the dielectric layer; the interconnection line is electrically connected with the rewiring layer and the substrate, and the supporting structure is arranged around the interconnection line; the encapsulation layer fills the gap between the bare chip and the rewiring layer, and the sides of the bare chip.

Description

Chip packaging structure, preparation method thereof and electronic equipment

Technical Field

The application relates to the technical field of semiconductors, in particular to a chip packaging structure, a preparation method thereof and electronic equipment.

Background

With the continuous development of semiconductor technology, the requirements for chip packaging are continuously increasing. Currently, in the chip packaging process, the bare chip and the substrate are often interconnected using a rewiring layer (redistribution layer, RDL). As shown in fig. 1, a first soldering component is disposed between the rewiring layer and the substrate, a second soldering component is disposed between the rewiring layer and the bare chip, electrical connection between the rewiring layer and the substrate is achieved through the first soldering component, electrical connection between the rewiring layer and the bare chip is achieved through the second soldering component, and further interconnection between the bare chip and the substrate is achieved through the rewiring layer. During the chip packaging process, as shown in fig. 1, the packaging layer may also be filled between the bare chip and the rewiring layer, as well as the sides of the bare chip.

However, since the materials such as the substrate, the bare chip, the rewiring layer, the packaging layer and the like in the chip packaging structure are different, the thermal expansion coefficients are different, but the thermal expansion coefficients of the substrate are generally larger than those of other components in the chip packaging structure, so that the substrate generates larger internal stress relative to the other components in the chip packaging structure, and larger deformation occurs, thus causing the problems of delamination of the rewiring layer, cracking of the packaging layer between two adjacent bare chips and the like.

Disclosure of Invention

The embodiment of the application provides a chip packaging structure, a preparation method thereof and electronic equipment, and can solve the problems of layering of a rewiring layer and cracking of a packaging layer between two adjacent bare chips in the chip packaging structure.

In a first aspect, a chip package structure is provided, the chip package structure including a substrate, at least one bare chip, a rewiring layer, a reinforcement structure, and a package layer; the rewiring layer is used for bearing at least one bare chip and is electrically connected with the bare chip; the rewiring layer is arranged between the at least one bare chip and the substrate; the reinforcement structure is arranged between the rewiring layer and the substrate and comprises a dielectric layer, an interconnection line penetrating through the dielectric layer and a columnar and/or grid-shaped support structure in the dielectric layer; the interconnection line is electrically connected with the substrate and the rewiring layer; the support structure is arranged around the interconnection line; the encapsulation layer fills the gap between the bare chip and the rewiring layer, and the sides of the bare chip. Since the chip packaging structure comprises the reinforcing structure, the reinforcing structure can isolate the internal stress generated by the substrate, so that the internal stress generated by the substrate can be prevented or reduced from being transferred to the rewiring layer, and the rewiring layer is layered. In the case that the chip package structure includes a plurality of bare chips, the reinforcement structure isolates the internal stress generated by the substrate, so that the internal stress generated by the substrate can be prevented or reduced from being transferred to a gap between two adjacent bare chips, and the package layer between the two adjacent bare chips is prevented from cracking. On this basis, because the reinforcing structure comprises a medium layer and an interconnection circuit, and also comprises a columnar and/or grid-shaped supporting structure, the supporting structure can improve the strength of the reinforcing structure, further isolate the transmission of internal stress generated by the substrate, prevent the rewiring layer from layering, or prevent the packaging layer between two adjacent bare chips from cracking, thereby improving the reliability and manufacturability of the packaging of the chip packaging structure.

In a possible implementation of the first aspect, the support structure comprises a grid structure, the interconnection line being located within the grid structure. When the support structure comprises a grid structure, the strength of the support structure is high due to the fact that the strength of the grid structure is high, and then the strength of the reinforcement structure can be improved.

In a possible implementation manner of the first aspect, the reinforcement structure further includes: the grounding structure is arranged in the dielectric layer; the grounding structure is electrically connected with the grounding terminal of the substrate and the grid structure. The grounding structure is electrically connected with the grounding terminal of the substrate, and the grounding structure is electrically connected with the grid structure, so that grounding voltage can be provided for the grounding structure through the grounding terminal of the substrate, and then the grounding voltage is provided for the grid structure, so that the grid structure can also play a role in preventing mutual crosstalk between signals on the substrate and signals on the bare chip, that is, the transmission of the signals along the direction vertical to the substrate is protected in a grounding mode, and the electrical performance is improved. In addition, the mesh structure may also function to prevent crosstalk of signals between the interconnect lines.

In a possible implementation of the first aspect, the support structure comprises a plurality of support columns. The structure of the support structure may be set as desired, so that flexibility in the design of the support structure may be mentioned.

In a possible implementation manner of the first aspect, the support structure penetrates through the dielectric layer. Because the interconnect lines extend through the dielectric layer, the interconnect lines and the support structure can be fabricated simultaneously when the support structure also extends through the dielectric layer.

In a possible implementation manner of the first aspect, a material of the dielectric layer is an organic material, and a material of the encapsulation layer is an organic material. Because the material of the packaging layer and the material of the dielectric layer are both organic materials, the thermal expansion coefficient of the packaging layer is not greatly different from that of the dielectric layer, and therefore the internal stress generated by the thermal expansion of the dielectric layer and the internal stress generated by the thermal expansion of the packaging layer can be mutually counteracted, so that the thermal stress mismatch of the packaging layer and the dielectric layer can be relieved, the delamination of a rewiring layer arranged between the packaging layer and a reinforcing structure and caused by the internal stress generated by the thermal expansion of the packaging layer and the dielectric layer can be avoided, or the cracking of the packaging layer between two adjacent bare chips can be prevented.

In one possible implementation of the first aspect, the encapsulation layer comprises a first underfill and a plastic layer; the first underfill is filled in a gap between the bare chip and the rewiring layer, and the plastic sealing layer is filled on the side face of the bare chip; the material of the dielectric layer is the same as that of the first underfill or plastic layer. If the material of the dielectric layer is the same as that of the first underfill, the thermal expansion coefficient of the dielectric layer is the same as that of the first underfill, so that the thermal stress mismatch of the dielectric layer and the first underfill can be relieved, the internal stress of the dielectric layer due to thermal expansion and the internal stress of the first underfill due to thermal expansion can be more effectively offset, and under the condition that the volume of the dielectric layer is the same as that of the first underfill, the internal stress of the dielectric layer due to thermal expansion and the internal stress of the first underfill can be even completely offset, so that the delamination of a rewiring layer arranged between the first underfill and the dielectric layer due to the internal stress of the first underfill and the internal stress of the dielectric layer due to thermal expansion can be more effectively avoided, or the plastic sealing layer between two adjacent bare chips can be more effectively prevented from cracking. Similarly, if the material of the dielectric layer is the same as that of the plastic sealing layer, the thermal expansion coefficient of the dielectric layer is the same as that of the plastic sealing layer, so that the thermal stress mismatch of the dielectric layer and the plastic sealing layer can be relieved, and delamination of a rewiring layer arranged between the plastic sealing layer and the dielectric layer and caused by internal stress generated by thermal expansion of the plastic sealing layer and the dielectric layer can be more effectively avoided, or cracking of the plastic sealing layer between two adjacent bare chips can be more effectively prevented.

In a possible implementation manner of the first aspect, the material of the dielectric layer includes one or more of epoxy resin, silica gel and polyimide.

In a possible implementation manner of the first aspect, the rewiring layer includes at least one metal line layer and an insulating layer, and the at least one metal line layer is located in the insulating layer; wherein the material of the insulating layer is an organic material or an inorganic material. The material of the insulating layer may be selected as an organic material or an inorganic material as needed, so that the design flexibility of the insulating layer may be improved.

In a possible implementation manner of the first aspect, the chip package structure further includes: and the second underfill is filled in the gap between the reinforcing structure and the substrate and overflows to the side surface of the packaging layer. The second underfill may serve to secure the bare chip encapsulated by the encapsulation layer, as well as the rewiring layer, dielectric layer, etc. to the substrate.

In a second aspect, a method for manufacturing a chip package structure is provided, where the method for manufacturing a chip package structure includes: firstly, forming a rewiring layer on a first temporary carrier plate; next, binding at least one bare chip on the rewiring layer, wherein the bare chip is electrically connected with the rewiring layer; next, filling the encapsulation layer to encapsulate the at least one bare chip, i.e., filling the encapsulation layer between the bare chip and the rewiring layer, the side of the bare chip, and the surface of the bare chip away from the first temporary carrier; removing the first temporary carrier plate to expose the rewiring layer; next, forming a reinforcing structure on the rewiring layer; the reinforcement structure comprises a dielectric layer and an interconnection line; the interconnection line penetrates through the dielectric layer and is electrically connected with the rewiring layer; next, binding the reinforcing structure with the substrate; the interconnection circuit is electrically connected with the substrate. The chip packaging structure prepared by the preparation method of the chip packaging structure comprises the reinforcing structure, and the reinforcing structure can isolate the internal stress generated by the substrate, so that the internal stress generated by the substrate is prevented or reduced from being transferred to the rewiring layer, and the rewiring layer is layered. In the case that the chip package structure includes a plurality of bare chips, the reinforcement structure isolates the internal stress generated by the substrate, so that the internal stress generated by the substrate can be prevented or reduced from being transferred to a gap between two adjacent bare chips, and the package layer between the two adjacent bare chips is prevented from cracking.

In a possible implementation manner of the second aspect, the reinforcement structure further includes: the support structure is arranged in the dielectric layer; the support structure is disposed about the interconnect line. The supporting structure can improve the strength of the reinforcing structure, further isolate the transmission of internal stress generated by the substrate, prevent the rewiring layer from layering, or prevent the packaging layer between two adjacent bare chips from cracking, thereby improving the reliability and manufacturability of the packaging of the chip packaging structure.

In a possible implementation of the second aspect, the support structure comprises a grid structure; the reinforcing structure further includes: the grounding structure is arranged in the dielectric layer and is electrically connected with the grounding terminal of the substrate and the grid structure. The grounding structure is electrically connected with the grounding terminal of the substrate, and the grounding structure is electrically connected with the grid structure, so that grounding voltage can be provided for the grounding structure through the grounding terminal of the substrate, and then the grounding voltage is provided for the grid structure, so that the grid structure can also play a role in preventing mutual crosstalk between signals on the substrate and signals on the bare chip, that is, the transmission of the signals along the direction vertical to the substrate is protected in a grounding mode, and the electrical performance is improved. In addition, the mesh structure may also function to prevent crosstalk of signals between the interconnect lines.

In one possible implementation manner of the second aspect, forming a reinforcing structure on the rewiring layer includes: firstly, forming an interconnection line on a rewiring layer, wherein the interconnection line is electrically connected with the rewiring layer; next, forming a dielectric layer on the interconnection line, the dielectric layer covering the interconnection line; next, the dielectric layer is thinned, exposing the interconnect lines. In the case that the material of the dielectric layer is an organic material, the interconnect line may be formed first according to the method, and then the dielectric layer may be formed.

In one possible implementation manner of the second aspect, after the encapsulation layer is filled between the bare chip and the rewiring layer, on a side surface of the bare chip, and on a surface of the bare chip away from the first temporary carrier, and before the first temporary carrier is removed, the preparation method further includes: and thinning the packaging layer to expose the surface of the bare chip far away from the first temporary carrier plate. The packaging layer is thinned to prevent the thickness of the packaging layer from being too thick to influence the heat dissipation performance of the finally formed chip packaging structure.

In one possible implementation manner of the second aspect, after the thinning of the encapsulation layer and before the removing of the first temporary carrier, the preparation method further includes: and forming a second temporary carrier plate on one side of the bare chip far away from the rewiring layer, wherein the second temporary carrier plate is fixedly connected with the bare chip. The second temporary carrier serves to prevent warpage of the bare chip and the rewiring layer after removal of the first temporary carrier.

In one possible embodiment of the second aspect, after the reinforcing structure is formed on the rewiring layer, before the reinforcing structure is bound to the substrate, the preparation method further includes: and removing the second temporary carrier plate. If the second temporary carrier is not removed, the heat dissipation performance of the finally formed chip package structure is affected.

In one possible embodiment of the second aspect, after forming the reinforcing structure on the rewiring layer, before binding the reinforcing structure with the substrate, the preparation method further includes: firstly, forming a plurality of first welding assemblies on a reinforcing structure, wherein the first welding assemblies are electrically connected with an interconnection circuit; next, wrapping the plurality of first welding components with an adhesive tape; next, thinning the encapsulation layer to expose the surface of the bare chip away from the rewiring layer; removing the adhesive tape to expose the plurality of first welding components; binding the reinforcing structure to the substrate, including: binding the plurality of first welding assemblies with the substrate, and electrically connecting the first welding assemblies with the substrate. The adhesive tape can protect the plurality of first welding components from being damaged when the packaging layer is thinned.

In a third aspect, an electronic device is provided, which includes a printed circuit board and the chip package structure provided in the first aspect; the chip packaging structure is electrically connected with the printed circuit board. The electronic device has the same technical effects as the chip package structure provided in the first aspect, and reference may be made to the description of the first aspect, which is not repeated here.

Drawings

Fig. 1 is a schematic structural diagram of a chip package structure provided in the prior art;

fig. 2 is a schematic structural diagram of an electronic device according to an embodiment of the present application;

fig. 3 is a schematic structural diagram of a chip package structure according to an embodiment of the present application;

FIG. 4 is a schematic diagram of a rewiring layer according to an embodiment of the present application;

fig. 5a is a schematic structural diagram of a chip package structure according to another embodiment of the present application;

fig. 5b is a schematic structural diagram of a chip package structure according to another embodiment of the present application;

fig. 5c is a schematic structural diagram of a chip package structure according to another embodiment of the present application;

FIG. 6a is a schematic structural view of a reinforcing structure according to an embodiment of the present application;

FIG. 6b is a schematic structural view of a reinforcing structure according to another embodiment of the present application;

FIG. 6c is a schematic structural view of a reinforcing structure according to yet another embodiment of the present application;

fig. 7 is a schematic structural diagram of a chip package structure according to another embodiment of the present application;

FIG. 8 is a schematic structural view of a reinforcing structure according to yet another embodiment of the present application;

fig. 9 is a schematic structural diagram of a chip package structure provided in the related art;

FIG. 10 is a schematic diagram of another chip package structure according to the related art;

fig. 11 is a schematic flow chart of a method for manufacturing a chip package structure according to an embodiment of the present application;

fig. 12 is a schematic structural diagram in the process of manufacturing a chip package structure according to an embodiment of the present application;

fig. 13 is a schematic diagram of a second structure in the process of manufacturing a chip package structure according to an embodiment of the present disclosure;

fig. 14 is a schematic diagram III of a chip package structure in the manufacturing process according to an embodiment of the present application;

fig. 15 is a schematic structural diagram in the process of manufacturing a chip package structure according to an embodiment of the present application;

fig. 16 is a schematic diagram of a chip package structure according to an embodiment of the present disclosure in a manufacturing process;

Fig. 17 is a schematic diagram sixth in the manufacturing process of a chip package structure according to an embodiment of the present application;

fig. 18 is a schematic diagram seventh in the preparation process of a chip package structure according to an embodiment of the present application;

fig. 19 is a schematic structural diagram eight in a process of manufacturing a chip package structure according to an embodiment of the present application;

fig. 20 is a schematic structural diagram nine in a process of manufacturing a chip package structure according to an embodiment of the present application;

fig. 21 is a schematic structural view of a chip package structure according to an embodiment of the present disclosure during a manufacturing process;

fig. 22 is a schematic diagram eleven in the manufacturing process of a chip package structure according to an embodiment of the present application;

fig. 23 is a schematic diagram showing a structure of a chip package structure in the manufacturing process according to an embodiment of the present disclosure;

fig. 24 is a schematic diagram of a chip package structure according to an embodiment of the present disclosure in the manufacturing process;

fig. 25 is a schematic diagram fourteen structural views during a manufacturing process of a chip package structure according to an embodiment of the present disclosure;

fig. 26 is a schematic structural diagram fifteen in a process of manufacturing a chip package structure according to an embodiment of the present application;

Fig. 27 is a schematic flow chart of a method for manufacturing a chip package structure according to another embodiment of the present application;

fig. 28 is a sixteen schematic structural diagrams during the manufacturing process of a chip package structure according to an embodiment of the present disclosure;

fig. 29 is a schematic diagram seventeen structures in a manufacturing process of a chip package structure according to an embodiment of the present application;

fig. 30 is a schematic structural diagram eighteenth of a chip package structure according to an embodiment of the present disclosure in a manufacturing process;

fig. 31 is a schematic structural diagram nineteenth during a manufacturing process of a chip package structure according to an embodiment of the present application;

fig. 32 is a schematic diagram showing a structure of a chip package structure in the manufacturing process according to an embodiment of the present application;

fig. 33 is a schematic structural diagram twenty-one in a process of manufacturing a chip package structure according to an embodiment of the present disclosure;

fig. 34 is a schematic structural diagram of a chip package structure according to an embodiment of the present disclosure in the preparation process;

fig. 35 is a schematic diagram of twenty-third in the manufacturing process of a chip package structure according to an embodiment of the present disclosure;

fig. 36 is a twenty-four structural schematic diagram of a chip package structure in the manufacturing process according to an embodiment of the present disclosure;

Fig. 37 is a schematic diagram twenty-fifth structural diagram in a manufacturing process of a chip package structure according to an embodiment of the present application;

fig. 38 is a schematic diagram of a manufacturing process of a chip package structure according to an embodiment of the present disclosure;

fig. 39 is a twenty-seventh structural diagram of a chip package structure in the manufacturing process according to an embodiment of the present disclosure;

fig. 40 is a schematic diagram of a manufacturing process of a chip package structure according to an embodiment of the present application.

Reference numerals: 1-an electronic device; 10-a chip packaging structure; 11-cover plate; 12-a display screen; 13-a middle frame; 14-a rear shell; 101-a substrate; 102-reinforcing the structure; 103-bare chip; 104-rewiring layer; 105-packaging layer; 106-a second underfill; 107-a second welding assembly; 108-a first welding assembly; 109-a first temporary carrier plate; 110-a second temporary carrier; 111-bonding glue; 112-adhesive tape; 131-a carrier plate; 132-frame; 1021-a dielectric layer; 1022-interconnect lines; 1023-support structure; 1023 a-support columns; 1023 b-mesh structure; 1024-ground structure; 1041-a metal line layer; 1042-an insulating layer; 1051-a first underfill; 1052-plastic sealing layer; 1071-second bump; 1072-second solder balls; 1081-a first bump; 1082-first solder balls.

Detailed Description

The following description of the technical solutions in the embodiments of the present application will be made with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, but not all embodiments.

Hereinafter, the terms "first," "second," and the like are used for descriptive convenience only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first", "a second", etc. may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

In the embodiments herein, unless explicitly specified and limited otherwise, the term "electrically connected" may be either a direct electrical connection or an indirect electrical connection via an intermediary.

In the embodiments of the present application, words such as "exemplary" or "such as" are used to mean serving as examples, illustrations, or descriptions. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.

In the embodiments of the present application, directions of directions such as up, down, left, right, front, and rear, etc., are used to explain the structure and movement of the different components in the present application are relative. These indications are appropriate when the component is in the position shown in the figures. However, if the description of the position of the element changes, then these directional indications will also change accordingly.

Embodiments of the present application provide an electronic device, which may be, for example, a mobile phone (mobile phone), a tablet computer (pad), a personal digital assistant (personal digital assistant, PDA), a television, an intelligent wearable product (e.g., a smart watch, a smart bracelet), a Virtual Reality (VR) terminal device, an augmented reality (augmented reality, AR) terminal device, a rechargeable household small-sized appliance (e.g., a soymilk machine, a floor sweeping robot), an unmanned plane, a radar, an aerospace device, a vehicle-mounted device, and other different types of user devices or terminal devices, and the specific forms of the electronic device are not particularly limited in the embodiments of the present application.

For convenience of explanation, an electronic device is taken as an example of a mobile phone. As shown in fig. 2, the electronic device 1 mainly includes a cover plate 11, a display screen 12, a middle frame 13, and a rear case 14. The rear shell 14 and the display screen 12 are respectively positioned at two sides of the middle frame 13, the middle frame 13 and the display screen 12 are arranged in the rear shell 14, the cover plate 11 is arranged at one side of the display screen 12 far away from the middle frame 13, and the display surface of the display screen 12 faces the cover plate 11.

The display 12 may be a liquid crystal display (liquid crystal display, LCD), in which case the liquid crystal display includes a liquid crystal display panel and a backlight module, the liquid crystal display panel is disposed between the cover plate 11 and the backlight module, and the backlight module is used to provide a light source for the liquid crystal display panel. The display 12 may also be an organic light emitting diode (organic light emitting diode, OLED) display. The OLED display screen is a self-luminous display screen, so that a backlight module is not required to be arranged.

The middle frame 13 includes a supporting plate 131 and a frame 132 surrounding the supporting plate 131. Printed circuit board (printed circuit boards, PCB), battery, camera, etc. electronic components in electronic device 1 may be disposed on carrier plate 131.

The electronic device 1 may further include a System On Chip (SOC), a chip package, etc. disposed on a PCB, where the PCB is configured to carry and electrically connect the SOC, the chip package, etc.

The above-described chip package structure includes packaging a single chip, and packaging a plurality of chips, that is, chip-on-package (chip). Taking chip encapsulation as an example, the chip encapsulation is an advanced encapsulation technology based on chip modularized design and integrated after completion. As chip technology goes to the end of moore's law, the demand for increased integration is not changed, and the bottleneck of completing all functions in a single chip is increased. The chip is modularized and functionalized, and different special chips are integrated on the package in a chip sealing mode after the special chips are developed, so that the development difficulty of the chip is greatly reduced, the commercial mode of an industrial chain is enriched, and the chip processes and the productivity of different process nodes (namely the cost) are fully reused, so that the chip industry has new vitality and vitality when the moore's law goes to the end stage. As the integration level of chips becomes higher, the modular design is also becoming more abundant, and the demands for high-density integrated packaging schemes (heterogeneous integration) of chips with different modular designs are increasing. How to complete high-density, high-speed and high-reliability interconnection modes of chips with different functions, different manufacturing processes and even different structures and materials on the same package becomes a challenge for chip encapsulation practitioners.

The embodiment of the present application provides a chip package structure, which may be applied to the electronic device 1 described above, and as shown in fig. 3, the chip package structure 10 includes a substrate (may also be referred to as a package substrate) 101, a reinforcement structure 102, at least one bare chip (die) 103, a rewiring layer 104, and a packaging layer 105.

In the case where the chip package structure 10 is applied to the electronic device 1, the substrate 101 may be disposed on and electrically connected with a PCB in the electronic device 1.

In the embodiment of the present application, the chip package structure 10 may include one bare chip 103, that is, package one bare chip 103; a plurality of die 103 may also be included, i.e., the plurality of die 103 are packaged, and the plurality of die 103 may be die 103 having different functions.

The re-wiring layer 104 is configured to carry the at least one die 103, the re-wiring layer 104 is disposed between the at least one die 103 and the substrate (substrate) 101, the re-wiring layer 104 is electrically connected to the die 103 and the substrate 101, and the re-wiring layer 104 is configured to electrically connect the die 103 and the substrate 101.

As shown in fig. 4, the re-wiring layer 104 includes at least one metal line layer 1041 and an insulating layer 1042, where the at least one metal line layer 1041 is located in the insulating layer 1042. The rewiring layer 104 is electrically connected to the bare chip 103, that is, the metal line layer 1041 in the rewiring layer 104 is electrically connected to the bare chip 103.

Here, the rewiring layer 104 may include one metal line layer 1041, or may include a plurality of metal line layers 1041, and fig. 4 is a schematic diagram illustrating that the rewiring layer 104 includes a plurality of metal line layers 1041. In the case where the rewiring layer 104 includes a plurality of metal line layers 1041, adjacent two metal line layers 1041 are spaced apart by an insulating layer 1042 and are electrically connected together by vias on the insulating layer 1042 located between the adjacent two metal line layers 1041.

The material of the metal line layer 1041 may include, for example, one or more of copper (Cu), aluminum (Al), nickel (Ni), gold (Au), silver (Ag), titanium (Ti), and the like. Copper has found wide application as a low cost, high reliability, low contact resistance mature process material for the metal line layer 1041 in the rewiring layer 104.

The material of the insulating layer 1042 may be an organic material, in which case the organic material may include one or more of silica gel and polyimide; the material of the insulating layer 1042 may also be an inorganic (inorganic) material, in which case the inorganic material may include, for example, one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiOxNy).

On this basis, in some examples, as shown in fig. 3, the chip package structure 10 further includes a plurality of second solder assemblies 107, where the plurality of second solder assemblies 107 are disposed between the rewiring layer 104 and the bare chip 103, and the plurality of second solder assemblies 107 are electrically connected to the rewiring layer 104 and the bare chip 103, respectively, for implementing electrical connection between the rewiring layer 104 and the bare chip 103. The second solder elements 107 are electrically connected to the rewiring layer 104, i.e., the second solder elements 107 are electrically connected to the metal line layer 1041 in the rewiring layer 104.

Referring to fig. 3, the second bonding assembly 107 may include, for example, a second bump 1071 and a second solder ball 1072 in contact with the second bump 1071. Here, it may be that the second bump 1071 is in contact with the bare chip 103, and the second solder ball 1072 is in contact with the metal line layer 1041 in the rewiring layer 104.

In this application, "solder ball" is only a term that is commonly used, and in actual products, "solder ball" is not necessarily spherical.

The second bump 1071 may be, for example, an under bump metal pad (UBM pad) or a copper pillar (Cu hiller).

The reinforcement structure 102 is disposed between the rewiring layer 104 and the substrate 101, and the reinforcement structure 102 includes a dielectric layer 1021, an interconnection line 1022 penetrating through the dielectric layer 1021, and a columnar and/or grid-shaped support structure 1023 disposed in the dielectric layer; interconnect lines 1022 are electrically connected to substrate 101 and rewiring layer 104, and support structure 1023 is disposed around interconnect lines 1022. The interconnect line 1022 is electrically connected to the re-wiring layer 104 and the substrate 101, and the interconnect line 1022 is electrically connected to the re-wiring layer 104, i.e., the interconnect line 1022 is electrically connected to the metal line layer 1041 in the re-wiring layer 104.

In some examples, as shown in fig. 3, the chip package structure 10 further includes a plurality of first solder assemblies 108, where the plurality of first solder assemblies 108 are disposed between the substrate 101 and the reinforcing structure 102, and the plurality of first solder assemblies 108 are electrically connected to the substrate 101 and the interconnection 1022, respectively, for electrically connecting the substrate 101 and the interconnection 1022.

Referring to fig. 3, the first bonding assembly 108 may include, for example, a first bump 1081 and a first solder ball 1082 in contact with the first bump 1081. Here, the first bump 1081 may be in contact with the interconnect line 1022, and the first solder ball 1082 may be in contact with the substrate 101.

The first bump 1081 may refer to the related description of the second bump 1071, which is not described herein.

The support structure 1023 is disposed in the dielectric layer 1021, and the projection of the support structure 1023 and the interconnect 1022 on the substrate 101 has no overlapping area.

It will be appreciated that the materials of interconnect 1022 and support structure 1023 may or may not be the same. Since the support structure 1023 is mainly used for supporting, a material having a higher hardness or strength may be selected as the material of the support structure 1023 when the support structure 1023 is manufactured. In addition, the material of the supporting structure 1023 may be a conductive material or an insulating material. The interconnect line 1022 is mainly used to electrically connect the rewiring layer 104 and the substrate 101 together, so that a material having a low resistivity may be selected as the material of the interconnect line 1022 when the interconnect line 1022 is manufactured.

Here, the material of the interconnect line 1022 and the support structure 1023 may include, for example, a metal material such as Cu (copper), ti (titanium), ni (nickel), or the like.

"support structure 1023 is disposed within dielectric layer 1021," it should be understood that support structure 1023 may extend through dielectric layer 1021 as shown in FIG. 3; dielectric layer 1021 may not be penetrated. In the case that the supporting structure 1023 does not penetrate the dielectric layer 1021, as shown in fig. 5a, the supporting structure 1023 is not exposed on the surface of the dielectric layer 1021 near the substrate 101, and is not exposed on the surface of the dielectric layer 1021 near the rewiring layer 104; as shown in fig. 5b, the supporting structure 1023 may be exposed on the surface of the dielectric layer 1021 near the substrate 101, but not on the surface of the dielectric layer 1021 near the rewiring layer 104; of course, as shown in fig. 5c, the support structure 1023 may be exposed on the surface of the dielectric layer 1021 near the rewiring layer 104, but not exposed on the surface of the dielectric layer 1021 near the substrate 101.

It will be appreciated that the interconnect lines 1022 and the support structures 1023 in the reinforcing structure 102 may be fabricated simultaneously or separately.

Here, the number of the interconnect lines 1022 may be set as necessary.

In some examples, as shown in fig. 6a and 6b, the interconnect line 1022 is a columnar structure, which may be, for example, a cylinder, a triangular prism, a quadrangular prism, a pentagonal prism, or the like.

On this basis, the reinforcement structure 102 comprising the columnar and/or grid-like support structure 1023 may comprise the following: in some examples, as shown in fig. 6a, the support structure 1023 described above includes a plurality of support columns 1023a. The shape of the support column 1023a may be, for example, a cylinder, a triangular prism, a quadrangular prism, a pentagonal prism, or the like.

In other examples, as shown in fig. 6b, the support structure 1023 may be provided in the form of a grid structure 1023b, with the interconnect 1022 located within the grid structure 1023 b.

In still other embodiments, as shown in fig. 6c, the support structure 1023 includes a grid structure 1023b and a plurality of support columns 1023a, with the interconnect lines 1022 located within the grid structure 1023 b. The plurality of support columns 1023a may be located within the grid structure 1023b or may be located outside the grid structure 1023 b. In addition, the plurality of support columns 1023a may or may not be electrically connected to the grid structure 1023 b. Fig. 6c illustrates a plurality of support columns 1023a positioned within the grid structure 1023b, wherein the support columns 1023a are not electrically connected to the grid structure 1023 b. When the supporting structure 1023 includes the mesh structure 1023b, since the strength of the mesh structure 1023b is large, the strength of the supporting structure 1023 is large, and thus the strength of the reinforcing structure 102 can be improved.

Based on the above, where the support structure 1023 includes a grid structure 1023b, in some examples, as shown in fig. 7, the above-described reinforcing structure 102 may further include: a grounding structure 1024, where the grounding structure 1024 is disposed in the dielectric layer 1021; the grounding structure 1024 is electrically connected to the grounding terminal of the substrate 101, as shown in fig. 8, and the grounding structure 1024 is also electrically connected to the grid structure 1023 b.

Here, the grounding structure 1024 may be electrically connected to the first soldering assembly 108 disposed between the reinforcing structure 102 and the substrate 101, and the electrical connection between the grounding structure 1024 and the grounding terminal of the substrate 101 is achieved through the first soldering assembly 108.

The material of the grounding structure 1024 and the material of the interconnect line 1022 may be the same or different.

In some examples, the ground structure 1024 is a columnar structure that may be, for example, a cylinder, a triangular prism, a quadrangular prism, a pentagonal prism, or the like.

The grounding structure 1024 may or may not penetrate the dielectric layer 1021. In the case that the grounding structure 1024 does not penetrate through the dielectric layer 1021, since the grounding structure 1024 needs to be electrically connected to the grounding terminal of the substrate 101, the grounding structure 1024 is exposed on the surface of the dielectric layer 1021 near the substrate 101, and is not exposed on the surface of the dielectric layer 1021 near the rewiring layer 104.

It is understood that the grounding structure 1024 may or may not be electrically connected to the rewiring layer 104.

Since the grounding structure 1024 is electrically connected with the grounding terminal of the substrate 101, and the grounding structure 1024 is electrically connected with the grid structure 1023b, the grounding voltage can be provided to the grounding structure 1024 through the grounding terminal of the substrate 101, and then the grounding voltage is provided to the grid structure 1023b, so that the grid structure 1023b can also play a role in preventing the mutual crosstalk between the signal on the substrate 101 and the signal on the bare chip 103, that is to say, the transmission of the signal along the direction perpendicular to the substrate is protected by the grounding manner, and the electrical performance is improved. In addition, the mesh structure 1023b may also function to prevent crosstalk of signals between the interconnect lines 1022.

The encapsulation layer 105 may cover the at least one die 103, i.e., the encapsulation layer 105 fills the gap between the die 103 and the rewiring layer 104, as well as the sides of the die 103. The encapsulation layer 105 is used to encapsulate the bare chip 103.

In some examples, as shown in fig. 7, encapsulation layer 105 includes a first underfill adhesive 1051 and a plastic layer 1052; a first underfill 1051 fills in the gap between the die 103 and the rewiring layer 104, and a plastic layer 1052 fills in the sides of the die 103.

Here, the material of the plastic layer 1052 and the material of the first underfill 1051 are generally organic materials, and the material of the plastic layer 1052 may be, for example, an epoxy adhesive (epoxy molding compound, EMC). The material of the first underfill 1051 may be, for example, a thermosetting adhesive or an ultraviolet curable adhesive.

In the chip package structure 10, since the materials of the substrate 101, the bare chip 103 and the package layer 105 are different, the thermal expansion coefficients of the substrate 101, the bare chip 103 and the package layer 105 are different, and the thermal expansion coefficient of the substrate 101 is larger than that of the bare chip 103, the package layer 105 and the like, so that the substrate 101 generates larger internal stress relative to the bare chip 103, the package layer 105 and the like, and larger deformation occurs, and the internal stress generated by the substrate 101 tears the structure on the first welding component 108 through the first welding component 108. In the embodiment of the present application, since the chip package structure 10 includes the reinforcing structure 102, the reinforcing structure 102 can isolate the internal stress generated by the substrate 101, so that the internal stress generated by the substrate 101 can be prevented or reduced from being transferred to the rewiring layer 104, resulting in delamination of the rewiring layer 104. In the case where the chip package structure 10 includes a plurality of bare chips 103, the reinforcement structure 102 isolates the internal stress generated by the substrate 101, so that it is possible to avoid or reduce the transmission of the internal stress generated by the substrate 101 to the gap between the adjacent two bare chips 103, resulting in cracking of the package layer 105 between the adjacent two bare chips 103. On this basis, since the reinforcing structure 102 includes the columnar and/or grid-shaped supporting structure 1023 in addition to the dielectric layer 1021 and the interconnection line 1022, the supporting structure 1023 can improve the strength of the reinforcing structure 102, further isolate the transmission of internal stress generated by the substrate 101, prevent the rewiring layer 104 from layering, or prevent the package layer 105 between two adjacent bare chips 103 from cracking, thereby improving the reliability and manufacturability of the package of the chip package structure 10.

In some examples, the material of the dielectric layer 1021 in the reinforcement structure 102 is an inorganic material, for example, the material of the dielectric layer 1021 may include one or more of silicon (Si), silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy).

In other examples, the material of the dielectric layer 1021 in the reinforcement structure 102 is an organic material. For example, the material of the dielectric layer 1021 may be a molding (molding) material. The molding material may include, for example, one or more of epoxy, silicone, polyimide.

In the case that the material of the encapsulation layer 105 is an organic material, when the material of the dielectric layer 1021 is an organic material, since the material of the encapsulation layer 105 and the material of the dielectric layer 1021 are both organic materials, the thermal expansion coefficient of the encapsulation layer 105 is not greatly different from that of the dielectric layer 1021, and thus the internal stress generated by thermal expansion of the dielectric layer 1021 and the internal stress generated by thermal expansion of the encapsulation layer 105 can cancel each other, so that the thermal stress mismatch of the encapsulation layer 105 and the dielectric layer 1021 can be relieved, delamination of the rewiring layer 104 disposed between the encapsulation layer 105 and the reinforcing structure 102 due to the internal stress generated by thermal expansion of the encapsulation layer 105 and the dielectric layer 1021 can be avoided, or cracking of the encapsulation layer 105 between two adjacent bare chips 103 can be prevented.

Where encapsulation layer 105 includes first underfill 1051 and plastic layer 1052, in some examples, the material of dielectric layer 1021 is the same as the material of first underfill 1051 or plastic layer 1052.

If the material of the dielectric layer 1021 is the same as that of the first underfill 1051, the thermal expansion coefficient of the dielectric layer 1021 is the same as that of the first underfill 1051, so that the thermal stress mismatch between the dielectric layer 1021 and the first underfill 1051 can be relieved, the internal stress generated by thermal expansion of the dielectric layer 1021 and the internal stress generated by thermal expansion of the first underfill 1051 can be more effectively offset, and the internal stress generated by thermal expansion of the dielectric layer 1021 and the internal stress generated by thermal expansion of the first underfill 1051 can even be completely offset under the condition that the volume of the dielectric layer 1021 and the volume of the first underfill 1051 are the same, so that delamination of the re-wiring layer 104 arranged between the first underfill 1051 and the dielectric layer 1021 due to the internal stress generated by thermal expansion of the first underfill 1051 can be more effectively avoided, or cracking of the plastic sealing layer 1052 between two adjacent bare chips 103 can be more effectively prevented. Similarly, if the material of the dielectric layer 1021 is the same as that of the molding layer 1052, the thermal expansion coefficient of the dielectric layer 1021 is the same as that of the molding layer 1052, so that the thermal stress mismatch between the dielectric layer 1021 and the molding layer 1052 can be relieved, and delamination of the rewiring layer 104 disposed between the molding layer 1052 and the dielectric layer 1021 due to internal stress generated by thermal expansion of the molding layer 1052 and the dielectric layer 1021 can be more effectively avoided, or cracking of the molding layer 1052 between two adjacent bare chips 103 can be more effectively prevented.

The related art provides a chip package structure 10, as shown in fig. 9, in order to avoid the problem that the re-wiring layer 104 is layered due to internal stress generated by the substrate 101, or the package layer 105 between two adjacent bare chips 103 is cracked, etc., therefore, a silicon interposer (si interposer) is added between the re-wiring layer 104 and the substrate 101 in the chip package structure 10 provided by the related art, and the silicon interposer naturally has a mature process of high yield and high density interconnection based on a silicon back-end process, and the internal stress generated by the substrate 101 is counteracted by using the silicon interposer while the re-wiring layer 104 and the substrate 101 are interconnected by using the silicon interposer. However, since the thermal expansion coefficient of the silicon interposer is different from that of the encapsulation layer 105, in order to prevent the silicon interposer from being warped due to internal stress, the thickness of the silicon interposer needs to be set larger to increase the rigidity of the silicon interposer, and the larger thickness of the silicon interposer introduces a new problem. It will be appreciated that the interconnect structure is formed in an inorganic material, typically by a TSV (through silicon via ) process, that is, by first forming a via in the inorganic material and then electroplating a conductive material within the via. The interconnect structure in the interposer is formed by a TSV (through silicon via ) process and a BVR (backside via reveal, backside via exposed) process, and the increased thickness of the interposer results in increased difficulty and cost of the TSV process and the BVR process. In addition, if the thickness of the silicon interposer is set too large, the internal stress of the silicon interposer due to thermal expansion is also large, and the silicon interposer still has problems of warpage and stress reliability.

The related art also provides a chip package structure 10, as shown in fig. 10, in which a first re-wiring layer 104a and a second re-wiring layer 104b are provided between a bare chip 103 and a substrate 101, the first re-wiring layer 104a and the second re-wiring layer 104b are provided side by side in a direction parallel to the substrate 101 with a gap therebetween. The material of the insulating layer in the first rewiring layer 104a is an organic material, and the material of the insulating layer in the second rewiring layer 104b is an inorganic material. In order to avoid the problem that the re-wiring layer 104 is layered due to the internal stress generated by the substrate 101, or the problem that the packaging layer 105 between two adjacent bare chips 103 is cracked, a silicon adapter plate can be added between the re-wiring layer and the substrate 101, and the internal stress generated by the substrate 101 is counteracted by using the silicon adapter plate, but on one hand, because the material of the silicon adapter plate is an inorganic material, the material of the packaging layer is an organic material, and the thermal expansion coefficients of the organic material and the inorganic material are greatly different, and larger internal stress can be generated; on the other hand, since the material of the insulating layer in the first rewiring layer 104a is an organic material, and the flexibility of the organic material is better, and the material of the insulating layer in the second rewiring layer 104b is an inorganic material, and the inorganic material is easily broken with respect to the organic material, the chip package structure 10 provided in the related art only increases the silicon interposer between the second rewiring layer 104b and the substrate 101, so that the arrangement area of the silicon interposer can be reduced, and further, the difference between the internal stress of the silicon interposer due to thermal expansion and the internal stress of the package layer 105 due to thermal expansion can be reduced, and the internal stress of the substrate 101 can be offset by using the silicon interposer. Although in this related art, the silicon interposer is added only between the second rewiring layer 104b and the substrate 101, also, in order to prevent the silicon interposer from being warped due to internal stress, it is necessary to set the thickness of the silicon interposer to be large in order to increase the rigidity of the silicon interposer. The larger thickness of the silicon interposer may result in increased process difficulty and cost when the TSV process and the BVR process are used to form the interconnect structure in the silicon interposer.

Compared to the two related arts described above, since the chip package structure 10 provided in the embodiment of the present application includes the reinforcing structure 102, the reinforcing structure 102 can isolate the internal stress generated by the substrate 101, so that the internal stress generated by the substrate 101 can be prevented or reduced from being transferred to the rewiring layer 104, resulting in delamination of the rewiring layer 104; the problem of cracking of the encapsulation layer 105 between the adjacent two die 103 caused by the transfer of internal stress generated by the substrate 101 to the gap between the adjacent two die 103 can also be avoided or reduced. On this basis, it is understood that, unlike the formation of an interconnect structure in an inorganic material, which requires the use of a TSV process, the interconnect structure may be formed first and then deposited in an organic material without using a TSV process to form the interconnect structure in the organic material. Based on this, in the case that the material of the dielectric layer 1021 in the reinforcing structure 102 is an organic material, the interconnect 1022, the supporting structure 1023, and the grounding structure 1024 in the reinforcing structure 102 may be formed first, and then the organic material is deposited, so as to form the reinforcing structure 102, so that the manufacturing process of the reinforcing structure 102 may be simplified, and the production cost of the chip package structure 10 may be reduced.

Based on the above, in some examples, as shown in fig. 7, the chip package structure 10 further includes a second underfill 106, where the second underfill 106 fills in the gap between the reinforcing structure 102 and the substrate 101 and overflows to the side of the package layer 105.

Here, the material of the second underfill 106 may be, for example, a thermosetting adhesive or an ultraviolet curable adhesive. In addition, the material of first underfill 1051 and the material of second underfill 106 may be the same or different.

It is understood that the second underfill 106 may function to fix the bare chip 103 encapsulated by the encapsulation layer 105, and the rewiring layer 104, the dielectric layer 102, and the like to the substrate 101.

The embodiments of the present application also provide a method for manufacturing the chip package structure 10, by which the chip package structure 10 can be manufactured, and the method for manufacturing the chip package structure 10 is described below by way of example in several specific embodiments.

Example 1

As shown in fig. 11, the method for manufacturing the chip package structure 10 includes the following steps:

s10, as shown in fig. 12, the rewiring layer 104 is formed on the first temporary carrier 109.

The first temporary carrier 109 may be, for example, glass (glass), stainless steel, or a silicon substrate.

In addition, the structure of the rewiring layer 104 may be referred to above, and will not be described here. The material of the insulating layer in the rewiring layer 104 may be an organic material or an inorganic material.

S11, as shown in fig. 13, at least one bare chip 103 is bound (bond) on the rewiring layer 104, and the bare chip 103 is electrically connected to the rewiring layer 104.

Step S11 may include, for example:

first, a second bump 1071 is formed on the bare chip 103, and the second bump 1071 is electrically connected to the bare chip 103.

Next, second solder balls 1072 are formed on the second bumps 1071; the second bump 1071 and the second solder ball 1072 constitute a second solder assembly 107.

Next, the second solder ball 1072 is soldered to the rewiring layer 104 to achieve bonding of the bare chip 103 to the rewiring layer 104. It is understood that "the second solder ball 1072 is soldered to the rewiring layer 104" means that the second solder ball 1072 is soldered to the metal line layer 1041 in the rewiring layer 104.

It is understood that one die 103 may be bound to the rewiring layer 104, or a plurality of dies 103 may be bound to the rewiring layer 104.

S12, filling the encapsulation layer 105 to encapsulate the at least one bare chip 103, that is, filling the encapsulation layer 105 between the bare chip 103 and the rewiring layer 104, on the side surface of the bare chip 103, and on the surface of the bare chip 103 away from the first temporary carrier 109.

Step S12 may include, for example:

first, as shown in fig. 14, a first underfill 1051 is filled between the bare chip 103 and the rewiring layer 104.

Next, as shown in fig. 15, a plastic layer 1052 is filled on the side of the bare chip 103 and the side of the bare chip 103 away from the first temporary carrier 109; wherein first underfill 1051 and plastic layer 1052 comprise package layer 105.

S13, as shown in fig. 16, the encapsulation layer 105 is thinned, exposing the surface of the bare chip 103 away from the first temporary carrier 109. Here, the encapsulation layer 105 is thinned, that is, the plastic layer 1052 is thinned.

It should be noted that, the encapsulation layer 105 may be thinned by one or more of grinding (polishing), chemical mechanical polishing (chemical mechanical polishing, CMP), dicing, and the like.

It will be appreciated that the thickness of the encapsulation layer 105 is reduced to prevent the thickness of the encapsulation layer 105 from being too thick to affect the heat dissipation performance of the finally formed chip package structure 10.

S14, as shown in fig. 17, a second temporary carrier 110 is formed on a side of the bare chip 103 away from the rewiring layer 104, and the second temporary carrier 110 is fixedly connected to the bare chip 103.

Step S14 may include, for example:

first, a bonding adhesive 111 is formed on a side of the bare chip 103 away from the rewiring layer 104, or the bonding adhesive 111 is formed on the second temporary carrier plate 110.

Here, the bonding adhesive 111 may be, for example, a thermosetting adhesive or an ultraviolet curable adhesive.

Next, as shown in fig. 17, the second temporary carrier 110 and the bare chip 103 are fixedly connected together by using a bonding adhesive 111.

S15, as shown in FIG. 18, removing the first temporary carrier 109 to expose the rewiring layer 104; after removing the first temporary carrier 109, the resulting structure is shown in fig. 19.

Here, the first temporary carrier plate 109 may be removed using one or more of grinding, chemical mechanical polishing, dicing, wet etching (wet etching), dry etching (dry etching), and the like.

It will be appreciated that in some examples, step S15 further includes: after the re-wiring layer 104 is exposed, the insulating layer 1042 in the re-wiring layer 104 is etched to expose the metal line layer 1041.

In step S14, the second temporary carrier 110 is formed, and the second temporary carrier 110 is used to prevent the bare chip 103 and the rewiring layer 104 from warping after the first temporary carrier 109 is removed.

S16, forming a reinforcing structure 102 on the rewiring layer 104; the reinforcing structure 102 includes a dielectric layer 1021 and interconnect lines 1022; interconnect lines 1022 extend through dielectric layer 1021, and interconnect lines 1022 are electrically connected to rewiring layer 104.

Step S16 may include, for example:

first, as shown in fig. 20, an interconnect line 1022 is formed on the rewiring layer 104, and the interconnect line 1022 is electrically connected to the rewiring layer 104.

Here, forming the interconnect line 1022 on the rewiring layer 104 may include, for example: forming a seed layer on the rewiring layer 104; forming a Photoresist (PR) layer on the seed layer, and performing processes such as mask exposure, development and the like on the photoresist layer to form a hollowed-out area; electroplating interconnection lines 1022 in the hollowed-out area; the photoresist layer is removed and other portions of the seed layer except under the interconnect lines 1022 are removed.

Next, as shown in fig. 21, a dielectric layer 1021 is formed over the interconnect line 1022, the dielectric layer 1021 covering the interconnect line 1022.

Here, the material of the dielectric layer 1021 may be, for example, a plastic molding material. The molding material may include, for example, one or more of epoxy, silicone, polyimide.

Next, as shown in fig. 22, the dielectric layer 1021 is thinned, exposing (reproducing) the interconnect line 1022.

Here, the dielectric layer 1021 may be thinned using one or more of grinding, chemical mechanical polishing, dicing, wet etching, dry etching, and the like.

S17, as shown in fig. 23, a first solder component 108 is formed on the reinforcing structure 102, and the first solder component 108 is electrically connected to the interconnection 1022.

Step S17 may include, for example:

first, as shown in fig. 23, a first bump 1081 is formed on the reinforcing structure 102, and the first bump 1081 is electrically connected to the interconnection 1022.

Next, as shown in fig. 23, a first solder ball 1082 is formed on the first bump 1081, and the first bump 1081 and the first solder ball 1082 constitute the first bonding assembly 108.

S18, as shown in fig. 24, the second temporary carrier plate 110 is removed.

In the case of fixedly connecting the second temporary carrier 110 and the bare chip 103 together by using the bonding adhesive 111, the second temporary carrier 110 may be separated from the bare chip 103 by breaking the bonding adhesive 111, thereby removing the second temporary carrier 110.

S19, as shown in FIG. 25, binding the reinforcing structure 102 and the substrate 101 together; wherein the interconnect 1021 is electrically connected to the substrate 101.

It is understood that the reinforcement structure 102 and the substrate 101 may be bonded together by the first bonding assembly 108, wherein the first solder balls 1082 in the first bonding assembly 108 are electrically connected to the substrate 101.

S20, as shown in fig. 26, a second underfill 106 is filled in the gap between the reinforcing structure 102 and the substrate 101, and the second underfill 106 overflows to the side surface of the encapsulation layer 105.

It should be noted that, step S20 is an optional step, for example, in some examples, step S20 may be omitted.

The function of the second underfill 106 may be referred to above, and will not be described here.

The chip package structure 10 shown in fig. 26 can be prepared through the above steps S10 to S20, where the chip package structure 10 includes a substrate 101, a reinforcing structure 102, at least one bare chip 103, a rewiring layer 104, a packaging layer 105, and a second underfill 106; the rewiring layer 104 is used for bearing the at least one bare chip 103, the rewiring layer 104 is arranged between the at least one bare chip 103 and the substrate 101, and the rewiring layer 104 is electrically connected with the bare chip 103 and the substrate 101; the reinforcing structure 102 is disposed between the rewiring layer 104 and the substrate 101, and the reinforcing structure 102 includes a dielectric layer 1021 and an interconnection line 1022 penetrating the dielectric layer 1021; interconnect lines 1022 are electrically connected to substrate 101 and rewiring layer 104; the encapsulation layer 105 fills the gap between the bare chip 103 and the rewiring layer 104, and the side of the bare chip 103; the second underfill 106 fills in the gap between the reinforcement structure 102 and the substrate 101 and overflows to the side of the encapsulation layer 105.

Since the chip package structure 10 manufactured according to the first embodiment includes the reinforcing structure 102, the reinforcing structure 102 can isolate the internal stress generated by the substrate 101, so that the internal stress generated by the substrate 101 can be prevented or reduced from being transferred to the rewiring layer 104, and the rewiring layer 104 is layered. In the case where the chip package structure 10 includes a plurality of bare chips 103, the reinforcement structure 102 isolates the internal stress generated by the substrate 101, so that it is possible to avoid or reduce the transmission of the internal stress generated by the substrate 101 to the gap between the adjacent two bare chips 103, resulting in cracking of the package layer 105 between the adjacent two bare chips 103.

Example two

As shown in fig. 27, the method for manufacturing the chip package structure 10 includes the steps of:

s30, as shown in fig. 12, the rewiring layer 104 is formed on the first temporary carrier 109.

It should be noted that, the step S30 may refer to the above step S10, which is not described herein.

S31, as shown in fig. 13, at least one bare chip 103 is bound (bond) on the rewiring layer 104, and the bare chip 103 is electrically connected to the rewiring layer 104.

It should be noted that, the step S31 may refer to the above step S11, and will not be described herein.

S32, as shown in fig. 14 and 15, the encapsulation layer 105 is filled to encapsulate the at least one bare chip 103, that is, the encapsulation layer 105 is filled between the bare chip 103 and the rewiring layer 104, on the side of the bare chip 103, and on the surface of the bare chip 103 away from the first temporary carrier 109.

It should be noted that, the step S32 may refer to the step S12, and will not be described herein.

S33, as shown in fig. 28, the first temporary carrier 109 is removed, exposing the rewiring layer 104.

It should be noted that, step S33 may refer to step S15, which is not described herein.

S34, forming a reinforcing structure 102 on the rewiring layer 104; the reinforcing structure 102 includes a dielectric layer 1021 and interconnect lines 1022; interconnect lines 1022 extend through dielectric layer 1021, and interconnect lines 1022 are electrically connected to rewiring layer 104.

Step S34 may include, for example:

first, as shown in fig. 29, an interconnect line 1022 is formed on the rewiring layer 104, and the interconnect line 1022 is electrically connected to the rewiring layer 104.

Next, as shown in fig. 30, a dielectric layer 1021 is formed over the interconnect line 1022, and the dielectric layer 1021 covers the interconnect line 1022.

Next, as shown in fig. 31, the dielectric layer 1021 is thinned, exposing the interconnect line 1022.

It should be noted that, the step S34 may refer to the step S16, and will not be described herein.

As shown in fig. 32, a first solder assembly 108 is formed on the reinforcing structure 102, and the first solder assembly 108 is electrically connected to the interconnection 1022.

It should be noted that, step S35 may refer to step S17, which is not described herein.

S36, as shown in fig. 33, the plurality of first welding assemblies 108 are wrapped with a tape (tape mount) 112.

Here, the adhesive tape 112 may protect the plurality of first welding components 108.

As shown in fig. 34, the encapsulation layer 105 is thinned to expose the surface of the bare chip 103 away from the rewiring layer 104.

Here, the method for thinning the encapsulation layer 105 may refer to the above step S13, and will not be described herein.

S38, as shown in fig. 24, the adhesive tape 112 is removed, exposing the plurality of first welding assemblies 108.

Here, the adhesive tape 112 may be removed by removing the adhesive tape 112 from the first welding assembly 108 by removing the adhesive tape 112 by heating, light irradiation, or the like.

S39, as shown in fig. 25, the reinforcement structure 102 is bound to the substrate 101, that is, the plurality of first welding assemblies 108 are bound to the substrate 101, and the first welding assemblies 108 are electrically connected to the substrate 101.

It should be noted that, the step S39 may refer to the step S19, and will not be described herein.

S40, as shown in fig. 26, the second underfill 106 is filled in the gap between the reinforcement structure 102 and the substrate 101, and the second underfill 106 overflows to the side surface of the encapsulation layer 105.

It should be noted that, the step S40 may refer to the above step S20, and will not be described herein.

The chip package structure 10 shown in fig. 26 may also be prepared through the steps S30 to S40, and the description of the chip package structure 10 shown in fig. 26 may refer to the first embodiment, which is not repeated here. The second embodiment has the same technical effects as the first embodiment, and reference may be made to the description of the first embodiment, which is not repeated here.

Example III

The manufacturing method of the chip package structure 10 provided in the third embodiment is different from the manufacturing method of the chip package structure 10 provided in the first embodiment in that the step S16 in the first embodiment is replaced by the step S50.

The third embodiment only describes the portions different from the first embodiment, and the same portions may refer to the first embodiment, which is not described herein.

Step S50 includes: forming a reinforcing structure 102 on the rewiring layer 104; the reinforcing structure 102 includes a dielectric layer 1021 and interconnect lines 1022; interconnect line 1022 extends through dielectric layer 1021, interconnect line 1022 is electrically connected to rewiring layer 104; the reinforcing structure 102 further includes: support structure 1023, support structure 1023 is disposed within dielectric layer 1021, and support structure 1023 is disposed around interconnect line 1022, with the projection of support structure 1023 and interconnect line 1022 onto rewiring layer 104 being free of overlapping areas.

Step S50 may include, for example:

first, as shown in fig. 35, interconnect lines 1022 and support structures 1023 are formed on the rewiring layer 104, and the interconnect lines 1022 are electrically connected to the rewiring layer 104.

Here, the supporting structure 1023 may include a plurality of supporting columns 1023a as shown in fig. 6a, or the supporting structure 1023 may be arranged in the form of a grid structure 1023b as shown in fig. 6 b; it is of course also possible that the support structure 1023 comprises a grid structure 1023b and a plurality of support columns 1023a as shown in fig. 6 c.

It should be noted that the interconnect line 1022 and the support structure 1023 may be formed at the same time; interconnect lines 1022 may be formed first, followed by support structure 1023; it is of course also possible to form the support structure 1023 first and then the interconnect 1022.

In addition, the height of the interconnect line 1022 and the height of the support structure 1023 may be the same or different.

In addition, regarding the materials of the interconnect line 1022 and the support structure 1023, reference may be made to the foregoing, and a detailed description thereof will be omitted.

Next, as shown in fig. 36, a dielectric layer 1021 is formed over the interconnect line 1022 and the support structure 1023, and the dielectric layer 1021 covers the interconnect line 1022 and the support structure 1023.

Next, as shown in fig. 37, the dielectric layer 1021 is thinned, exposing the interconnect line 1022.

The chip packaging structure 10 shown in fig. 3, fig. 5a, fig. 5b, and fig. 5c can be obtained by using the method for manufacturing the chip packaging structure 10 provided in the third embodiment. In addition to the technical effects similar to those of the first embodiment, in the third embodiment, since the reinforcing structure 102 further includes the supporting structure 1023, the supporting structure 1023 can enhance the strength of the reinforcing structure 102, further isolate the internal stress generated by the substrate 101, prevent the rewiring layer 104 from delamination, or prevent the package layer 105 between two adjacent bare chips 103 from cracking.

It should be noted that, in the third embodiment, the step S16 in the first embodiment is replaced by the step S50, and it is to be understood that the step S34 in the second embodiment may be replaced by the step S50, and the chip package structure 10 shown in fig. 3, fig. 5a, fig. 5b, and fig. 5c may be prepared after the step S34 in the second embodiment is replaced by the step S50.

Example IV

The manufacturing method of the chip package structure 10 provided in the fourth embodiment is different from the manufacturing method of the chip package structure 10 provided in the first embodiment in that in the fourth embodiment, the step S16 in the first embodiment is replaced by the step S60, and in the fourth embodiment, the supporting structure 1023 includes a grid structure.

The fourth embodiment only describes the portions different from the first embodiment, and the same portions may refer to the first embodiment, which is not described herein.

Step S60 includes: forming a reinforcing structure 102 on the rewiring layer 104; the reinforcing structure 102 includes a dielectric layer 1021 and interconnect lines 1022; interconnect line 1022 extends through dielectric layer 1021, interconnect line 1022 is electrically connected to rewiring layer 104; the reinforcing structure 102 further includes: a support structure 1023, the support structure 1023 disposed within the dielectric layer 1021; support structure 1023 is disposed around interconnect line 1022, with the projection of support structure 1023 and interconnect line 1022 onto rewiring layer 104 being free of overlapping areas; support structure 1023 includes a grid structure 1023b, and reinforcing structure 102 further includes: the grounding structure 1024, the grounding structure 1024 is disposed in the dielectric layer 1021, and the grounding structure 1024 is electrically connected to the grounding terminal of the substrate 101 and the grid structure 1023 b.

Step S60 may include, for example:

first, as shown in fig. 38, an interconnect line 1022, a support structure 1023, and a ground structure 1024 are formed on the rewiring layer 104; interconnect 1022 is electrically connected to rewiring layer 104, and ground structure 1024 is electrically connected to support structure 1023.

Here, the supporting structure 1023 and the grounding structure 1024 may be electrically connected to the rewiring layer 104, or may not be electrically connected to the rewiring layer 104.

Note that in some examples, interconnect line 1022, support structure 1023, and ground structure 1024 are formed simultaneously. In other examples, the interconnect line 1022, the support structure 1023, and the ground structure 1024 are sequentially formed, in which case the order in which the interconnect line 1022, the support structure 1023, and the ground structure 1024 are sequentially formed is not limited, and for example, the interconnect line 1022 may be formed first, the ground structure 1024 may be formed, and the support structure 1023 may be formed. In still other examples, any two of interconnect lines 1022, support structure 1023, and ground structure 1024 may be formed first, and then one of them is formed; alternatively, one of them is formed first, and then the remaining two are formed. For example, interconnect lines 1022 and ground structure 1024 may be formed simultaneously, followed by formation of support structure 1023.

In addition, the heights of the interconnect lines 1022, the support structure 1023, and the ground structure 1024 may be the same or different.

Next, as shown in fig. 39, a dielectric layer 1021 is formed over the interconnect line 1022, the support structure 1023, and the ground structure 1024, and the dielectric layer 1021 covers the interconnect line 1022, the support structure 1023, and the ground structure 1024.

Next, as shown in fig. 40, the dielectric layer 1021 is thinned, exposing the interconnect line 1022 and the ground structure 1024.

The first solder assembly 108 is also electrically connected to the grounding structure 1024 when the first solder assembly 108 is formed on the reinforcing structure 102 in a subsequent step. Since the reinforcement structure 102 is bonded to the substrate 101, the plurality of first solder elements 108 are electrically connected to the substrate 101, and the grounding structure 1024 is electrically connected to the substrate 101.

The chip package structure 10 shown in fig. 7 can be manufactured by using the manufacturing method of the chip package structure 10 provided in the fourth embodiment. In addition to having the same technical effects as those of the third embodiment, in the fourth embodiment, since the supporting structure 1023 in the reinforcing structure 102 includes the grid structure 1023b, the reinforcing structure 102 further includes the grounding structure 1024, and the grounding structure 1024 is electrically connected with the grounding terminal of the substrate 101 and the grid structure 1023b, so that the grounding voltage can be provided to the grounding structure 1024 through the grounding terminal of the substrate 101, and then the grounding voltage is provided to the grid structure 1023b, so that the grid structure 1023b can also play a role in preventing the mutual crosstalk between the signals on the substrate 101 and the signals on the bare chip 103, that is, the transmission of the signals along the direction perpendicular to the substrate is protected by the grounding manner, and the electrical performance is improved. In addition, the mesh structure may also function to prevent crosstalk of signals between the interconnect lines.

It should be noted that, in the fourth embodiment, the step S16 is replaced by the step S60 in the first embodiment, it is to be understood that the step S34 in the second embodiment may be replaced by the step S60, and the step S34 in the second embodiment may be replaced by the step S60, so that the chip package structure 10 shown in fig. 7 may be prepared.

In another aspect of the present application, there is also provided a non-transitory computer readable storage medium for use with a computer having software for creating the chip-packaging structure 10 described above, the computer readable storage medium having stored thereon one or more computer readable data structures having control data, such as photomask data, for preparing any of the illustrations provided above.

The foregoing is merely specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the present application, and the changes and substitutions are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A chip package structure, comprising:

at least one bare chip;

a rewiring layer for carrying the at least one die;

a substrate, the rewiring layer being disposed between the at least one die and the substrate;

a reinforcing structure arranged between the rewiring layer and the substrate, wherein the reinforcing structure comprises a dielectric layer, an interconnection line penetrating through the dielectric layer and a columnar and/or grid-shaped supporting structure in the dielectric layer; the interconnection line is electrically connected with the rewiring layer and the substrate, and the supporting structure is arranged around the interconnection line;

and an encapsulation layer filling a gap between the bare chip and the rewiring layer, and a side surface of the bare chip.
The chip package structure of claim 1, wherein the support structure comprises a grid structure, the interconnect lines being located within the grid structure.
The chip package structure of claim 2, wherein the reinforcement structure further comprises: the grounding structure is arranged in the dielectric layer;

the grounding structure is electrically connected with the grounding terminal of the substrate and the grid structure.
A chip package structure according to any one of claims 1-3, wherein the support structure comprises a plurality of support posts.
The chip package structure of any one of claims 1-4, wherein the support structure extends through the dielectric layer.
The chip package structure according to any one of claims 1 to 5, wherein a material of the dielectric layer is an organic material, and a material of the package layer is an organic material.
The chip package structure of claim 6, wherein the encapsulation layer comprises a first underfill and a plastic layer; the first underfill is filled in a gap between the bare chip and the rewiring layer, and the plastic layer is filled on the side face of the bare chip;

the material of the dielectric layer is the same as that of the first underfill or the plastic layer.
The chip package structure according to claim 6 or 7, wherein the material of the dielectric layer comprises one or more of epoxy, silicone, polyimide.
The chip package structure according to any one of claims 1 to 8, wherein the rewiring layer comprises at least one metal line layer and an insulating layer, the at least one metal line layer being located within the insulating layer;

Wherein the material of the insulating layer is an organic material or an inorganic material.
The chip packaging structure according to any one of claims 1 to 9, further comprising: and the second underfill is filled in the gap between the reinforcing structure and the substrate and overflows to the side surface of the packaging layer.
The preparation method of the chip packaging structure is characterized by comprising the following steps:

forming a rewiring layer on the first temporary carrier plate;

binding at least one bare chip on the rewiring layer, wherein the bare chip is electrically connected with the rewiring layer;

filling an encapsulation layer to encapsulate the at least one die;

removing the first temporary carrier plate and exposing the rewiring layer;

forming a reinforcement structure on the rewiring layer; the reinforcement structure comprises a dielectric layer and an interconnection line; the interconnection line penetrates through the dielectric layer and is electrically connected with the rewiring layer;

binding the reinforcing structure with the substrate; wherein the interconnection line is electrically connected with the substrate.
The method of manufacturing according to claim 11, wherein the reinforcing structure further comprises: the support structure is arranged in the dielectric layer; the support structure is disposed about the interconnect line.
The method of manufacturing according to claim 12, wherein the support structure comprises a lattice structure; the reinforcing structure further includes: the grounding structure is arranged in the dielectric layer and is electrically connected with the grounding terminal of the substrate and the grid structure.
The method of any one of claims 11-13, wherein forming a reinforcing structure on the rewiring layer comprises:

forming an interconnect line on the rewiring layer, the interconnect line being electrically connected to the rewiring layer;

forming a dielectric layer on the interconnection line, wherein the dielectric layer covers the interconnection line;

and thinning the dielectric layer to expose the interconnection line.
The method of any one of claims 11-14, wherein after the filling of the encapsulation layer, before the removing the first temporary carrier, the method further comprises:

and thinning the packaging layer to expose the surface of the bare chip far away from the first temporary carrier plate.
The method of manufacturing of claim 15, wherein after the thinning the encapsulation layer, before the removing the first temporary carrier, the method further comprises:

And forming a second temporary carrier plate on one side of the bare chip far away from the rewiring layer, wherein the second temporary carrier plate is fixedly connected with the bare chip.
The method of manufacturing of claim 16, wherein after the forming of the reinforcing structure on the rewiring layer, before the bonding of the reinforcing structure to the substrate, the method of manufacturing further comprises:

and removing the second temporary carrier plate.
The method of any of claims 11-14, wherein after the forming of the reinforcing structure on the rewiring layer, prior to the bonding of the reinforcing structure to the substrate, the method further comprises:

forming a plurality of first welding assemblies on the reinforcing structure, wherein the first welding assemblies are electrically connected with the interconnection circuit;

wrapping a plurality of the first welding components with adhesive tape;

thinning the packaging layer to expose the surface of the bare chip far away from the rewiring layer;

removing the adhesive tape to expose a plurality of the first welding components;

binding the reinforcing structure with the substrate, comprising:

binding the plurality of first welding assemblies with the substrate, wherein the first welding assemblies are electrically connected with the substrate.
An electronic device comprising a printed circuit board and the chip package structure of any one of claims 1-10;

the chip packaging structure is electrically connected with the printed circuit board.