CN112992807A - Semiconductor structure and manufacturing method thereof - Google Patents

Semiconductor structure and manufacturing method thereof Download PDF

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Publication number
CN112992807A
CN112992807A CN202110133835.4A CN202110133835A CN112992807A CN 112992807 A CN112992807 A CN 112992807A CN 202110133835 A CN202110133835 A CN 202110133835A CN 112992807 A CN112992807 A CN 112992807A
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China
Prior art keywords
layer
support
semiconductor structure
supporting piece
redistribution
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CN202110133835.4A
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Chinese (zh)
Inventor
吕文隆
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CN202110133835.4A priority Critical patent/CN112992807A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

The present disclosure relates to semiconductor structures and methods of fabricating the same. The semiconductor structure includes: a rewiring layer having a first surface and a second surface opposite to the first surface; the first electronic assembly is arranged on the first surface or the second surface and is electrically connected with the rewiring layer; the first support piece is arranged on the first surface or the second surface; and the mold sealing layer coats the rewiring layer, the first electronic assembly and the first supporting piece. The semiconductor structure and the manufacturing method thereof can not only effectively reduce the thickness of the whole structure, but also prevent warping.

Description

Semiconductor structure and manufacturing method thereof
Technical Field
The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor structure and a method for fabricating the same.
Background
With the increasing demand for miniaturization, multi-functionalization and high efficiency of electronic product systems, attention is paid to a high-density Package structure, i.e., a Double-sided Package Module (DSM), in System In Package (SiP) applications.
However, the overall semiconductor structure is quite complex due to the use of multiple encapsulation materials in the DSM structure and the use of various components and functional devices. The semiconductor structure may fail due to warpage of the entire structure caused by mismatch of various device materials or mixed sizes of various devices.
Disclosure of Invention
The present disclosure provides semiconductor structures and methods of fabricating the same.
In a first aspect, the present disclosure provides a semiconductor structure comprising: a rewiring layer having a first surface and a second surface opposite to the first surface; the first electronic assembly is arranged on the first surface or the second surface and is electrically connected with the rewiring layer; the first support piece is arranged on the first surface or the second surface; and the mold sealing layer coats the rewiring layer, the first electronic assembly and the first supporting piece.
In some alternative embodiments, the redistribution layer has at least one via; and a mold sealing layer covering the rewiring layer, the electronic component and the first support member, including: the mold sealing layer coats the rewiring layer, the first electronic assembly and the first supporting piece through at least one through hole.
In some optional embodiments, the semiconductor structure further comprises: and the second electronic assembly is arranged on the first surface or the second surface and is electrically connected with the rewiring layer.
In some optional embodiments, the semiconductor structure further comprises: the second support piece is arranged on the first surface or the second surface.
In some optional embodiments, the semiconductor structure further comprises: and the fixing piece is arranged between the first supporting piece and the rewiring layer and between the second supporting piece and the rewiring layer.
In some optional embodiments, the redistribution layer includes a first circuit layer, a second circuit layer and a dielectric layer, the first circuit layer and the second circuit layer are buried in the dielectric layer and exposed from the dielectric layer, and the first circuit layer is electrically connected to the second circuit layer.
In some optional embodiments, the first support, provided on the first surface or the second surface, comprises: the first supporting piece is arranged on the first circuit layer or the second circuit layer;
in some optional embodiments, the second support, provided on the first surface or the second surface, comprises: the second supporting piece is arranged on the first circuit layer or the second circuit layer.
In some alternative embodiments, the first support or the second support is exposed from the encapsulation layer; and the semiconductor structure further comprises: and the conductive element is arranged on the first support part or the second support part and is electrically connected with the redistribution layer through the first support part or the second support part.
In some optional embodiments, the first support, provided on the first surface or the second surface, comprises: the first support part is arranged on the dielectric layer;
in some optional embodiments, the second support, provided on the first surface or the second surface, comprises: the second support is arranged on the dielectric layer.
In a second aspect, the present disclosure provides a method of fabricating a semiconductor structure, comprising: arranging a first support member on a first carrier; forming a rewiring layer on the second carrier, the rewiring layer having a first surface and a second surface opposite to the first surface; disposing a first electronic component on the first surface or the second surface; disposing a first support on the first surface or the second surface; providing at least one through hole on the rewiring layer; and filling the mold sealing material, wherein the mold sealing material passes through the at least one through hole to form a mold sealing layer for coating the rewiring layer, the first electronic component and the first supporting piece.
In some optional embodiments, after disposing the first electronic component on the first surface or the second surface, the method further comprises: the second electronic component is disposed on the first surface or the second surface.
In some optional embodiments, after disposing the first support on the first surface or the second surface, the method further comprises: disposing a second support on a third carrier; the second support is disposed on the first surface or the second surface.
In some alternative embodiments, the first carrier, the second carrier, and the third carrier are carriers having release films.
In some alternative embodiments, after providing the first support on the first carrier, the method further comprises: a fixing member is provided on the first support member.
In some alternative embodiments, providing the first support on the first surface or the second surface comprises: and fixing the first support on the first surface or the second surface through the fixing piece.
In some optional embodiments, after disposing the second support on the third carrier, the method further comprises: arranging a fixing piece on the second supporting piece; and disposing a second support on the first surface or the second surface, comprising: and fixing the second support piece on the first surface or the second surface through a fixing piece.
In some optional embodiments, forming a redistribution layer on the second carrier includes: forming a first circuit layer on a second carrier; forming a dielectric layer on the first circuit layer to embed the first circuit layer in the dielectric layer; providing at least one buried via in the dielectric layer; forming a second circuit layer on the dielectric layer; the first circuit layer is electrically connected with the second circuit layer through at least one buried via.
In some alternative embodiments, providing the first support on the first surface or the second surface comprises: the first supporting member is arranged on the first circuit layer or the second circuit layer.
In some alternative embodiments, disposing the second support on the first surface or the second surface comprises: arranging a second supporting piece on the first circuit layer or the second circuit layer; and the first support member or the second support member is exposed from the mold sealing layer; and the method further comprises: a conductive element is disposed on the first support or the second support.
In some alternative embodiments, providing the first support on the first surface or the second surface comprises: the first support is disposed on the dielectric layer.
In some alternative embodiments, disposing the second support on the first surface or the second surface comprises: the second support is disposed on the dielectric layer.
In order to solve the technical problem that the semiconductor structure is finally failed due to warpage deformation of the whole structure caused by mismatch of various component materials or mixed sizes of various components in the DSM structure, the present disclosure provides a semiconductor structure and a manufacturing method thereof, wherein a Redistribution layer (RDL) is designed and a first support member for providing support strength for the Redistribution layer is provided to replace a Substrate (Substrate) in the existing DSM structure. The thickness of the substrate is usually several millimeters, while the thickness of the redistribution layer is only several micrometers, and the stress increases with the increase of the thickness, and warpage deformation is liable to occur under the stress accumulation. Therefore, the semiconductor structure and the manufacturing method thereof provided by the disclosure can effectively reduce the thickness of the whole structure and can prevent warping.
In addition, in the manufacturing process of the existing DSM structure, the two sides of the substrate need to be respectively molded, that is, two times of molding are needed, and the semiconductor structure and the manufacturing method thereof provided by the present disclosure can avoid stress accumulation and prevent warpage by arranging the through hole on the redistribution layer to allow the molding material to pass through the through hole to complete the DSM structure in a manner of realizing one-time molding.
Drawings
Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIG. 1 is a schematic structural diagram of one embodiment of a semiconductor structure according to the present disclosure;
FIG. 2 is a schematic structural diagram of yet another embodiment of a semiconductor structure according to the present disclosure;
FIG. 3 is a schematic structural diagram of yet another embodiment of a semiconductor structure according to the present disclosure;
FIG. 4 is a schematic structural diagram of yet another embodiment of a semiconductor structure according to the present disclosure;
FIG. 5 is a schematic structural diagram of yet another embodiment of a semiconductor structure according to the present disclosure;
FIG. 6 is a schematic structural diagram of yet another embodiment of a semiconductor structure according to the present disclosure;
fig. 7A to 7G are schematic structural views in the manufacturing process of a semiconductor structure according to the present disclosure.
Description of the symbols:
1-a rewiring layer, 101-a via, 102-a first circuit layer, 103-a second circuit layer, 104-a dielectric layer, 2-a first electronic component, 3-a first support, 4-a mold seal, 5-a second electronic component, 6-a second support, 7-a fixture, 8-a conductive element, 9-an underfill, 10-a first carrier, 11-a second carrier, 12-a fourth carrier, 13-an adhesive layer.
Detailed Description
The following description of the embodiments of the present disclosure will be provided in conjunction with the accompanying drawings and examples, and those skilled in the art can easily understand the technical problems and effects of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.
It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the conditions under which the present disclosure can be implemented, so they are not technically significant, and any modifications of the structures, changes in the proportions and adjustments of the dimensions should be made without affecting the efficacy and attainment of the same. In the present specification, the terms "upper", "first", "second" and "first" are used for clarity of description only, and are not intended to limit the scope of the present disclosure, and changes or modifications in relative relationships thereof should be construed as being within the scope of the present disclosure without substantial technical changes.
In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Fig. 1 is a schematic structural diagram of one embodiment of a semiconductor structure according to the present disclosure. As shown in fig. 1, the semiconductor structure may include: the rewiring layer 1, the first electronic component 2, the first support 3, and the mold seal layer 4. The redistribution layer 1 has a first surface and a second surface opposite to the first surface, the first electronic component 2 is disposed on the first surface or the second surface, the first electronic component 2 is electrically connected to the redistribution layer 1, the first support member 3 is disposed on the first surface or the second surface, and the mold sealing layer 4 covers the redistribution layer 1, the first electronic component 2, and the first support member 3.
The redistribution layer 1 may change the location of the Circuit contact (I/O pad) of an originally designed Integrated Circuit (IC), so that the IC can be adapted to different packaging types.
The first electronic component 2 may be an active component (active component), such as a chip or the like, or a passive component (passive component), such as a capacitor, an inductor, a resistor or the like.
The first support member 3 can provide support strength to the rewiring layer 1, and thus can enhance the strength of the entire structure.
The first support 3 may be a rigid support or a soft support, for example. The material for the rigid support may be an insulating material comprising a metal or alloy, such as copper, nickel, gold, silver or stainless steel, such as silicon, glass, ceramic or an organic material, or any other suitable material. The material for the soft support may be rubber, thermoplastic, thermoelastic or any other suitable material.
The first support 3 may be, for example, a solder ball or a conductive post. Fig. 6 is a schematic structural diagram of a semiconductor structure according to another embodiment of the present disclosure, and as shown in fig. 6, the first support 3 may be a stud, for example.
The Molding layer 4 may be formed of various Molding materials (Molding Compound). For example, the molding material may include Epoxy resin (Epoxy resin), bt (toner Triazine resin), Filler (Filler), Catalyst (Catalyst), Pigment (Pigment), Release Agent (Release Agent), Flame Retardant (Flame Retardant), Coupling Agent (Coupling Agent), Hardener (hardner), Low Stress Absorber (Low Stress Absorber), Adhesion Promoter (Adhesion Promoter), Ion trap (Ion Trapping Agent), and the like.
In some alternative embodiments, the redistribution layer 1 may have at least one through hole 101, and the mold sealing layer 4 covers the redistribution layer 1, the first electronic component 2, and the first support 3 through the at least one through hole 101.
Through the through hole 101 arranged on the rewiring layer 1, the DSM structure is completed by enabling the molding material to pass through the through hole 101 in a primary molding mode, and stress accumulation can be avoided as much as possible to prevent warping.
In some optional embodiments, the semiconductor structure may further include: and a second electronic component 5 provided on the first surface or the second surface, the second electronic component 5 being electrically connected to the redistribution layer 1.
The second electronic component 5 may be an active component (active component), such as a chip or the like, or a passive component (passive component), such as a capacitor, an inductor, a resistor or the like.
In some optional embodiments, fig. 3 is a schematic structural diagram of a further embodiment of a semiconductor structure according to the present disclosure, as shown in fig. 3, the semiconductor structure may further include: and the second support 6 is arranged on the first surface or the second surface.
The second support member 6 can provide a supporting strength to the redistribution layer 1, and thus, the strength of the entire structure can be enhanced.
The second support 6 may be a rigid support or a soft support, for example. The material for the rigid support may be an insulating material comprising a metal or alloy, such as copper, nickel, gold, silver or stainless steel, such as silicon, glass, ceramic or an organic material, or any other suitable material. The material for the soft support may be rubber, thermoplastic, thermoelastic or any other suitable material.
In some optional embodiments, the semiconductor structure may further include: and a fixing member 7 provided between the first support member 3 and the redistribution layer 1 and between the second support member 6 and the redistribution layer 1.
The fixing member 7 may be used to position the position where the first support member 3 is connected to the rewiring layer 1 and the position where the second support member 6 is connected to the rewiring layer 1. Thus, the fixing member 7 can be arranged at the selected vacant position by circuit design to connect the first support member 3 or the second support member 6.
The fixing member 7 may be a material having an adhesive function, and may be, for example, epoxy resin conductive paste, phenolic resin conductive paste, polyurethane conductive paste, thermoplastic resin conductive paste, and polyimide conductive paste.
The fixing member 7 may also be a material having an adsorbing effect, such as a solder ball.
In some optional embodiments, the redistribution layer 1 may include a first line layer 102, a second line layer 103, and a dielectric layer 104, the first line layer 102 and the second line layer 103 are embedded in the dielectric layer 104 and exposed from the dielectric layer 104, and the first line layer 102 is electrically connected to the second line layer 103.
Here, the first circuit layer 102 may electrically connect the first electronic component 2, and the second circuit layer 103 may electrically connect the second electronic component 5.
In some alternative embodiments, the first support 3 may be disposed on the first circuit layer 102 or the second circuit layer 103.
Here, the first supporting member 3 may be electrically connected to the first circuit layer 102 or the second circuit layer 103 to achieve an electrical connection function. The first support 3 may not only provide support strength for the redistribution layer 1, but also be used for electrical connection.
In some alternative embodiments, the second supporting member 6 may be disposed on the first wiring layer 102 or the second wiring layer 103.
Here, the second supporting member 6 may be electrically connected to the first circuit layer 102 or the second circuit layer 103 to achieve an electrical connection function. The second supporting member 6 may not only provide a supporting strength for the redistribution layer 1, but also be used for electrical connection.
In some alternative embodiments, the first support 3 or the second support 6 may be exposed from the mold seal layer 4; and the semiconductor structure may further include: and the conductive element 8 is arranged on the first support part 3 or the second support part 6, and the conductive element 8 is electrically connected with the rewiring layer 1 through the first support part 3 or the second support part 6.
The conductive element 8 may be, for example, a wire (Trace), a Bump (Bump), a Solder Ball (Solder Ball), or the like, to electrically connect the semiconductor structure with the outside.
In some alternative embodiments, the first support 3 may be provided on the dielectric layer 104.
Here, the first support 3 is mainly used for supporting the redistribution layer 1, and a part of the first support 3 may also be used for electrical connection. When the first support 3 is used only for supporting the rewiring layer 1, it may be provided on the first line layer 102 or the dielectric layer 104 of the rewiring layer 1. When the first support 3 is used only for supporting the redistribution layer 1 and electrically connecting, it may be disposed on the first circuit layer 102 of the redistribution layer 1.
In some alternative embodiments, the second support 6 may be provided on the dielectric layer 104.
Here, the second supporting member 6 is mainly used for supporting the redistribution layer 1, and a part of the second supporting member 6 may also be used for electrical connection. When the second support member 6 is used only for supporting the rewiring layer 1, it may be provided on the second wiring layer 103 or the dielectric layer 104 of the rewiring layer 1. When the second support member 6 is used only for supporting the redistribution layer 1 and electrically connecting, it may be disposed on the second wiring layer 103 of the redistribution layer 1.
In some optional embodiments, fig. 2 is a schematic structural diagram of a further embodiment of a semiconductor structure according to the present disclosure, and as shown in fig. 2, a redistribution layer 1 may cover a part of an edge of the semiconductor structure.
In some optional embodiments, fig. 4 is a schematic structural diagram of a further embodiment of a semiconductor structure according to the present disclosure, as shown in fig. 4, the semiconductor structure may further include: an underfill 9, the underfill 9 may encapsulate the first electronic component 2. The first electronic component 2 is electrically connected to the rewiring layer 1 by flip-chip technology.
The underfill 9 may be, for example, Capillary Underfill (CUF), Molded Underfill (MUF), Non-conductive Paste (NCP), or the like. The underfill 9 may fill the voids to achieve reinforcement.
In some alternative embodiments, fig. 5 is a schematic structural diagram of another example of the semiconductor structure according to the present disclosure, and as shown in fig. 5, the redistribution layer 1 and the first electronic component 2 may be electrically connected by wire bonding.
The semiconductor structure provided by the disclosure replaces a substrate in the existing DSM structure by designing the redistribution layer 1 and the first support member 3 providing support strength for the redistribution layer 1, so that the thickness of the whole structure can be effectively reduced, and warping can be prevented. Furthermore, by providing the through hole 101 in the redistribution layer 1 and forming the DSM structure by passing the molding material through the through hole 101 in a manner of primary molding, it is possible to prevent the accumulation of stress as much as possible and prevent warpage.
Fig. 7A to 7G are schematic structural views in the manufacturing process of a semiconductor structure according to the present disclosure. The figures have been simplified for a better understanding of various aspects of the disclosure.
Referring to fig. 7A, a first support 3 may be disposed on the first carrier 10.
In some alternative embodiments, a fixing member 7 may be provided on the first support 3.
The first support 3 can be fixed to the first surface or the second surface by the fixing member 7.
In some alternative embodiments, a second support 6 may be provided on the third carrier.
In some alternative embodiments, a fixing member 7 may be provided on the second support member 6.
The second support 6 can be fixed to the first surface or the second surface by means of a fixing 7.
In some alternative embodiments, the first carrier 10, the second carrier 11, and the third carrier may be carriers having release films.
Referring to fig. 7B, a rewiring layer 1 may be formed on the second carrier 11.
The rewiring layer 1 may have a first surface and a second surface opposite to the first surface.
In some optional embodiments, specifically, the redistribution layer 1 may be formed by: forming a first wiring layer 102 on the second carrier 11; forming a dielectric layer 104 on the first circuit layer 102, so that the first circuit layer 102 is embedded in the dielectric layer 104; providing at least one buried via on the dielectric layer 104; forming a second circuit layer 103 on the dielectric layer 104; the first wiring layer 102 is electrically connected to the second wiring layer 103 through at least one buried via.
Referring to fig. 7C, the first electronic component 2 may be disposed on the first surface or the second surface.
Referring to fig. 7D, in some alternative embodiments, an adhesive layer 13 may be disposed on the redistribution layer 1 to cover the first electronic component 2, and a fourth carrier 12 may be disposed on the adhesive layer 13, and turned over to dispose the second electronic component 5 on the first surface or the second surface.
Referring to fig. 7E, at least one via 101 may be provided on the redistribution layer 1.
Here, the at least one through hole 101 may be provided using, for example, laser drilling.
Referring to fig. 7F, the first support 3 may be disposed on the first surface or the second surface.
In some alternative embodiments, the second support 6 may be provided on the first surface or the second surface.
In some alternative embodiments, the first support 3 may be disposed on the first circuit layer 102 or the second circuit layer 103.
In some alternative embodiments, the second supporting member 6 may be disposed on the first wiring layer 102 or the second wiring layer 103.
In some alternative embodiments, the first support 3 may be disposed on the dielectric layer 104.
In some alternative embodiments, the second support 6 may be disposed on the dielectric layer 104.
In some alternative embodiments, the first support 3 or the second support 6 may be exposed from the mold seal layer 4; and the method further comprises: a conductive element 8 is provided on the first support 3 or the second support 6.
Referring to fig. 7G, a mold sealing material may be filled in, and the mold sealing material may pass through the at least one through hole 101 to form a mold sealing layer 4 covering the redistribution layer 1, the first electronic component 2 and the first support member 3.
According to the method for manufacturing the semiconductor structure, the first supporting piece 3 and the second supporting piece 6 are prepared firstly and then connected with the redistribution layer 1, and the first supporting piece 3 and the second supporting piece 6 can be arranged at different positions and can be used for supporting the redistribution layer 1 and can also be used for electrical connection. Furthermore, by providing the through hole 101 in the redistribution layer 1 and forming the DSM structure by passing the molding material through the through hole 101 in a manner of primary molding, it is possible to prevent the accumulation of stress as much as possible and prevent warpage.
While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof within the embodiments without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction and the actual implementation in the present disclosure due to variables in the manufacturing process, and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.

Claims (10)

1. A semiconductor structure, comprising:
a rewiring layer having a first surface and a second surface opposite to the first surface;
the first electronic assembly is arranged on the first surface or the second surface and is electrically connected with the rewiring layer;
the first support piece is arranged on the first surface or the second surface;
and the mould sealing layer coats the rewiring layer, the first electronic assembly and the first supporting piece.
2. The semiconductor structure of claim 1, wherein the redistribution layer has at least one via; and
the mold sealing layer, cladding the rewiring layer, the electronic component and the first support member, includes:
the mold sealing layer coats the rewiring layer, the first electronic component and the first supporting piece through the at least one through hole.
3. The semiconductor structure of claim 1 or 2, wherein the semiconductor structure further comprises:
and the second electronic assembly is arranged on the first surface or the second surface and is electrically connected with the redistribution layer.
4. The semiconductor structure of claim 1 or 2, wherein the semiconductor structure further comprises:
the second supporting piece is arranged on the first surface or the second surface.
5. The semiconductor structure of claim 4, wherein the semiconductor structure further comprises:
and the fixing piece is arranged between the first supporting piece and the redistribution layer and between the second supporting piece and the redistribution layer.
6. The semiconductor structure of claim 4, wherein the redistribution layer comprises a first line layer, a second line layer, and a dielectric layer, the first and second line layers being buried within and exposed from the dielectric layer, the first line layer being electrically connected with the second line layer.
7. The semiconductor structure of claim 6, wherein the first support, disposed on the first surface or the second surface, comprises:
the first supporting piece is arranged on the first circuit layer or the second circuit layer; and/or
The second supporting member is disposed on the first surface or the second surface, and includes:
the second supporting piece is arranged on the first circuit layer or the second circuit layer.
8. The semiconductor structure of claim 7, wherein the first or second support is exposed from the encapsulation layer; and
the semiconductor structure further includes:
and the conductive element is arranged on the first support part or the second support part and is electrically connected with the redistribution layer through the first support part or the second support part.
9. The semiconductor structure of claim 6, wherein the first support, disposed on the first surface or the second surface, comprises:
the first supporting piece is arranged on the dielectric layer; and/or
The second supporting member is disposed on the first surface or the second surface, and includes:
the second support is arranged on the dielectric layer.
10. A method of fabricating a semiconductor structure, comprising:
arranging a first support member on a first carrier;
forming a redistribution layer on a second carrier, the redistribution layer having a first surface and a second surface opposite the first surface;
disposing a first electronic component on the first surface or the second surface;
disposing the first support on the first surface or the second surface;
providing at least one via on the redistribution layer;
and filling a mold sealing material, wherein the mold sealing material passes through the at least one through hole to form a mold sealing layer for coating the rewiring layer, the first electronic component and the first supporting piece.
CN202110133835.4A 2021-02-01 2021-02-01 Semiconductor structure and manufacturing method thereof Pending CN112992807A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023123106A1 (en) * 2021-12-29 2023-07-06 华为技术有限公司 Chip packaging structure and preparation method therefor, and electronic device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023123106A1 (en) * 2021-12-29 2023-07-06 华为技术有限公司 Chip packaging structure and preparation method therefor, and electronic device

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