CN117279462A - Preparation method of flexible three-dimensional integrated circuit structure, inverter and integrated circuit - Google Patents

Preparation method of flexible three-dimensional integrated circuit structure, inverter and integrated circuit Download PDF

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CN117279462A
CN117279462A CN202311326159.8A CN202311326159A CN117279462A CN 117279462 A CN117279462 A CN 117279462A CN 202311326159 A CN202311326159 A CN 202311326159A CN 117279462 A CN117279462 A CN 117279462A
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type transistor
flexible
dielectric layer
integrated circuit
drain electrode
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张敏
张娇娜
王婉婷
朱家豪
王佳良
王新炜
孟鸿
赵长斌
潘媛
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Peking University Shenzhen Graduate School
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Peking University Shenzhen Graduate School
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
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    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/10—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising field-effect transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/20—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00 comprising components having an active region that includes an inorganic semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K19/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic element specially adapted for rectifying, amplifying, oscillating or switching, covered by group H10K10/00
    • H10K19/201—Integrated devices having a three-dimensional layout, e.g. 3D ICs

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Abstract

The application relates to a preparation method of a flexible three-dimensional integrated circuit structure, an inverter and an integrated circuit, wherein the method comprises the following steps: forming a first substrate; forming a P-type transistor on a first substrate; depositing a second gate dielectric layer of the N-type transistor over the P-type transistor; forming a second channel region of the N-type transistor on the second gate dielectric layer; etching to expose the first source electrode and the first drain electrode of the P-type transistor in a second wet etching mode; and forming a second source electrode and a second drain electrode of the N-type transistor on two sides of the second channel region respectively, wherein the second drain electrode is connected with a first drain electrode of the P-type transistor below to form an output end of the inverter. The inverter and the integrated circuit prepared by the method have the advantages of keeping high flexibility of the inverter and the integrated circuit, ensuring stability of the inverter and the integrated circuit and reducing time delay.

Description

Preparation method of flexible three-dimensional integrated circuit structure, inverter and integrated circuit
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for manufacturing a flexible three-dimensional integrated circuit structure, an inverter, and an integrated circuit.
Background
The rapid development of flexible electrons based on the CMOS technology accelerates the arrival of the Internet of things era. Flexible CMOS electronics are widely used in health monitoring, human-machine interaction and wearable electronics. In most flexible product applications, CMOS integrated circuits are required to have both high integration density and high mechanical flexibility characteristics.
For the realization of high density integrated circuits, single layer stacked three-dimensional structures are widely used. The structure has the advantages of high integration density and reduced interconnect parasitics compared to conventional planar circuit structures. However, there are different inter-layer connected interconnect leads in a conventional three-dimensional structure. The interconnect leads are formed by opening the dielectric layers of the upper and lower transistor layers and depositing metal in the holes. These interconnects cannot withstand high mechanical stresses when the flex circuit is bent, and therefore the mechanical flexibility of the integrated circuit formed based on this structure is greatly compromised, reducing the performance of the integrated circuit formed from this structure.
In view of the above, there is a need for a new method for fabricating a flexible three-dimensional integrated circuit structure, an inverter, and an integrated circuit.
Disclosure of Invention
Aiming at the technical problems in the prior art, the preparation method of the flexible three-dimensional integrated circuit structure, the inverter and the integrated circuit solve the technical problems that interconnection lines in the integrated circuit structure in the prior art cannot bear high mechanical stress when the flexible circuit is bent, the flexibility of the integrated circuit structure is low, and the structural performance of the integrated circuit is greatly reduced.
In a first aspect, the present application provides a method for fabricating a flexible three-dimensional integrated circuit structure, the method comprising:
providing a first substrate;
spin-coating metallic carbon nanotubes as forming materials of source and drain electrodes on a first substrate, patterning to form a first source electrode and a first drain electrode of a P-type transistor, spin-coating semiconducting carbon nanotubes as forming materials of a channel region on the first substrate between the first source electrode and the first drain electrode, patterning to form a first channel region of the P-type transistor, depositing a first gate dielectric layer of the P-type transistor on the first channel region, depositing a gate layer on the first gate dielectric layer and patterning to form a gate of the P-type transistor;
depositing an oxide insulating layer on the P-type transistor, wherein the oxide insulating layer is a second gate dielectric layer of the N-type transistor;
depositing a metal oxide a-IGZO on the second grid dielectric layer in a DC magnetron sputtering mode to form a metal oxide a-IGZO channel layer, and removing the metal oxide a-IGZO channel layer outside the second channel region in a first wet etching mode to form a second channel region of the N-type transistor;
etching the first gate dielectric layer and the second gate dielectric layer in a second wet etching mode to expose the first source electrode and the first drain electrode of the P-type transistor; and
and forming a second source electrode and a second drain electrode of the N-type transistor on two sides of the second channel region respectively, wherein the second drain electrode is connected with a first drain electrode of the P-type transistor below to form an output end of the inverter.
In some embodiments, the DC magnetron sputtering mode adopts sputtering power of 120W and sputtering time of 200s, so as to realize the thickness of the metal oxide a-IGZO channel layer of 20nm;
the first wet etching mode adopts a ratio solution of 36% of dilute hydrochloric acid and 50:1 of deionized water.
In some embodiments, a flexible material solution is spin coated on a support substrate comprising glass, and the flexible material solution on the support substrate is baked to form a thin film, forming a first substrate.
In some embodiments, the first substrate, the first gate dielectric layer, the second gate dielectric layer, the first channel region, the second channel region, the first source electrode, and the first drain electrode are all formed of a flexible material.
In some embodiments, the first substrate comprises flexible PEN, PET, or PI.
In some embodiments, the first channel region of the P-type transistor is formed of a material including at least semiconducting carbon nanotubes, the first source and drain electrodes are formed of a material including at least metallic carbon nanotubes, the gate is formed of a material including at least metallic ITO, and the first and second gate dielectric layers are formed of a material including at least Al 2 O 3 Mixing with PI.
In some embodiments, the gate of the P-type transistor is formed by photolithography, the patterning includes patterning a photoresist, depositing ITO, and removing the photoresist to form the gate.
In a second aspect, the present application provides a flexible three-dimensional inverter comprising:
a first substrate;
the P-type transistor is positioned on the first substrate and comprises a first source electrode, a first drain electrode, a first channel region, a first grid dielectric layer and a grid electrode, wherein the first source electrode and the first drain electrode are respectively positioned on two sides of the first channel region, and the first grid dielectric layer and the grid electrode are sequentially positioned on the first source electrode, the first channel region and the first drain electrode; the first channel region of the P-type transistor is formed by a material at least comprising a semiconducting carbon nanotube, and the first source electrode and the first drain electrode are formed by a material at least comprising a metallic carbon nanotube;
the oxide insulating layer is positioned on the P-type transistor, and the oxide insulating layer is a second grid dielectric layer of the N-type transistor;
a second channel region of the N-type transistor on the second gate dielectric layer;
and the second drain electrode is connected with the first drain electrode of the P-type transistor below to form an output end of the inverter.
In some embodiments, the gate is formed of a material including at least metallic ITO, and the first gate dielectric layer and the second gate dielectric layer are formed of a material including at least Al 2 O 3 Mixing with PI.
In a third aspect, the present application provides an integrated circuit comprising a flexible three-dimensional inverter as defined in any one of the above.
The preparation method of the flexible three-dimensional integrated circuit structure, the inverter and the integrated circuit provided by the application provide a new design structure, and the method can realize high mechanical flexibility simultaneously on the premise of ensuring high density of the integrated circuit, even after the flexible three-dimensional integrated circuit structure is bent under severe bending conditions, the electrical characteristics of the inverter prepared by the preparation method of the flexible three-dimensional integrated circuit structure are not obviously reduced, the high flexibility of the inverter and the integrated circuit is maintained, and the technical effects of ensuring the stability performance of the inverter and the integrated circuit and reducing time delay are realized.
Drawings
Preferred embodiments of the present application will be described in further detail below with reference to the attached drawing figures, wherein:
FIGS. 1A-1F are schematic structural diagrams of a flexible three-dimensional integrated circuit structure according to one embodiment of the present application;
FIG. 2 is a flow chart diagram of a method of fabricating a flexible three-dimensional integrated circuit structure according to one embodiment of the present application;
3A-3I are schematic diagrams of a three-dimensional structure of a flexible three-dimensional integrated circuit structure according to one embodiment of the present application;
FIG. 4 is a second flowchart of a method of fabricating a flexible three-dimensional integrated circuit structure according to one embodiment of the present application;
FIG. 5 is a schematic diagram of a structure of a flexible three-dimensional inverter according to one embodiment of the present application; and
FIG. 6A is a bending state diagram of a flexible inverter fabricated by a method of fabricating a flexible three-dimensional integrated circuit structure according to one embodiment of the present application; and
fig. 6B is a graph illustrating performance of a flexible inverter fabricated by a method for fabricating a flexible three-dimensional integrated circuit structure according to an embodiment of the present invention with different bending conditions.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the application may be practiced. In the drawings, like reference numerals describe substantially similar components throughout the different views. Various specific embodiments of the present application are described in sufficient detail below to enable those skilled in the art to practice the teachings of the present application. It is to be understood that other embodiments may be utilized or structural, logical, or electrical changes may be made to the embodiments of the present application.
Techniques, methods, and apparatus known to one of ordinary skill in the relevant art may not be discussed in detail, but are intended to be part of the specification where appropriate. For the purpose of illustration only, the connection between elements in the figures is meant to indicate that at least the elements at both ends of the connection are in communication with each other and is not intended to limit the inability to communicate between elements that are not connected. In addition, the number of lines between two units is intended to indicate at least the number of signals involved in communication between the two units or at least the output terminals provided, and is not intended to limit the communication between the two units to only signals as shown in the figures.
Transistors may refer to transistors of any structure, such as Field Effect Transistors (FETs) or bipolar transistors (BJTs). When the transistor is a field effect transistor, it may be hydrogenated amorphous silicon, metal oxide, low temperature polysilicon, organic transistor, or the like, depending on the channel material. The carriers are electrons or holes, and can be classified into N-type transistors and P-type transistors, the control electrode of which refers to the gate of the field effect transistor, the first electrode can be the drain or source (which can also be referred to as drain or source electrode, both of which are referred to herein as the same), the corresponding second electrode can be the source or drain of the field effect transistor, and the control electrode or third electrode can be the gate; when the transistor is a bipolar transistor, the control electrode refers to the base electrode of the bipolar transistor, the first electrode may be the collector electrode or the emitter electrode of the bipolar transistor, the corresponding second electrode may be the emitter electrode or the collector electrode of the bipolar transistor, and the control electrode or the third electrode may be the base electrode. The transistor may be fabricated using amorphous silicon, polysilicon, oxide semiconductor, organic semiconductor, NMOS/PMOS processes, or CMOS processes.
The following description will take several embodiments as examples with reference to the accompanying drawings, and the drain and source of the transistor in the embodiments of the present application may vary according to the bias states of the transistor. However, the present application is not to be construed as limited to the embodiments illustrated, but is intended to cover modifications within the scope of the embodiments.
In order to realize a CMOS integrated circuit of high density and high mechanical flexibility, an excellent structural design is indispensable. The current mainstream CMOS integrated circuit structure mainly has two structures of plane and three-dimensional stack, and the plane structure has the characteristic of high flexibility, but is limited by low circuit integration density. While the three-dimensional stacked structure may help achieve a high integrated density of circuits, the structure may degrade the mechanical flexibility of the integrated circuit due to the presence of inter-layer interconnect lines. Thus, there is a tradeoff between high integration density and high flexibility of integrated circuits.
The present application provides a novel integrated circuit structure that circumvents the previously non-concurrent problems of the two features of high density and high mechanical flexibility. The high integrated density circuit realized based on the structure exhibits super-flexible characteristics, and the electrical characteristics are not significantly reduced after bending under severe bending conditions.
Embodiments of the present application will be described in further detail below with reference to the accompanying drawings. Wherein the method steps referred to in this application are presented by way of example only in terms of an exemplary flexible three-dimensional integrated circuit structure, and the disclosed methods are equally applicable to other types of integrated circuits and based on other material systems, such as logic gates, SRAM, full adder, amplifier, etc., as is well known to those skilled in the art.
Fig. 2 is a flowchart one of a method for manufacturing a flexible three-dimensional integrated circuit structure according to an embodiment of the present application, and as shown in fig. 2, the present application provides a method for manufacturing a flexible three-dimensional integrated circuit structure, which includes:
s201: forming a first substrate;
s202: spin-coating metallic carbon nanotubes as forming materials of source and drain electrodes on a first substrate, patterning to form a first source electrode and a first drain electrode of a P-type transistor, spin-coating semiconducting carbon nanotubes as forming materials of a channel region on the first substrate between the first source electrode and the first drain electrode, patterning to form a first channel region of the P-type transistor, depositing a first gate dielectric layer of the P-type transistor on the first channel region, depositing a gate layer on the first gate dielectric layer and patterning to form a gate of the P-type transistor;
s203: depositing an oxide insulating layer on the P-type transistor, wherein the oxide insulating layer is a second gate dielectric layer of the N-type transistor;
s204: depositing a metal oxide a-IGZO on the second grid dielectric layer in a DC magnetron sputtering mode to form a metal oxide a-IGZO channel layer, and removing the metal oxide a-IGZO channel layer outside the second channel region in a first wet etching mode to form a second channel region of the N-type transistor;
s205: etching the first gate dielectric layer and the second gate dielectric layer in a second wet etching mode to expose the first source electrode and the first drain electrode of the P-type transistor; and
s206: and forming a second source electrode and a second drain electrode of the N-type transistor on two sides of the second channel region respectively, wherein the second drain electrode is connected with a first drain electrode of the P-type transistor below to form an output end of the inverter.
Specifically, a P-type transistor is formed on a first substrate, the P-type transistor includes a first source electrode, a first drain electrode, a first channel region, a first gate dielectric layer, and a gate electrode, wherein the first source electrode and the first drain electrode are respectively located at two sides of the first channel region, and the first gate dielectric layer and the gate electrode are sequentially located above the first source electrode, the first channel region, and the first drain electrode.
The preparation method of the flexible three-dimensional integrated circuit structure in the embodiment provides a new design structure, which can simultaneously realize high mechanical flexibility on the premise of ensuring high density of the integrated circuit, and even after the flexible three-dimensional integrated circuit structure is bent under a severe bending condition, the electrical characteristics of the inverter prepared by the preparation method of the flexible three-dimensional integrated circuit structure are not obviously reduced, so that the high flexibility of the inverter and the integrated circuit is maintained, and the technical effect of ensuring the stability performance of the inverter and the integrated circuit is realized.
In some embodiments, the DC magnetron sputtering mode adopts sputtering power of 120W and sputtering time of 200s, so as to realize the thickness of the metal oxide a-IGZO channel layer of 20nm;
the first wet etching mode adopts a ratio solution of 36% of dilute hydrochloric acid and 50:1 of deionized water.
In some embodiments, a flexible material solution is spin coated on a support substrate comprising glass, and the flexible material solution on the support substrate is baked to form a thin film, forming a first substrate.
In some embodiments, the first substrate, the first gate dielectric layer, the second gate dielectric layer, the first channel region, the second channel region, the first source electrode, and the first drain electrode are all formed of a flexible material.
In some embodiments, the first substrate comprises flexible PEN, PET, or PI; other substrate materials known to those skilled in the art may be used herein, by way of example, and are not limited thereto.
In some embodiments, the first channel region of the P-type transistor is formed of a material including at least semiconducting carbon nanotubes, the first source and drain electrodes are formed of a material including at least metallic carbon nanotubes, the gate is formed of a material including at least metallic ITO, and the first and second gate dielectric layers are formed of a material including at least Al 2 O 3 Mixing with PI.
In some embodiments, the gate of the P-type transistor is formed by photolithography, the patterning includes patterning a photoresist, depositing ITO, and removing the photoresist to form the gate.
A method for fabricating a flexible three-dimensional integrated circuit structure according to another embodiment of the present application is described in detail below by way of another example. FIGS. 1A-1F are schematic structural diagrams of a flexible three-dimensional integrated circuit structure according to one embodiment of the present application; FIG. 4 is a second flowchart of a method of fabricating a flexible three-dimensional integrated circuit structure according to one embodiment of the present application; wherein, fig. 4 corresponds to the steps in fig. 1A-1F one by one. Fig. 3A-3I are schematic perspective views of a flexible three-dimensional integrated circuit structure according to one embodiment of the present application.
In the method according to the present application, the pretreatment of the support substrate thereof prior to the formation of the flexible material substrate (e.g., flexible PI substrate) is not described in detail in the steps without any particular explanation.
In some embodiments, the support substrate needs to be pre-treated to ensure that the flexible material substrate forms a film thereon and that the circuit can be nondestructively torn off the support substrate after the flexible material substrate has been completed.
As shown in fig. 4, step S401: forming a flexible substrate; the flexible substrate refers to the aforementioned first substrate;
by way of example, flexible substrates may include PEN, PET, and PI films, and the flexible substrate may be formed by a process that includes forming the film directly using commercially available films, or spin-on solutions.
In some embodiments, the flexible substrate is a flexible PI solution spin-coated on a support substrate comprising glass and silicon, and the flexible PI solution spin-coated on the support substrate is baked and cured into a PI film to obtain a flexible substrate 101 as shown in fig. 1A.
Step S402: a P-type transistor is formed on a flexible substrate.
Illustratively, the P-type transistor may include a carbon nanotube thin film transistor.
In some embodiments, as shown in fig. 1B and 3B-3E, metallic carbon nanotubes may be spin coated on a flexible substrate 101 as a forming material for a first source electrode and a first drain electrode (alternatively referred to as a source drain electrode, where the first definition is a distinction, for representing a source drain electrode that is a P-type transistor), patterned by photolithography and plasma etching. Subsequently, a semiconductor carbon nanotube is spin-coated and patterned to form a channel region of the P-type transistor, otherwise referred to as a first channel region, in the same manner as the source-drain electrode of the P-type transistor. By ALD the gate dielectric layer of a P-type transistor (e.g., al 2 O 3 A PI mixed material) is deposited on the channel layer (or first channel region) of the formed P-type transistor and patterned by photolithography and wet etching at 70 c with phosphoric acid. Subsequently deposited by magnetron sputtering and patterned by stripping to form the gate of the P-type transistorA pole or gate electrode. The power of the magnetron sputtering is 100W for 6.5mins and the thickness of the deposited ITO is 80nm, and then the device is placed in acetone for ultrasonic treatment, photoresist is removed, and ITO over the photoresist is removed to form a gate electrode of the transistor, thereby forming a P-type transistor 102.
Other modes such as ink jet printing or other material systems may be used in some embodiments to form the P-type transistor, so long as the patterning mode and the choice of materials are compatible with the flexible substrate, and are not particularly limited.
Step S403: depositing a gate dielectric layer of the N-type transistor; in which the P-type transistor and the N-type transistor share a gate, as shown in fig. 1C and 3F, an oxide insulating layer is deposited on the gate electrode of the P-type transistor as the gate dielectric layer 103 of the N-type transistor (which may be referred to as a second gate dielectric layer for the purpose of distinguishing the gate dielectric layers of the P-type transistor).
In some embodiments, the gate dielectric layer may be formed of a material including Al 2 O 3 PI blend material. In this embodiment, the deposition and etching manner of the layer material is the same as the formation manner of the gate dielectric layer in the P-type transistor, and will not be described herein.
Step S404: forming a channel region 104 of an N-type transistor. For example, the second channel region of the N-type transistor (or the channel layer of the N-type transistor) may include a metal oxide a-IGZO.
In some embodiments, as shown in FIGS. 1D and 3G, a metal oxide a-IGZO channel layer is deposited on the second gate dielectric layer Al by DC magnetron sputtering 2 O 3 On the/PI mixed material, the sputtering power was 120W and the sputtering time was 200s to achieve a thickness of 20nm for the metal oxide a-IGZO channel layer. And then, etching the metal oxide a-IGZO channel layer by a wet etching mode through a mixed solution of 36% of dilute hydrochloric acid and 50:1 of deionized water to remove a-IGZO outside the channel region so as to realize patterning. In some embodiments, other semiconductor materials known to those skilled in the art may be used as the trenches for the N-type transistorsThe channel layer is not limited as long as the deposition and patterning process is compatible with the underlying existing materials and does not degrade the performance of the formed P-type transistor.
Step S405: the gate dielectric layer of the N-type transistor is patterned to leak out the source-drain electrode of the underlying P-type transistor. The patterning may include wet etching, for example.
In some embodiments, as shown in FIGS. 1E and 3H, the gate dielectric layer Al of the N-type transistor is patterned after the formation of the channel layer a-IGZO 2 O 3 The PI mixture can reduce the interface state formation between the channel layer and the gate dielectric layer of the N-type transistor. The etching mode is identical to the etching mode of the grid dielectric layer in the P-type transistor.
Step S406: a source-drain electrode 106 of the N-type transistor is formed. Illustratively, the N-type transistor source drain electrode may comprise metallic ITO. In some embodiments, the drain electrode of the N-type transistor needs to be connected to the drain electrode of the underlying P-type transistor to form the output of the inverter.
In some embodiments, as shown in fig. 1D and 3I, the source-drain electrode ITO is formed in the same manner as the gate electrode of the P-type transistor in step 402, and will not be described here again. Of course, other metal materials may be used as the source/drain electrode forming material on the premise of ensuring a work function match with the channel layer material, and any other material known to those skilled in the art may be used, and this is not a limitation.
The integrated circuit prepared by the preparation method of the flexible three-dimensional integrated circuit structure provided by the embodiment has excellent mechanical flexibility and stable performance.
Embodiments of the present application also provide a flexible three-dimensional inverter comprising:
a first substrate;
the P-type transistor is positioned on the first substrate and comprises a first source electrode, a first drain electrode, a first channel region, a first grid dielectric layer and a grid electrode, wherein the first source electrode and the first drain electrode are respectively positioned on two sides of the first channel region, and the first grid dielectric layer and the grid electrode are sequentially positioned on the first source electrode, the first channel region and the first drain electrode; the first channel region of the P-type transistor is formed by a material at least comprising a semiconducting carbon nanotube, and the first source electrode and the first drain electrode are formed by a material at least comprising a metallic carbon nanotube;
the oxide insulating layer is positioned on the P-type transistor, and the oxide insulating layer is a second grid dielectric layer of the N-type transistor;
a second channel region of the N-type transistor on the second gate dielectric layer;
and the second drain electrode is connected with the first drain electrode of the P-type transistor below to form an output end of the inverter.
In some embodiments, the gate is formed of a material including at least metallic ITO, and the first gate dielectric layer and the second gate dielectric layer are formed of a material including at least Al 2 O 3 Mixing with PI.
In some embodiments, the first substrate is formed of a flexible film; the first substrate has a thickness of 10-15 μm.
In some embodiments, the first substrate is a PI film.
In some embodiments, a flexible PI solution is first spin coated on a support substrate comprising glass, and then baked to cure the PI film formed, and the thickness of the PI film is controlled by controlling the spin speed of the spin coating.
In some embodiments, the second channel region of the N-type transistor is formed of a material including at least a-IGZO, and the second source electrode, the second drain electrode, and the gate material include at least metallic ITO.
FIG. 5 is a schematic diagram of a structure of a flexible three-dimensional inverter according to one embodiment of the present application; the schematic structure of the flexible three-dimensional inverter further comprises a stacked structure cross-section SEM and a partial enlarged view. As shown in fig. 5, the inverter is prepared by adopting a structure of common gate and common drain of two types of transistors. The materials of the layers in the structures disclosed herein include, but are not limited to, the materials shown in fig. 5.
Embodiments of the present application provide an integrated circuit comprising a flexible three-dimensional inverter as any one of the above.
The flexible three-dimensional inverter and the integrated circuit can realize the technical effects realized by the preparation method of the flexible three-dimensional integrated circuit structure, and are not repeated here.
FIG. 6A is a bending state diagram of a flexible inverter fabricated by a method of fabricating a flexible three-dimensional integrated circuit structure according to one embodiment of the present application; fig. 6B is a graph illustrating performance of a flexible inverter fabricated by a method for fabricating a flexible three-dimensional integrated circuit structure according to an embodiment of the present invention with different bending conditions.
The integrated circuit prepared by the method has excellent mechanical flexibility, and the electrical characteristics of the integrated circuit do not show obvious attenuation after being bent for different times under the bending condition shown in fig. 6A. As shown in fig. 6B, curve 601 is an electrical characteristic diagram obtained by testing after the preparation of the inverter, and curves 602 and 603 are electrical characteristic diagrams after the inverter is bent 3000 times and 6000 times, respectively, under the condition that the bending radius is 500 μm. As can be clearly seen from the curves in the figure, the variation amplitude between the curves is small under the condition of different bending times.
The integrated circuit structure and the preparation method integrate the P-type carbon nano tube transistor and the N-type a-IGZO transistor in a vertical stacking mode to form the flexible three-dimensional inverter. Wet etching of gate dielectric layers is proposed to achieve a common gate and common drain structure. The flexible three-dimensional integrated circuit has the characteristic of high mechanical flexibility on the premise of ensuring high integration density of the circuit by adopting the structure. The flexible three-dimensional inverter prepared by the method still maintains excellent electrical performance after 6000 times of bending under the condition that the bending radius is 500 mu m.
The preparation method of the flexible three-dimensional integrated circuit structure, the inverter and the integrated circuit have higher mechanical flexibility than an integrated circuit (such as a traditional inverter) adopting a traditional three-dimensional structure design, and the performance of the integrated circuit structure after bending under severe bending conditions is not obviously reduced; and has a lower delay time; the manufacturing method of the integrated circuit is simple, and the integrated circuit has strong adaptability and convenience for mass production of flexible integrated circuits in the future.
The preparation method of the flexible three-dimensional integrated circuit structure, the inverter and the integrated circuit provided by the application provide a new design structure, and the method can realize high mechanical flexibility simultaneously on the premise of ensuring high density of the integrated circuit, even after the flexible three-dimensional integrated circuit structure is bent under severe bending conditions, the electrical characteristics of the inverter prepared by the preparation method of the flexible three-dimensional integrated circuit structure are not obviously reduced, the high flexibility of the inverter and the integrated circuit is maintained, and the technical effects of ensuring the stability performance of the inverter and the integrated circuit and reducing time delay are realized.
The application also provides a memory comprising a memory array and a control circuit, wherein the memory cell circuit in the memory array and the control circuit comprise an integrated circuit as described in any one of the preceding.
The above embodiments are provided for illustrating the present application and are not intended to limit the present application, and various changes and modifications can be made by one skilled in the relevant art without departing from the scope of the present application, therefore, all equivalent technical solutions shall fall within the scope of the present disclosure.

Claims (10)

1. A method of fabricating a flexible three-dimensional integrated circuit structure, the method comprising:
providing a first substrate;
spin-coating metallic carbon nanotubes as a forming material of a source electrode and a drain electrode on the first substrate, patterning to form a first source electrode and a first drain electrode of a P-type transistor, spin-coating a forming material of a semiconductor carbon nanotube as a channel region on the first substrate between the first source electrode and the first drain electrode, patterning to form a first channel region of the P-type transistor, depositing a first gate dielectric layer of the P-type transistor on the first channel region, depositing a gate layer on the first gate dielectric layer, and patterning to form a gate of the P-type transistor;
depositing an oxide insulating layer on the P-type transistor, wherein the oxide insulating layer is a second gate dielectric layer of the N-type transistor;
depositing a metal oxide a-IGZO on the second grid dielectric layer in a DC magnetron sputtering mode to form a metal oxide a-IGZO channel layer, and removing the metal oxide a-IGZO channel layer outside a second channel region in a first wet etching mode to form the second channel region of the N-type transistor;
etching the first gate dielectric layer and the second gate dielectric layer in a second wet etching mode to expose the first source electrode and the first drain electrode of the P-type transistor; and
and forming a second source electrode and a second drain electrode of the N-type transistor on two sides of the second channel region respectively, wherein the second drain electrode is connected with the first drain electrode of the P-type transistor below to form an output end of the inverter.
2. The method of manufacturing a flexible three-dimensional integrated circuit structure of claim 1,
the DC magnetron sputtering mode adopts sputtering power of 120W and sputtering time of 200s, so that the thickness of the metal oxide a-IGZO channel layer is 20nm;
the first wet etching mode adopts a mixed solution of 36% of dilute hydrochloric acid and 50:1 of deionized water.
3. The method of manufacturing a flexible three-dimensional integrated circuit structure of claim 1,
spin-coating a flexible material solution on a support substrate comprising glass, and baking and curing the flexible material solution on the support substrate to form a film, thereby forming the first substrate.
4. The method of claim 1, wherein the first substrate, the first gate dielectric layer, the second gate dielectric layer, the first channel region, the second channel region, the first source electrode, and the first drain electrode are all formed of a flexible material.
5. The method of manufacturing a flexible three-dimensional integrated circuit structure according to claim 1 or 4, wherein the first substrate comprises flexible PEN, PET, or PI.
6. The method of claim 1, wherein the gate electrode is formed of a material comprising at least metal ITO, and the first gate dielectric layer and the second gate dielectric layer are formed of a material comprising at least Al 2 O 3 Mixing with PI.
7. The method of fabricating a flexible three-dimensional integrated circuit structure according to claim 1, wherein forming the gate of the P-type transistor by photolithography comprises: setting the power of magnetron sputtering as 100W, the time as 6.5mins, depositing an ITO layer with the thickness of 80nm, performing ultrasonic treatment in acetone, and removing photoresist and the ITO layer above the photoresist to form the grid electrode.
8. A flexible three-dimensional inverter, the flexible three-dimensional inverter comprising:
a first substrate;
the P-type transistor is positioned on the first substrate and comprises a first source electrode, a first drain electrode, a first channel region, a first gate dielectric layer and a gate electrode, wherein the first source electrode and the first drain electrode are respectively positioned on two sides of the first channel region, and the first gate dielectric layer and the gate electrode are sequentially positioned on the first source electrode, the first channel region and the first drain electrode; wherein, the forming material of the first channel region of the P-type transistor at least comprises a semiconducting carbon nanotube, and the forming material of the first source electrode and the first drain electrode at least comprises a metallic carbon nanotube;
the oxide insulating layer is positioned on the P-type transistor and is a second gate dielectric layer of the N-type transistor;
a second channel region of the N-type transistor on the second gate dielectric layer;
and the second drain electrode is connected with the first drain electrode of the P-type transistor below to form an output end of the inverter.
9. The flexible three-dimensional inverter of claim 8, wherein the gate is formed of a material comprising at least metallic ITO, and the first gate dielectric layer and the second gate dielectric layer are formed of a material comprising at least Al 2 O 3 Mixing with PI.
10. An integrated circuit comprising a flexible three-dimensional inverter as claimed in any one of claims 8-9.
CN202311326159.8A 2023-10-13 2023-10-13 Preparation method of flexible three-dimensional integrated circuit structure, inverter and integrated circuit Pending CN117279462A (en)

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