CN109300911B - AND/OR logic gate circuit based on two-dimensional semiconductor heterojunction and implementation and preparation method thereof - Google Patents
AND/OR logic gate circuit based on two-dimensional semiconductor heterojunction and implementation and preparation method thereof Download PDFInfo
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Abstract
The invention discloses an AND/or logic gate circuit based on a two-dimensional semiconductor heterojunction and an implementation and preparation method thereof. Two-dimensional semiconductor heterogeneous PN junctions with one-way conductivity are connected in parallel and matched with a fixed resistor, and then the AND/or logic function can be realized. The direction of the one-way conductivity of the two-dimensional semiconductor heterojunction is adjusted through the change of the gate voltage, so that the change from the PN junction to the NP junction is realized. When the two-dimensional semiconductor heterojunction is in different unidirectional conduction directions, an AND logic function or a logic function can be realized respectively, namely, the AND/or logic conversion can be realized by changing the gate voltage. The device has simple preparation process and easy circuit realization, greatly reduces the circuit area and can realize large-scale integration.
Description
Technical Field
The invention belongs to the technical field of nanoelectronics, and particularly relates to a method for realizing and/or logic gate circuits of two-dimensional semiconductor heterojunctions and a preparation method thereof.
Background
Two-dimensional materials have many interesting physical and chemical properties, making them the leading focus of international material science research. They are diverse and complementary in nature, ranging from conductors, semiconductors to insulators, including graphene, transition metal dichalcogenides, black phosphorus, and boron nitride, among others. In the field of electronic devices, in recent years, two-dimensional semiconductor materials can realize ideal gate control due to the atomic-level thickness thereof, and the two-dimensional semiconductor materials have a larger forbidden band width and can inhibit source-drain tunneling current, so that the two-dimensional semiconductor materials become a very promising semiconductor material in the later molarity, and particularly have great application potential in the low-power consumption field in the future. In addition, due to its excellent optical, electronic, mechanical properties, etc., there are many applications including photoelectric devices, flexible devices, etc. Meanwhile, due to the potential of mass production, a circuit based on full two-dimensional material integration is expected to become a reality in the future, and researchers are concerned more and more about devices based on two-dimensional semiconductor materials and related circuits. At present, for logic circuit application, research has been conducted on implementing an inverter by using a two-dimensional semiconductor material and a heterojunction thereof, and the inverter is the most basic logic gate in a logic circuit. It is not sufficient to implement only the basic inverter for future circuits based on fully two-dimensional semiconductor materials, while and gates, or gates, and or gates need to be considered. There is no research in the related direction, which is a problem to be solved urgently in the future two-dimensional semiconductor material circuit application.
Disclosure of Invention
The invention aims to provide a realization and preparation method of an AND/or logic gate circuit based on a two-dimensional semiconductor heterojunction. In the invention, two different two-dimensional semiconductor materials are adopted to form a heterojunction, and the two heterojunctions share one port. Due to the fact that the two-dimensional semiconductor materials are different in work function, doping concentration and the like, a PN junction can be formed after the two-dimensional semiconductor materials are contacted, and the PN junction has one-way conductivity. Two PN junctions with one-way conductivity are connected in parallel, and then the use of a resistor is matched, so that the AND/or logic function can be realized. The two-dimensional semiconductor material can be electrically doped through the grid voltage due to the fact that the two-dimensional semiconductor material is thin, so that the doping type of the two-dimensional semiconductor material is changed. When the two-dimensional semiconductor heterojunction is in different unidirectional conduction directions, an AND logic function or a logic function can be realized respectively, namely, the AND/or logic conversion can be realized by changing the gate voltage.
Specifically, the technical scheme of the invention is as follows:
an AND/or logic gate circuit based on two-dimensional semiconductor heterojunction comprises a two-dimensional semiconductor heterojunction device and an external fixed resistor, wherein: the two-dimensional semiconductor heterojunction device comprises an insulating substrate and a first two-dimensional semiconductor material on the insulating substrate; a second two-dimensional semiconductor material and a third two-dimensional semiconductor material are respectively arranged above the first two-dimensional semiconductor material at two ends to form longitudinal stacking with the first two-dimensional semiconductor material, two heterogeneous PN junctions with the same one-way conductivity direction are formed, and the second two-dimensional semiconductor material and the third two-dimensional semiconductor material are not connected with each other; the electrode shared by the two heterogeneous PN junctions is positioned above the first two-dimensional semiconductor material, and the non-shared electrode is respectively positioned above the second two-dimensional semiconductor material and the third two-dimensional semiconductor material; the external fixed resistor is connected with an electrode shared by the two heterogeneous PN junctions.
The second two-dimensional semiconductor material and the third two-dimensional semiconductor material may be the same or different. The second two-dimensional semiconductor material and the third two-dimensional semiconductor material are different from the first two-dimensional semiconductor material in work function, doping concentration and the like, so that a PN junction is formed after the two-dimensional semiconductor materials are contacted, and the PN junction has unidirectional conductivity.
The first, second and third two-dimensional semiconductor materials may be selected from the following materials: WSe2、SnS2、MoS2、MoSe2、WS2、SnSe2、WTe2And the PN junction formed by the first two-dimensional semiconductor material and the second two-dimensional semiconductor material has the same unidirectional conductivity direction as the PN junction formed by the first two-dimensional semiconductor material and the third two-dimensional semiconductor material. In one embodiment of the invention, the first two-dimensional semiconductor material is WSe2The second two-dimensional semiconductor material is SnS2The third two-dimensional semiconductor material is MoS2。
The thicknesses of the first two-dimensional semiconductor material, the second two-dimensional semiconductor material and the third two-dimensional semiconductor material are all preferably between 1nm and 10 nm.
In the above and/or logic gate circuit based on two-dimensional semiconductor heterojunction, the insulating substrate of the two-dimensional semiconductor heterojunction device has an insulating layer, and the material of the insulating layer can be selected from SiO2Conventional insulators such as high-k insulating media, or two-dimensional material insulators such as BN.
In the two-dimensional semiconductor heterojunction device, the gate electrode may be located on the back surface of the insulating substrate, or a top gate structure may be adopted, that is, a layer of insulating gate dielectric is grown above the PN junction, and the gate electrode is located above the insulating dielectric.
In the two-dimensional semiconductor heterojunction device, the electrode shared by the two heterojunction PN junctions and the non-shared electrode are generally metal electrodes, and the metal electrodes are required to have good adhesion with the two-dimensional semiconductor material and to form ohmic contact. The three metal electrodes may be made of the same or different materials, and are preferably made of a metal such as Ni, Au, or Pt, or a mixed metal such as Pd/Au, Ti/Au, or Ti/Ni.
The device adopts the two-dimensional semiconductor material, and the doping type of the device can be electrically regulated through the grid voltage, so that the change of the one-way conduction direction of the two-dimensional semiconductor heterojunction from PN to NP can be realized, and the conversion of logic function can be realized after the device is externally connected with a resistor.
As shown in FIG. 1, an electrode (Y end) shared by two hetero-PN junctions in the two-dimensional semiconductor heterojunction device is externally connected with a fixed resistor R1, and the other end of R1 is connected with a power supply voltage VDDAnd logic gate circuit is formed. The realization principle is as follows: when grid voltage VGWhen the voltage is negative, the first two-dimensional semiconductor material is electrically doped to be P-type under the action of the gate voltage, and the second and third two-dimensional semiconductor materials are in intrinsic state, i.e. I-type. At the moment, the heterojunction YA and the heterojunction YB are both of PI type, so when the Y end potential is higher than the A, B end potential, the PI junction is positively biased and presents conduction characteristic; when the Y end potential is lower than the A, B end potential, the PI junction is reversely biased and is in a cut-off state. The A, B port is used as the input of the AND gate, and the Y port is shared by two heterojunctions and used as the output of the AND gate. When the input of the port A, B is all low level 0, the two PI junctions are both in a positive bias conducting state, and the Y end is low level; when one of the A, B ports is at low level 0 and the other is at high level 1, the PI junction corresponding to the low level port is in a forward bias conducting state, the PI junction corresponding to the high level port is in a reverse bias cut-off state, and the Y end is still at low level; when the input of the port A, B is all high level 1, both PI junctions are in reverse bias cut-off state, and the Y terminal is high level. Thus, the AND logic function is realized.
As shown in FIG. 2, the electrode (Y end) shared by two hetero-PN junctions in the two-dimensional semiconductor heterojunction device is externally connected with a fixed resistor R2, and the other end of R2 is grounded VSSAnd forming an OR logic gate circuit. The realization principle is as follows: when grid voltage VGWhen the first two-dimensional semiconductor material is positive, the first two-dimensional semiconductor material is electrically doped to be N-type under the action of the grid voltage, and the second and the third two-dimensional semiconductor materialsThe vitamin semiconductor is in an intrinsic state, i.e., type I. At the moment, the heterojunction YA and YB are both of NI type, so when the Y end potential is higher than the A, B end potential, the NI junction is reversely biased and presents cut-off characteristics; when the Y end potential is lower than the A, B end potential, the NI junction is positively biased and takes on an off-on state. The A, B port is used as the input of the OR gate, and the Y port is shared by two heterojunctions and used as the output of the OR gate. When the input of the port A, B is all low level 0, the two NI junctions are both in a reverse bias cut-off state, and the Y end is low level; when one of the A, B ports is at a low level 0 and the other port is at a high level 1, the NI junction corresponding to the low level port is in a reverse bias cut-off state, the NI junction corresponding to the high level port is in a forward bias conducting state, and the Y end is at a high level; when the input of the port A, B is all high level 1, both NI junctions are in a forward biased conducting state, and the Y terminal is high level. Thus implementing an or logic function.
As shown in fig. 6, a PMOS transistor M1, an NMOS transistor M2, and two fixed resistors (R1 and R2) are externally connected to an electrode (Y terminal) common to two hetero PN junctions in the two-dimensional semiconductor heterojunction device, so as to form an and/or logic gate circuit that can be switched with each other. The PMOS transistor M1 and the NMOS transistor M2 share a gate electrode with the two-dimensional semiconductor heterojunction device. The drain terminal of the PMOS transistor M1 is connected with the common electrode (Y terminal) of the device, the source terminal is connected with the fixed resistor R1, and the other end of the resistor R1 is connected with the power supply voltage VDD. The drain terminal of the NMOS transistor M2 is connected to the common electrode (Y terminal) of the device, the source terminal is connected to the fixed resistor R2, and the other terminal of R2 is grounded VSS. The realization principle is as follows: when grid voltage VGWhen the voltage is negative, the PMOS transistor M1 is turned on, which can be regarded as a short circuit, and the NMOS transistor M2 is turned off, which can be regarded as an open circuit, and at this time, the circuit can be simplified to fig. 1 (a), and the and logic can be implemented. When grid voltage VGWhen the voltage is positive, the PMOS transistor M1 is in the off state and can be considered as open, and the NMOS transistor M2 is in the on state and can be considered as short, and at this time, the circuit can be simplified to fig. 2 (a), and the or logic can be realized.
The invention also provides a method for preparing the device for forming and/or logic gates based on the two-dimensional semiconductor heterojunction, which comprises the following steps:
(1) depositing a first two-dimensional semiconductor material on an insulating substrate by a method of Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD);
(2) photoetching to expose an area except for preparing a device, removing the first two-dimensional semiconductor material in the area except the device by a dry etching or wet etching method, and reserving the first two-dimensional semiconductor material for preparing the device;
(3) depositing a second two-dimensional semiconductor material on the insulating substrate and the first two-dimensional semiconductor material for preparing the device by a method of Chemical Vapor Deposition (CVD) or Atomic Layer Deposition (ALD);
(4) removing the second two-dimensional semiconductor material outside the device preparation area by adopting a photoetching and dry etching or wet etching method to obtain a second two-dimensional semiconductor material which is partially positioned on the insulating substrate and partially longitudinally stacked on the first two-dimensional semiconductor material;
(5) repeating the steps (3) and (4) to prepare a third two-dimensional semiconductor material on the first two-dimensional semiconductor material and the insulating substrate;
(6) and photoetching an area exposing the metal electrode, carrying out metal deposition on the whole piece of tape by means of electron beam evaporation and the like, and obtaining three metal electrodes by stripping, wherein one metal electrode is a common electrode positioned on the first two-dimensional semiconductor material, and the other two metal electrodes are non-common electrodes respectively positioned on the second two-dimensional semiconductor material and the third two-dimensional semiconductor material.
In the above preparation method, the quality of the first two-dimensional semiconductor material is ensured to be good by controlling the growth conditions of the second two-dimensional semiconductor material and the third two-dimensional semiconductor material in the steps (3) and (5), for example, the growth temperature is 50 ℃ to 100 ℃ lower than that of the first two-dimensional semiconductor material grown in the step (1).
In the above-mentioned preparation method, the materials of the metal electrodes in the step (6) may be the same or different, and it is necessary to select a metal that can form ohmic contact with the two-dimensional semiconductor material.
The invention has the following technical effects:
firstly, a basic AND/or logic gate circuit in a logic circuit is formed by adopting a two-dimensional semiconductor device, and the method has very important significance for future large-scale integrated circuits based on full two-dimensional materials.
The two-dimensional semiconductor material can realize ideal grid control due to the atomic-level thickness, has larger forbidden band width, can inhibit source-drain tunneling current and the like, becomes a semiconductor material with very promising future in the post-molar age, and particularly has great application potential in the field of low power consumption. The research of the circuit based on the full two-dimensional material integration is of great significance. At present, for logic circuit application, apart from the function of inverter realized by two-dimensional semiconductor material, the research of other basic logic gate circuits is still blank, and this is exactly the most basic requirement for realizing large-scale integrated circuit. The invention adopts the two-dimensional semiconductor device to realize the basic AND/or logic gate circuit, fills the research gap, and has very important significance for the future large-scale integrated circuit research based on the full two-dimensional semiconductor material.
And secondly, by adopting a two-dimensional semiconductor device, the change between and/or logics can be realized through the change of the grid voltage, and the method has great advantages for multiplexing devices and basic logic gates.
The invention adopts two-dimensional semiconductor material, the doping type of which can be electrically regulated by gate voltage, so that the change of the one-way conduction direction of the two-dimensional semiconductor heterojunction from PN to NP can be realized, and the conversion of logic function can be realized. In the traditional CMOS integrated circuit, basic AND/or logic gates are realized by combining NAND gates/NOR gates and inverters, at least 6 standard CMOS devices are needed, but one device can be realized, and the circuit area overhead is greatly reduced. In the invention, the change of logic function can be realized through the change of grid voltage, thereby greatly reducing the difficulty and complexity of the multiplexing of the basic logic gate and simultaneously saving the area expense brought by the control circuit and the conversion circuit.
And thirdly, the device is simple in preparation process, easy in circuit realization and has the potential of large-scale production.
The device utilizes an insulating material as a substrate, the whole device comprises three two-dimensional semiconductor materials and metal electrodes, the preparation process is simple, the function of a basic and/or logic gate can be realized by matching with an external fixed resistor, the device has very important significance for devices and circuits formed by the full two-dimensional semiconductor materials, and the device has the potential of large-scale production due to the formation of the full two-dimensional materials.
Drawings
Fig. 1 is a circuit diagram (a), an input-output waveform diagram (b), and a truth table (c) of the two-dimensional semiconductor heterojunction formation and logic gate of the present invention.
Fig. 2 is a circuit diagram (a), an input-output waveform diagram (b), and a truth table (c) of the two-dimensional semiconductor heterojunction-based or logic gate of the present invention.
Fig. 3 is a cross-sectional view (a) and a top view (b) of a two-dimensional semiconductor heterojunction-based device for forming and/or logic gates prepared in example 1 of the present invention.
Fig. 4 is a process flow diagram for preparing a two-dimensional semiconductor heterojunction-based device for forming and/or logic gates according to embodiment 1 of the present invention.
FIG. 5 shows the one-way conductivity of the two-dimensional semiconductor heterojunction when the gate voltage is in different bias states in the two-dimensional semiconductor heterojunction-based and/or logic gate circuit of embodiment 2 of the invention; wherein: (a) when the grid voltage is negative (V)G<0) Implementing and logic functions; (b) when the grid voltage is positive (V)G>0) Implementing or logical functions.
Fig. 6 is a circuit diagram of the present invention based on a two-dimensional semiconductor heterojunction to form switchable dual function and/or logic gates.
In the figure:
0-gate electrode
1-insulating substrate
2-first two-dimensional semiconductor material
3-second two-dimensional semiconductor Material
4-third two-dimensional semiconductor Material
A-first metal electrode
B-metal electrode
Y-metal electrode
Detailed Description
The invention is further illustrated by the following examples in conjunction with the accompanying drawings.
EXAMPLE 1 preparation of a device for forming and/or logic gates based on two-dimensional semiconductor heterojunctions
As shown in fig. 3, the device portion of the and/or logic gate circuit based on the two-dimensional semiconductor heterojunction of the present embodiment includes a gate electrode 0, an insulating substrate 1, a first two-dimensional semiconductor material 2 on the insulating substrate 1, a second two-dimensional semiconductor material 3 and a third two-dimensional semiconductor material 4 formed thereon in a longitudinal stack, a first metal electrode a located above the second two-dimensional semiconductor material 3, a second metal electrode B located above the third two-dimensional semiconductor material 4, and a third metal electrode Y located above the first two-dimensional semiconductor material 2.
The method of fabricating the device portion described above for implementing a two-dimensional semiconductor heterojunction with and/or logic gates is described below. As shown in fig. 4, the process steps are as follows:
1) to have 300nm SiO2Thin-film silicon wafer as insulating substrate 1 with Ti/Au metal as gate electrode 0 on its back surface, and growing WSe with thickness of 5nm at 400 deg.C by Chemical Vapor Deposition (CVD)2As the first two-dimensional semiconductor material layer 2, as shown in fig. 4 (a);
2) photoetching to expose the area outside the device, removing the first two-dimensional semiconductor material 2 in the area outside the device by a plasma etching method, and reserving the first two-dimensional semiconductor material 2 for preparing the device, as shown in (b) in fig. 4;
3) deposition of SnS with a thickness of 10nm on an insulating substrate 1 and on a first two-dimensional semiconductor material 2 for the preparation of a device, by means of Chemical Vapor Deposition (CVD)2As the second two-dimensional semiconductor material 3, the growth temperature was 350 ℃, as shown in (c) of fig. 4;
4) removing the second two-dimensional semiconductor material 3 outside the device preparation region by means of photolithography and plasma etching, as shown in fig. 4 (d);
5) repeating the steps 3) and 4) to prepare MoS with the thickness of 10nm on the first two-dimensional semiconductor material 2 and the insulating substrate2And is a third two-dimensional semiconductor material 4, the growth temperature is 300 ℃, as shown in fig. 4 (e);
6) the first metal electrode and the second metal electrode were patterned by photolithography, Ti/Au (10nm/50nm) was electron beam evaporated on the sample with the adhesive, and the first metal electrode a and the second metal electrode B were formed after stripping with acetone and cleaning with ethanol, as shown in fig. 4 (f).
7) And photoetching a third metal electrode (common electrode) pattern, performing electron beam evaporation on the glued sample to obtain Pd/Au (10nm/50nm), stripping with acetone and cleaning with ethanol to obtain a third metal electrode Y, and thus obtaining the two-dimensional semiconductor device for forming and/or logic, wherein the graph is shown in (g) in fig. 4.
EXAMPLE 2 AND/OR logic Gate implementation based on two-dimensional semiconductor heterojunction
The third metal electrode of the two-dimensional semiconductor heterojunction device prepared in example 1 is externally connected with a fixed resistor (R1 or R2) to form an AND/or logic gate circuit. When the logic function is realized, one end of the external fixed resistor R1 is connected with the common electrode of the device, namely the third metal electrode Y, and the other end is connected with the power supply voltage VDDAs shown in fig. 1; when realizing the logic function, one end of the external fixed resistor R2 is connected with the third metal electrode Y of the device, and the other end is grounded VSSAs shown in fig. 2.
For and logic, see fig. 1, 3 and 5 (a), the implementation process is as follows: when grid voltage VGWhen the value is negative, the first two-dimensional semiconductor material 2 is electrically doped to be P-type under the action of the gate voltage, and the second and third two-dimensional semiconductors are far away from the gate dielectric, so that the electrical doping effect is weaker, and therefore the two-dimensional semiconductor material can be considered to be in an intrinsic state, i.e. I-type. At this time, the heterojunction YA and YB are both PI type, so when the Y end potential is higher than A, B end potential, the PI junction is forward biased to present the on characteristic, when the Y potential is lower than A, B end potential, the PI junction is reverse biased to present the off state.To implement the and logic, the A, B port is used as an input to an and gate, and the Y port is shared by two heterojunctions and used as an output of the and gate. When the input of the port A, B is all low level 0, both PI junctions are in a forward biased conducting state, and the Y terminal is low level. When one of the A, B ports is at low level 0 and the other is at high level 1, the PI junction corresponding to the low level port is in a forward bias conducting state, the PI junction corresponding to the high level port is in a reverse bias cut-off state, and the Y end is still at low level. When the input of the port A, B is all high level 1, both PI junctions are in reverse bias cut-off state, and the Y terminal is high level. Thus, the AND logic function is realized.
For or logic, see fig. 2, fig. 3 and fig. 5 (b), the implementation process is as follows: when grid voltage VGWhen the value is positive, the first two-dimensional semiconductor material is electrically doped to be in an N type under the action of the gate voltage, and the second two-dimensional semiconductor and the third two-dimensional semiconductor are farther away from the gate dielectric, so that the electrical doping effect is weaker, and the second two-dimensional semiconductor and the third two-dimensional semiconductor can be considered to be in an intrinsic state, namely in an I type. At this time, both the heterojunction YA and YB are NI type, so when the Y potential is higher than A, B, the NI junction is reverse biased and exhibits the off characteristic, and when the Y potential is lower than A, B, the NI junction is forward biased and exhibits the off on state. To implement or logic, the A, B port is used as an input to an or gate, and the Y port is shared by two heterojunctions and used as an output of the or gate. When the input of the port A, B is all low 0, both NI junctions are in reverse bias off state, and the Y terminal is low. When one of the A, B ports is at low level 0 and the other is at high level 1, the NI junction corresponding to the low level port is in reverse bias off state, the NI junction corresponding to the high level port is in forward bias on state, and the Y terminal is at high level. When the input of the port A, B is all high level 1, both NI junctions are in a forward biased conducting state, and the Y terminal is high level. Thus implementing an or logic function.
EXAMPLE 3 implementation of bifunctional and/or logic Gate circuits based on two-dimensional semiconductor heterojunctions
The third metal electrode Y of the two-dimensional semiconductor heterojunction device prepared in example 1 is externally connected with a PMOS transistor M1, an NMOS transistor M2, and two fixed resistors R1 and R2 to form a dual-function and/or logic gate circuit. PMOS transistor M1 and NMOS transistor M2, and twoThe dimensional semiconductor heterojunction device shares a gate electrode. The drain terminal of the PMOS transistor M1 is connected with the common electrode of the device, namely the third metal electrode Y, the other end of the source terminal junction fixed resistor R1 and R1 is connected with a power supply voltage VDD. The drain of the NMOS transistor M2 is connected to the common electrode of the device, i.e. the third metal electrode Y, the source is connected to the fixed resistor R2, and the other end of R2 is grounded VSSAs shown in fig. 6.
For and logic, the implementation is as follows: when grid voltage VGWhen the voltage is negative, the PMOS transistor M1 is turned on, and can be considered as a short circuit, and the NMOS transistor M2 is turned off, and can be considered as an open circuit, and the circuit can be simplified as shown in fig. 1 (a), see fig. 1
For OR logic, the implementation is as follows: when grid voltage VGWhen the voltage is positive, the PMOS transistor M1 is turned off and can be considered as open, and the NMOS transistor M2 is turned on and can be considered as short, and the circuit can be simplified as shown in fig. 2 (a), with reference to fig. 2
Example 2, an implementation or logic may be achieved.
It is noted that the disclosed embodiments are intended to aid in further understanding of the invention, but those skilled in the art will appreciate that: various substitutions and modifications are possible without departing from the spirit and scope of the invention and appended claims. Therefore, the invention should not be limited to the embodiments disclosed, but the scope of the invention is defined by the appended claims.
Claims (7)
1. An AND/or logic gate circuit, characterized in that the AND/or logic gate circuit comprises a two-dimensional semiconductor heterojunction device, a PMOS transistor M1, an NMOS transistor M2, and two fixed resistors R1 and R2, wherein the two-dimensional semiconductor heterojunction device comprises an insulating substrate and a first two-dimensional semiconductor material on the insulating substrate; a second two-dimensional semiconductor material and a third two-dimensional semiconductor material are respectively arranged above the first two-dimensional semiconductor material and form longitudinal stacking with the first two-dimensional semiconductor material and form two heterogeneous PN junctions with the same one-way conductivity direction, and the second two-dimensional semiconductor materialThe material and the third two-dimensional semiconductor material are not connected with each other; the electrode shared by the two heterogeneous PN junctions is positioned above the first two-dimensional semiconductor material, and the non-shared electrode is respectively positioned above the second two-dimensional semiconductor material and the third two-dimensional semiconductor material; the PMOS transistor M1 and the NMOS transistor M2 share one gate electrode with the two-dimensional semiconductor heterojunction device; the drain terminal of the PMOS transistor M1 is connected with the common electrode of the two-dimensional semiconductor heterojunction device, the source terminal is connected with the fixed resistor R1, and the other end of the fixed resistor R1 is connected with the power supply voltage VDD(ii) a The drain terminal of the NMOS tube M2 is connected with the common electrode of the two-dimensional semiconductor heterojunction device, the source terminal is connected with the fixed resistor R2, and the other end of the fixed resistor R2 is grounded VSS。
2. The and/or logic gate of claim 1, wherein the first two-dimensional semiconductor material, the second two-dimensional semiconductor material, and the third two-dimensional semiconductor material are each selected from one of the following materials: WSe2、SnS2、MoS2、MoSe2、WS2、SnSe2And WTE2And the one-way conductivity direction of the PN junction formed by the first two-dimensional semiconductor material and the second two-dimensional semiconductor material is the same as that of the PN junction formed by the first two-dimensional semiconductor material and the third two-dimensional semiconductor material.
3. The and/or logic gate of claim 2, wherein the first two-dimensional semiconductor material is WSe2The second two-dimensional semiconductor material is SnS2The third two-dimensional semiconductor material is MoS2。
4. The AND/or logic gate of claim 1, wherein the first two-dimensional semiconductor material, the second two-dimensional semiconductor material, and the third two-dimensional semiconductor material are all 1nm to 10nm thick.
5. The and/or logic gate circuit of claim 1, wherein the gate electrode of the two-dimensional semiconductor heterojunction device is located on the back side of the insulating substrate, or a top gate structure is adopted, that is, an insulating gate dielectric is grown on the PN junction, and the gate electrode is located above the insulating dielectric.
6. The and/or logic gate circuit of claim 1, wherein the electrode common to both the heterogeneous PN junctions and the non-common electrode are metal electrodes and form an ohmic contact with the connected two-dimensional semiconductor material.
7. The method of implementing an AND/or logic gate circuit as claimed in any one of claims 1 to 6, wherein two non-common electrodes located above the second two-dimensional semiconductor material and the third two-dimensional semiconductor material are used as the input terminals of the gate, and an electrode common to two hetero-PN junctions is used as the output terminal of the gate; making the gate voltage V of the two-dimensional semiconductor heterojunction deviceGIf the value is negative, the AND logic function is realized; making the gate voltage V of the two-dimensional semiconductor heterojunction deviceGPositive values, the or logic function is implemented.
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