CN117279398A - Vertical electrolyte gate control transistor, electronic device, preparation method and operation method - Google Patents
Vertical electrolyte gate control transistor, electronic device, preparation method and operation method Download PDFInfo
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K10/00—Organic devices specially adapted for rectifying, amplifying, oscillating or switching; Organic capacitors or resistors having potential barriers
- H10K10/40—Organic transistors
- H10K10/46—Field-effect transistors, e.g. organic thin-film transistors [OTFT]
- H10K10/462—Insulated gate field-effect transistors [IGFETs]
- H10K10/491—Vertical transistors, e.g. vertical carbon nanotube field effect transistors [CNT-FETs]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
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- Thin Film Transistor (AREA)
Abstract
Embodiments of the present disclosure provide a vertical electrolyte gate controlled transistor, an electronic device, a method of manufacturing, and a method of operating. The vertical electrolyte gate control transistor includes a substrate, a source-drain stack, a channel layer, an electrolyte layer, and a gate. A source-drain stack disposed on the substrate in a direction perpendicular to a surface of the substrate, including source and drain stacked on each other and insulated from each other; the channel layer is respectively contacted with the side surface of the source electrode and the side surface of the drain electrode at least on the first side of the source electrode and the drain electrode; an electrolyte layer disposed outside the channel layer on at least a first side of the source-drain stack and at least partially in contact with the channel layer between the source and drain; the gate is spaced from the channel layer by an electrolyte layer at least on a first side of the source-drain stack and is at least partially in contact with the electrolyte layer between the source and drain. The vertical electrolyte gate control transistor has the characteristics of vertical structure, small device area and low power consumption, and can realize artificial neurons with ultra-high density and ultra-low energy consumption.
Description
Technical Field
Embodiments of the present disclosure relate to a vertical electrolyte gate control transistor, an electronic device, a method of manufacturing, and a method of operating.
Background
The brain is the highest level part of the biological nervous system, processing massive amounts of information in a highly efficient and low power consumption manner. The brain relies primarily on neurons and synapses for information transfer between neurons to effect the transfer and processing of information. Neurons are basic units for processing information of the cerebral nervous system, and can be used for receiving, integrating, filtering, storing, transmitting information and the like, so that various functional activities of a person are regularly performed to adapt to changes of internal and external environments, and the neurons have very abundant dynamic processes and very strong space-time information processing capability.
Inspired by biological neurons, artificial neuron devices are produced. The artificial neural component is the basis of a neuromorphic computing technology, and the neuromorphic computing technology can greatly improve the data processing capacity and reduce the energy consumption, so that the method is a feasible scheme for efficiently processing mass data in an intelligent society.
In order to simulate the large number of neurons and synapses in the brain, designed artificial neurons need to have low power consumption performance and small footprint. However, the existing artificial neural components are limited by materials and structures, and often have the problems of single function, large occupied area, high power consumption and the like, so that the overall processing capacity of the computing system is reduced. Therefore, development of small-sized low-power-consumption artificial neurons is important for development of future high-area and energy-efficient neuromorphic computing technologies.
Disclosure of Invention
At least one embodiment of the present disclosure provides a vertical electrolyte gate controlled transistor, the transistor comprising: a substrate; a source-drain stack disposed on the substrate in a direction perpendicular to a surface of the substrate, including source and drain electrodes stacked on each other and insulated from each other; a channel layer in contact with a side of the source and a side of the drain, respectively, at least on a first side of the source-drain stack; an electrolyte layer disposed outside the channel layer on at least the first side of the source-drain stack and at least partially in contact with the channel layer between the source and the drain; a gate is spaced from the channel layer by the electrolyte layer at least on the first side of the source-drain stack and is at least partially in contact with the electrolyte layer between the source and the drain.
For example, in a vertical electrolyte gated transistor provided in at least one embodiment of the present disclosure, the channel layer is in contact with the sides of the source and the drain on the first and second sides of the source-drain stack, respectively; the electrolyte layer is disposed outside the channel layer on the first side and the second side of the source-drain stack, respectively, and is at least partially in contact with the channel layer between the source and the drain; the gate is spaced from the channel layer by the electrolyte layer and is at least partially in contact with the electrolyte layer between the source and the drain on the first side and the second side of the source-drain stack, respectively, wherein the second side is opposite the first side.
For example, in a vertical electrolyte gate control transistor provided in at least one embodiment of the present disclosure, the gate includes a first gate and a second gate, and the first gate and the second gate are disposed in parallel on the source-drain stack.
For example, in a vertical electrolyte gated transistor provided in at least one embodiment of the present disclosure, the channel layer and the electrolyte layer include the same pattern as the gate on the source drain stack.
For example, in a vertical electrolyte gate transistor provided in at least one embodiment of the present disclosure, the source-drain stack includes an insulating layer disposed between and on the source and drain in a direction perpendicular to a surface of the substrate.
For example, in a vertical electrolyte gated transistor provided in at least one embodiment of the present disclosure, the insulating layer is thickThe degree is 5-100nm; the material of the insulating layer comprises SiO 2 ，Si 3 N 4 ，Al 2 O 3 Or HfO 2 。
For example, in a vertical electrolyte gate control transistor provided in at least one embodiment of the present disclosure, the channel layer thickness is 5-20nm; the material of the channel layer comprises alpha-Si, inZnO and LiCoO 2 ，Li x TiO 2 ，VO 2 Or NbO x 。
For example, in a vertical electrolyte gated transistor provided in at least one embodiment of the present disclosure, the electrolyte layer thickness is 5-30nm; the electrolyte layer comprises chitosan, ionic gel, perfluorosulfonic acid, liClO 4 /PEO，Li x SiO y ，Li x TiO y LiPON or SiO 2 H, wherein x and y represent stoichiometric ratios.
At least one embodiment of the present disclosure also provides an electronic device comprising any of the vertical electrolyte gated transistors as described above.
At least one embodiment of the present disclosure also provides a method for preparing any of the vertical electrolyte gated transistors described above, the method comprising: forming a source-drain stack including source and drain stacked and insulated from each other on a substrate in a direction perpendicular to a surface of the substrate; forming a channel layer on at least a first side of the source-drain stack in contact with a side of the source and a side of the drain, respectively; an electrolyte layer formed at least partially in contact with the channel layer between the source and the drain, at least outside the channel layer on the first side of the source-drain stack; a gate is formed on at least the first side of the source-drain stack spaced from the channel layer by the electrolyte layer and at least partially in contact with the electrolyte layer between the source and the drain.
For example, the preparation method provided in at least one embodiment of the present disclosure further includes: further forming the channel layer on a second side of the source-drain stack in contact with a side of the source and a side of the drain, respectively; further forming the electrolyte layer between the source and the drain at least partially in contact with the channel layer outside the channel layer on the second side of the source-drain stack; the gate electrode is further formed on the second side of the source-drain stack spaced apart from the channel layer by the electrolyte layer and at least partially in contact with the electrolyte layer between the source and the drain, wherein the second side is opposite the first side.
For example, in the method for manufacturing at least one embodiment of the present disclosure, the gate includes a first gate and a second gate formed in parallel on the source-drain stack.
For example, in a method of manufacturing provided in at least one embodiment of the present disclosure, the channel layer and the electrolyte layer and the gate electrode include the same pattern on the source-drain stack.
At least one embodiment of the present disclosure also provides a method of operation for a vertical electrolyte gated transistor as described above, the method comprising: applying a first input voltage to the first gate and a second input voltage signal to the second gate, wherein the first input voltage and the second input voltage are different signals; grounding one of the source and the drain; an output current signal is obtained from the other of the source and the drain.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the following brief description of the drawings of the embodiments will make it apparent that the drawings described below relate only to some embodiments of the present disclosure and are not limiting of the present disclosure.
FIG. 1 is a schematic diagram of a biological neuron unit;
fig. 2A is a schematic structural diagram of a vertical electrolyte gate transistor according to an embodiment of the present disclosure;
fig. 2B is a schematic structural diagram of a vertical electrolyte gate transistor according to another embodiment of the present disclosure;
fig. 3A is a schematic diagram of a method for manufacturing a vertical electrolyte gate transistor according to an embodiment of the disclosure;
fig. 3B is a schematic diagram of a method for manufacturing a vertical electrolyte gate transistor according to an embodiment of the disclosure;
fig. 3C is a schematic diagram of a method for manufacturing a vertical electrolyte gate transistor according to an embodiment of the disclosure;
fig. 4 is a schematic diagram of an operation method of a vertical electrolyte gate control transistor according to an embodiment of the disclosure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present disclosure. It will be apparent that the described embodiments are some, but not all, of the embodiments of the present disclosure. All other embodiments, which can be made by one of ordinary skill in the art without the need for inventive faculty, are within the scope of the present disclosure, based on the described embodiments of the present disclosure.
Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this disclosure belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Likewise, the terms "a," "an," or "the" and similar terms do not denote a limitation of quantity, but rather denote the presence of at least one. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.
FIG. 1 is a schematic diagram of a biological neuron unit.
As shown in fig. 1, neurons include cell bodies, dendrites, and axons, and cell bodies have the function of communicating and integrating input information and transmitting information; the dendrite is used for receiving impulses transmitted by other neuron axons and transmitting the impulses to cell bodies; the axon acts to receive external stimuli and is then transported out of the cell body. The axons, except for the lateral branches, form branch-like nerve endings at their ends.
The electrolyte gate control transistor is capable of reproducing various functions of biological neurons, such as dendrite integration, orientation adjustment, and neuron gain control functions. The structure is similar to that of a conventional field effect transistor, except that an electrolyte gate transistor is used which contains mobile ions (e.g., H + 、Li + And O 2- Etc.) replaces silicon dioxide as the gate dielectric layer. Under the action of the gate voltage, movable electrolyte ions migrate to the electrolyte/channel interface and induce charges with opposite polarities on one side of the channel of the electrolyte/channel interface through electrostatic induction, so that the conductivity of the channel is increased or reduced. After the grid voltage is removed, electrolyte ions accumulated at the interface of the electrolyte and the channel migrate to the inside of the electrolyte under the action of the built-in electric field and the concentration gradient, and meanwhile, charges which are originally induced and generated in the channel gradually start to disappear, so that the conductivity of the channel is finally restored to an initial state. Since the neuron is a multiple-input single-output information processing unit, in addition to the basic simulation of the function of the neuron based on the operation mechanism of the electrolyte gate control transistor, the simulation of the function of the neuron is more abundant, and the electrolyte gate control transistor with a multiple-gate structure is required.
The inventors of the present disclosure have noted that existing multi-gate electrolyte gate-controlled transistors are typically based on a coplanar structure, i.e. the gate, source and drain of the transistor are in the same plane, taking up a large area and thus causing too high energy overhead, and this problem is particularly pronounced in the case of multiple gates.
At least one embodiment of the present disclosure provides a vertical electrolyte gate controlled transistor including a substrate, a source-drain stack, a channel layer, an electrolyte layer, and a gate. A source-drain stack disposed on the substrate in a direction perpendicular to a surface of the substrate, including source and drain stacked on each other and insulated from each other; the channel layer is respectively contacted with the side surface of the source electrode and the side surface of the drain electrode at least on the first side of the source electrode and the drain electrode; an electrolyte layer disposed outside the channel layer on at least a first side of the source-drain stack and at least partially in contact with the channel layer between the source and drain; the gate is spaced from the channel layer by an electrolyte layer at least on a first side of the source-drain stack and is at least partially in contact with the electrolyte layer between the source and drain.
The vertical electrolyte gate control transistor disclosed by the embodiment of the disclosure has the characteristics of vertical structure, small device area and low power consumption, can realize artificial neurons with ultra-high density and ultra-low energy consumption, and provides a basis for the nerve morphology calculation technology with high area and energy efficiency.
Fig. 2A is a schematic structural diagram of a vertical electrolyte gate transistor according to an embodiment of the disclosure.
As shown in fig. 2A, the vertical electrolyte gate controlled transistor 100 includes a substrate 101, a source-drain stack 102, a channel layer 103, an electrolyte layer 104, and a gate 105.
In this vertical electrolyte gate transistor 100, a source-drain stack 102 is provided on a substrate 101 in a direction perpendicular to the surface of the substrate 101, including a source 1021 and a drain 1022 stacked on each other and insulated from each other. In some examples, the material of the source 1021 and the drain 1022 may include a conductive material of titanium nitride (TiN), polysilicon (Poly-Si), amorphous silicon (α -Si), tungsten (W), tantalum (Ta), etc., and the thickness of the source 1021 and the drain 1022 may be, for example, 5-60nm, as the embodiments of the present disclosure are not limited thereto.
It should be noted that, although the case where the source electrode 1021 is below the drain electrode 1022 in the direction perpendicular to the surface of the substrate 101 is illustrated in fig. 2A, embodiments of the present disclosure are not limited thereto, and for example, the source electrode 1021 may be above the drain electrode 1022, which is not limited thereto by the present disclosure.
In the vertical electrolyte gate control transistor 100, source and drain stacksLayer 102 has a first side and a second side, the first side and the second side being opposite. The channel layer 103 is in contact with the sides of the source 1021 and the drain 1022, respectively, on a first side of the source drain stack 102, e.g., the channel layer 103 is disposed on the first side of the source drain stack 102, e.g., also at least partially on the top layer of the source drain stack 102, from the bottom layer to the top layer of the source drain stack 102 in a direction perpendicular to the surface of the substrate 101 as shown in fig. 2A. In some examples, the material of the channel layer 103 may include amorphous silicon (α -Si), indium zinc oxide (InZnO), lithium cobaltate (LiCoO) 2 ) Lithium titanate (Li) x TiO 2 ) Vanadium dioxide (VO) 2 ) Niobium oxide (NbO) x ) Such materials, but are not limited to the above materials, other semiconductor materials compatible with CMOS processes may be used, and the thickness of the channel layer 103 may be, for example, 5-20nm, as embodiments of the present disclosure are not limited thereto.
In this vertical electrolyte gate controlled transistor 100, the electrolyte layer 104 is arranged outside the channel layer 103 on the first side of the source drain stack 102 and at least partly in contact with the channel layer between the source 1021 and the drain 1022, thereby functioning as a gate insulation layer between the source 1021 and the drain 1022, e.g. the electrolyte layer 104 is arranged on the first side of the source drain stack 102 from bottom to top of the source drain stack 102 in a direction perpendicular to the surface of the substrate 101 as shown in fig. 2A, e.g. also at least partly on the top layer of the source drain stack 102. In some examples, the material of the electrolyte layer 104 may include chitosan, ionic gel, perfluorosulfonic acid, lithium perchlorate/polyethylene oxide (LiClO) 4 PEO), lithium silicate (Li x SiO y ) Lithium titanate (Li) x TiO y ) Lithium phosphorus oxynitride (LiPON), hydrogenated silicon dioxide (SiO 2 H), etc., where x, y represent the stoichiometric ratio, but are not limited to the above materials, the thickness of the electrolyte layer 104 may be, for example, 5-30nm, as the embodiments of the present disclosure are not limited in this regard. In some examples, a method comprising moving ions (e.g., H + 、Li + And O 2- Etc.) is capable of achieving high conductivity at low voltages, thereby providing the vertical electrolyte gate control transistor with lower workConsumption and efficient energy conversion efficiency.
In this vertical electrolyte gated transistor 100, the gate 105 is spaced apart from the channel layer 103 by the electrolyte layer 104 on a first side of the source drain stack 102 and is at least partially in contact with the electrolyte layer 104 between the source 1021 and the drain 1022, thereby exerting control over the channel layer between the source 1021 and the drain 1022, e.g. the gate 105 is arranged on the first side of the source drain stack 102 from bottom to top of the source drain stack 102 in a direction perpendicular to the surface of the substrate 101, e.g. also at least partially on the top layer of the source drain stack 102, as shown in fig. 2A. In some examples, the material of the gate electrode 105 may include conductive materials such as titanium nitride (TiN), polysilicon (Poly-Si), palladium (Pd), titanium/platinum (Ti/Pt), tungsten (W), or titanium/gold (Ti/Au), but is not limited to the above materials, and the thickness of the gate electrode 105 may be, for example, 20-100nm, as the embodiments of the present disclosure are not limited thereto.
Although fig. 2A shows the case where the channel layer 103, the electrolyte layer 104, and the gate electrode 105 are disposed on only one side of the source-drain stack 102, embodiments of the present disclosure are not limited thereto, and for example, the channel layer 103, the electrolyte layer 104, and the gate electrode 105 may be disposed on opposite sides of the source-drain stack 102, which is not limited thereto.
In the vertical electrolyte gate control transistor 100, the gate 105 includes a first gate 1051 and a second gate 1052, and the first gate 1051 and the second gate 1052 are juxtaposed on the source-drain stack 102.
It should be noted that, although fig. 2A illustrates a case where two gates are included, embodiments of the present disclosure are not limited thereto, and for example, more gates may be included in the vertical electrolyte gate control transistor 100, and the present disclosure does not limit the number of gates.
For example, the channel layer 103 and the electrolyte layer 104 include the same pattern as the gate electrode 105 on the source-drain stack 102.
In the vertical electrolyte gate transistor 100, the source-drain stack 102 further includes an insulating layer 1023 provided between and on the upper side of the source 1021 and the drain 1022 in a direction perpendicular to the surface of the substrate 101. In some examples, insulating layer 1023The species may be silicon dioxide (SiO 2 ) Silicon nitride (Si 3 N 4 ) Alumina (Al) 2 O 3 ) Hafnium oxide (HfO) 2 ) The thickness of insulating layer 1023 may be, for example, 5-100nm, as insulating materials, as embodiments of the present disclosure are not limited in this respect.
Fig. 2B is a schematic structural diagram of a vertical electrolyte gate transistor according to another embodiment of the present disclosure.
Fig. 2B shows a case where the channel layer 103, the electrolyte layer 104, and the gate electrode 105 are disposed on opposite sides (first side and second side) of the source-drain stack 102.
In the vertical electrolyte gate transistor 100, the channel layer 103 is in contact with the side of the source 1021 and the side of the drain 1022 on a first side and a second side of the source-drain stack 102, respectively, wherein the first side is opposite to the second side.
In the vertical electrolyte gated transistor 100, the electrolyte layer 104 is disposed outside the channel layer 103 on the first and second sides of the source drain stack 102 and is at least partially in contact with the channel layer between the source 1021 and the drain 1022.
In this vertical electrolyte gated transistor 100, the gate 105 is spaced apart from the channel layer 103 by the electrolyte layer 104 on the first and second sides of the source drain stack 102 and is at least partially in contact with the electrolyte layer 104 between the source 1021 and the drain 1022.
Likewise, the channel layer, the electrolyte layer, and the gate electrode may also be disposed on the second side of the source-drain stack from the bottom layer to the top layer of the source-drain stack in a direction perpendicular to the surface of the substrate.
The positional relationship and functions of the remaining components in the vertical electrolyte gate control transistor structure shown in fig. 2B may refer to the corresponding components in the vertical electrolyte gate control transistor structure shown in fig. 2A, and will not be described herein.
At least one embodiment of the present disclosure also provides an electronic device comprising a vertical electrolyte gated transistor as defined in any one of the above. For example, the electronic device further includes a drive circuit configured to apply different voltage signals to the gates of the vertical electrolyte gated transistors. For example, the drive circuit may include analog/digital circuitry or the like, for example, which may receive control signals from a Central Processing Unit (CPU) or the like and thereby drive the vertical electrolyte gate transistor (as described below with reference to fig. 4) to, for example, implement an artificial neuron function. For example, the drive circuit may be formed on the same substrate as the vertical electrolyte gate control transistor, or may be prepared separately from the vertical electrolyte gate control transistor and then combined with the vertical electrolyte gate control transistor, e.g., directly electrically or by other means, so that signals may be transferred between the two.
At least one embodiment of the present disclosure also provides a method for preparing a vertical electrolyte gated transistor as described above, comprising steps S1 to S4.
Step S1: a source-drain stack including source and drain electrodes stacked on each other and insulated from each other is formed on a substrate in a direction perpendicular to a surface of the substrate.
Step S2: forming channel layers on at least a first side of the source-drain stack in contact with a side of the source and a side of the drain, respectively;
step S3: forming an electrolyte layer at least partially in contact with the channel layer between the source and drain electrode, at least outside the channel layer on the first side of the source-drain stack;
step S4: a gate electrode is formed on at least the first side of the source-drain stack spaced from the channel layer by the electrolyte layer and at least partially in contact with the electrolyte layer between the source and drain electrodes.
For example, in the preparation method provided in at least one embodiment of the present disclosure, step S5 to step S7 are further included.
Step S5: further forming channel layers on the second side of the source-drain stack in contact with the side surfaces of the source and drain, respectively;
step S6: further forming an electrolyte layer between the source and drain electrodes at least partially in contact with the channel layer outside the channel layer on the second side of the source drain stack;
step S7: a gate spaced apart from the channel layer by the electrolyte layer and at least partially in contact with the electrolyte layer between the source and the drain is further formed on a second side of the source drain stack, wherein the second side is opposite the first side.
Likewise, the channel layer, the electrolyte layer and the gate electrode may be disposed on the first side and/or the second side of the source-drain stack from a bottom layer to a top layer of the source-drain stack in a direction perpendicular to the surface of the substrate.
Fig. 3A-3C are schematic diagrams illustrating a method for manufacturing a vertical electrolyte gate transistor according to an embodiment of the present disclosure.
In step S1, as shown in fig. 3A, a source-drain stack 12 including a source layer 121 and a drain layer 122 stacked on each other and insulated from each other is formed on a substrate 101 in a direction perpendicular to a surface of the substrate 101. The source-drain stack 12 further includes an insulating layer 123 disposed between and on the upper side of the source layer 121 and the drain layer 122 in a direction perpendicular to the surface of the substrate 101.
For example, the exposed areas of the source drain stack 12 are etched using photoresist as a masking material, for example, until the substrate 101 is etched. For example, different etching schemes (e.g., wet etching or dry etching) may be selected for different source and drain materials and insulating layer materials, as embodiments of the present disclosure are not limited in this respect. For example, for source and drain materials of titanium nitride (TiN), the insulating layer material is silicon dioxide (SiO 2 ) The etching gas may be boron trichloride (BCl) 3 ) And chlorine (Cl) 2 ) And (3) mixing the gases. For example, after etching is completed, the photoresist and organics generated during etching are removed using a cleaning agent, resulting in a clean sidewall structure, as shown in fig. 3B.
In steps S2-S7, as shown in fig. 3C, for example, on the first side and the second side of the source-drain stack 102, a channel layer, an electrolyte layer, and a gate layer may be sequentially deposited by using a thin film deposition method such as magnetron sputtering, vacuum evaporation, arc ion plating, and the like, and then the stack including the channel layer, the electrolyte layer, and the gate layer may be patterned by using a photolithography method and the like, thereby obtaining the channel layer 103 and the electrolyte layer 104, and the gate 105. For example, the gate 105 includes a first gate 1051 and a second gate 1052 formed in parallel on the source-drain stack, but embodiments of the present disclosure are not limited thereto, and for example, more gates may be formed in parallel, and the present disclosure does not limit the number of gates.
For example, if the channel layer, the electrolyte layer, and the gate layer are patterned in the same process (photolithography process), the channel layer 103 and the electrolyte layer 104 include the same pattern as the gate electrode 105 on the source-drain stack 102, but the embodiments of the present disclosure are not limited thereto, and if the channel layer, the electrolyte layer, and the gate layer are patterned by photolithography or the like independently, the channel layer 103 and the electrolyte layer 104 may be different patterns from the gate electrode 105 on the source-drain stack 102.
At least one embodiment of the present disclosure also provides an operating method for a vertical electrolyte gate controlled transistor as described above, comprising steps S10 to S30:
step S10: applying a first input voltage to the first gate and a second input voltage to the second gate, wherein the first input voltage and the second input voltage are different signals;
step S20: grounding one of the source and drain electrodes;
step S30: an output current signal is taken from the other of the source and the drain.
Fig. 4 is a schematic diagram of an operation method of a vertical electrolyte gate control transistor according to an embodiment of the disclosure.
In step S10, as shown in fig. 4, a first input voltage is applied to a first gate and a second input voltage is applied to a second gate through a driving circuit, wherein the first input voltage and the second input voltage are different signals. In some examples, the gate is used to simulate dendrites, and the first input voltage and the second input voltage are used to simulate pre-synaptic signals. For example, the first input voltage and the second input voltage may be pulse signals, sine waves, or square waves, which the present disclosure is not limited to.
In step S20, as shown in fig. 4, one of the source and the drain is grounded. For example, the source is grounded.
In step S30, as shown in fig. 4, an output current signal is acquired from the other of the source and the drain by the driving circuit. For example, in the case where the source is grounded, the output current signal is taken from the drain, which is used to simulate an axon. In some examples, the action potential of a neuron may be simulated by converting the output current signal.
It should be noted that, the first input voltage and the second input voltage may be different signals or the same signal, which is not limited in the embodiments of the present disclosure. For example, when the first gate and the second gate cooperate, the time interval between the first input voltage and the second input voltage may be 0, or may be another value greater than 0. As the time interval increases, the value of the output current signal spike corresponding to the second input voltage end time will gradually decrease. On the other hand, by setting the current threshold AND making the value of the output current signal peak when the first gate AND the second gate act together larger than the value of the output current signal peak when any gate acts alone, the artificial neuron can realize AND logic, thereby realizing the coincidence detection function in the dendrite calculation in the biological neuron.
In at least one embodiment, for example, in the case where the vertical electrolyte gate control transistor has a plurality of gates, an input voltage needs to be applied to each gate, and in order to implement different artificial neuron functions, the input voltages may be the same signal or different signals.
One or more embodiments of the present disclosure provide a vertical electrolyte gate controlled transistor, an electronic device including the vertical electrolyte gate controlled transistor, a method of manufacturing the vertical electrolyte gate controlled transistor, and an operating method for the vertical electrolyte gate controlled transistor. In at least one embodiment, the vertical electrolyte gated transistor, an electronic device comprising the vertical electrolyte gated transistor, a method of making the vertical electrolyte gated transistor, and a method of operating the vertical electrolyte gated transistor have one or more of the following benefits:
(1) The vertical electrolyte gate control transistor provided by at least one embodiment of the present disclosure successfully reproduces the short-time-interval information processing characteristics and the multi-dendrite structure characteristics of biological neurons, thereby greatly facilitating the simulation of higher-level and complex functions of biological neurons, and thus being applied to neuromorphic computation as artificial neurons.
(2) At least one embodiment of the present disclosure provides a vertical electrolyte gated transistor whose vertical structure imparts a dual gate structure that can allow for higher level biological neuron dendrite computation functionality.
(2) The vertical structure of the vertical electrolyte gate control transistor provided by at least one embodiment of the present disclosure endows the realized characteristics of ultra-high density and ultra-low energy consumption of the artificial neuron, realizes energy consumption close to biological neurons, and still has a further optimized space along with size miniaturization, thus paving a road for future high-area and energy-efficiency neuromorphic calculation technology.
(3) The vertical electrolyte gate control transistor provided by at least one embodiment of the present disclosure has a simple preparation method and is completely compatible with a CMOS process, and the prepared artificial neuron has excellent performance, and has an ultra-high array density and ultra-low energy consumption, thus providing a basis for a high-area and energy-efficient neuromorphic calculation technology based on the electrolyte gate control transistor.
In addition to the non-limiting description above, the following points are illustrated:
(1) The drawings of the embodiments of the present disclosure relate only to the structures to which the embodiments of the present disclosure relate, and reference may be made to the general design for other structures.
(2) The embodiments of the present disclosure and features in the embodiments may be combined with each other to arrive at a new embodiment without conflict.
The foregoing is merely specific embodiments of the disclosure, but the scope of the disclosure is not limited thereto, and the scope of the disclosure should be determined by the claims.
Claims (14)
1. A vertical electrolyte gated transistor comprising:
a substrate;
a source-drain stack disposed on the substrate in a direction perpendicular to a surface of the substrate, including source and drain electrodes stacked on each other and insulated from each other;
a channel layer in contact with a side of the source and a side of the drain, respectively, at least on a first side of the source-drain stack;
an electrolyte layer disposed outside the channel layer on at least the first side of the source-drain stack and at least partially in contact with the channel layer between the source and the drain;
a gate is spaced from the channel layer by the electrolyte layer at least on the first side of the source-drain stack and is at least partially in contact with the electrolyte layer between the source and the drain.
2. The vertical electrolyte gate control transistor of claim 1, wherein,
the channel layer is in contact with a side of the source and a side of the drain on the first and second sides of the source-drain stack, respectively;
the electrolyte layer is disposed outside the channel layer on the first side and the second side of the source-drain stack, respectively, and is at least partially in contact with the channel layer between the source and the drain;
the gate is spaced from the channel layer by the electrolyte layer and at least partially in contact with the electrolyte layer between the source and the drain on the first side and the second side of the source-drain stack respectively,
wherein the second side is opposite the first side.
3. The vertical electrolyte gate control transistor of claim 1, wherein,
the gate includes a first gate and a second gate,
the first grid electrode and the second grid electrode are arranged on the source-drain electrode lamination in parallel.
4. A vertical electrolyte gate transistor according to any one of claims 1 to 3, wherein,
the channel layer and the electrolyte layer include the same pattern as the gate electrode on the source-drain stack.
5. A vertical electrolyte gate transistor according to any one of claims 1 to 3, wherein,
the source-drain stack further includes an insulating layer disposed between and on the source electrode and the drain electrode in a direction perpendicular to a surface of the substrate.
6. The vertical electrolyte gate control transistor of claim 5, wherein,
the thickness of the insulating layer is 5-100nm;
the material of the insulating layer comprises SiO 2 ，Si 3 N 4 ，Al 2 O 3 Or HfO 2 。
7. A vertical electrolyte gate transistor according to any one of claims 1 to 3, wherein,
the thickness of the channel layer is 5-20nm;
the material of the channel layer comprises alpha-Si, inZnO and LiCoO 2 ，Li x TiO 2 ，VO 2 Or NbO x 。
8. A vertical electrolyte gate transistor according to any one of claims 1 to 3, wherein,
the thickness of the electrolyte layer is 5-30nm;
the electrolyte layer comprises chitosan, ionic gel, perfluorosulfonic acid, liClO 4 /PEO，Li x SiO y ，Li x TiO y LiPON or SiO 2 H, wherein x and y represent stoichiometric ratios.
9. An electronic device comprising the vertical electrolyte gated transistor of any of claims 1-8.
10. A method for preparing the vertical electrolyte gated transistor of any of claims 1-8 comprising:
forming a source-drain stack including source and drain stacked and insulated from each other on a substrate in a direction perpendicular to a surface of the substrate;
forming a channel layer on at least a first side of the source-drain stack in contact with a side of the source and a side of the drain, respectively;
an electrolyte layer formed at least partially in contact with the channel layer between the source and the drain, at least outside the channel layer on the first side of the source-drain stack;
a gate is formed on at least the first side of the source-drain stack spaced from the channel layer by the electrolyte layer and at least partially in contact with the electrolyte layer between the source and the drain.
11. The method of claim 10, further comprising:
further forming the channel layer on a second side of the source-drain stack in contact with a side of the source and a side of the drain, respectively;
further forming the electrolyte layer between the source and the drain at least partially in contact with the channel layer outside the channel layer on the second side of the source-drain stack;
further forming the gate electrode on the second side of the source-drain stack spaced apart from the channel layer by the electrolyte layer and at least partially in contact with the electrolyte layer between the source electrode and the drain electrode,
wherein the second side is opposite the first side.
12. The method of claim 10, wherein the gate comprises a first gate and a second gate formed in parallel on the source-drain stack.
13. The method of claim 10, wherein the channel layer and the electrolyte layer comprise the same pattern on the source drain stack as the gate.
14. A method of operation for the vertical electrolyte gated transistor of claim 3 comprising:
applying a first input voltage to the first gate and a second input voltage to the second gate, wherein the first input voltage and the second input voltage are different signals;
grounding one of the source and the drain;
an output current signal is obtained from the other of the source and the drain.
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