CN117278041A

CN117278041A - Time sequence control circuit

Info

Publication number: CN117278041A
Application number: CN202311559288.1A
Authority: CN
Inventors: 蔡成林; 王坤鹏; 张啸尘
Original assignee: Guangzhou Jiangxinchuang Technology Co ltd
Current assignee: Guangzhou Jiangxinchuang Technology Co ltd
Priority date: 2023-11-22
Filing date: 2023-11-22
Publication date: 2023-12-22
Anticipated expiration: 2043-11-22
Also published as: CN117278041B

Abstract

The invention discloses a time sequence control circuit, which comprises: the counting module comprises a plurality of counting pins and a counter, wherein the counting pins are connected with the counter, the counting pins are used for generating digital signals, and the counter is used for counting the received clock signals according to the digital signals so as to adjust clock cycles and output clock cycle signals; the comparison module comprises a comparator and a switch group, the switch group is connected with the negative input end of the comparator, and the comparator is used for outputting a comparison signal according to the working state of the switch group; the logic module is respectively connected with the counting module and the comparison module, and is used for generating a switch control signal according to the clock period signal and the comparison signal and sending the switch control signal to the comparison module so as to adjust the time sequence of the time sequence control circuit. In the embodiment of the invention, the clock period of the circuit is changed through the digital logic circuit, so that the ADC time sequence is further controlled, and the ADC performance is improved.

Description

Time sequence control circuit

Technical Field

The invention belongs to the technical field of integrated circuits, and particularly relates to a time sequence control circuit.

Background

With the rapid development of integrated circuits, internet of things, sensor networks and other technologies, and the urgent demands of people for services such as smart home and smart medical services, various miniaturized and low-power-consumption sensors are receiving higher and higher importance as bridges for connecting the physical world and various intelligent devices. Various Analog signals in the world can be sensed through the sensor, then the Analog signals can be converted into Digital signals through an Analog-to-Digital converter (ADC), then the Digital signals are sent into a Digital circuit system at the rear end, operation processing can be carried out, further the control equipment reacts, and the ADC serves as an interface of an Analog circuit and a Digital circuit and is an important bridge between the Analog signals and the Digital signals.

Among the ADC types, the high-precision Successive approximation type analog-to-Digital converter (sar ADC) has become popular in the current ADC research due to its excellent performance, such as simple structure, high degree of digitization, convenient application, low delay and low power consumption, and meanwhile, the ADC is widely applied in various fields, especially for some high-speed, high-precision and low power consumption applications. With the continuous application of electronic products, the performance requirements of the market on the electronic products are higher and higher, and the design adopted by the current time sequence control circuit is basically that RC (resistance capacitance) charges and discharges or a given constant current is mirrored to a time sequence module to generate different time sequences. For high-speed high-precision SAR ADC design, a large capacitor is externally connected outside a chip in order to improve the stability of reference voltage. But the ADC performance is severely limited due to resonance created by parasitic capacitance and parasitic inductance on the package bonding line. Therefore, how to control the timing sequence of the SAR ADC under the condition that the ADC reference voltage is externally connected with a large capacitor becomes a technical problem to be solved.

Disclosure of Invention

The invention aims at solving at least one of the technical problems in the prior art, and provides a time sequence control circuit which changes the clock period of a circuit through a digital logic circuit to further control the time sequence of an ADC and improve the performance of the ADC.

In a first aspect, the present invention provides a timing control circuit comprising:

the counting module comprises a plurality of counting pins and a counter, wherein the counting pins are connected with the counter, the counting pins are used for generating digital signals, and the counter is used for counting the received clock signals according to the digital signals so as to adjust clock cycles and output clock cycle signals;

the comparison module comprises a comparator and a switch group, wherein the switch group is connected with the negative input end of the comparator, and the comparator is used for outputting a comparison signal according to the working state of the switch group;

the logic module is respectively connected with the counting module and the comparison module, and is used for generating a switch control signal according to the clock period signal and the comparison signal and sending the switch control signal to the comparison module so as to adjust the time sequence of the time sequence control circuit.

The time sequence control circuit provided by the embodiment of the invention has at least the following beneficial effects: the counter counts the received clock signals according to the digital signals, so that the clock period of the output signals of the counter module is adjustable, the clock period signals are output, the subsequent sequential control circuit can be controlled to approach conversion time bit by bit, the conversion time of the analog-to-digital converter is reduced, the sequential control circuit is subjected to approach conversion bit by bit through the comparison module, the comparison signals are output according to the working states of the switch groups, finally, the logic module generates the switch control signals according to the clock period signals and the last comparison signals, and sends the switch control signals to the comparison module to adjust the working states of the switch groups in the comparison module, the sequential control circuit is further controlled, and the speed and the precision of the sequential control circuit are optimized.

According to some embodiments of the invention, the switch group comprises a plurality of groups of switch units connected in parallel, each group of switch units comprising one capacitor and one switch element connected.

According to some embodiments of the invention, a positive input terminal of the comparator is connected to a reference voltage source to receive a reference level signal input by the reference voltage source, the switch group is used for outputting a voltage signal to the comparator, and the comparator is used for comparing the voltage signal and the reference level signal bit by bit and outputting a comparison signal.

According to some embodiments of the invention, the comparing module is further configured to receive the switch control signal to control an operating state of the switch group according to the switch control signal.

According to some embodiments of the invention, the operating state of the switch group comprises the switching elements in the switching unit being closed to connect the capacitance to a reference voltage or to a reference ground and/or the switching elements in the switching unit being opened to open the switching unit.

According to some embodiments of the invention, the comparing module is further configured to update the voltage signal to adjust the switch control signal according to an operating state of the switch group.

According to some embodiments of the invention, the logic module includes a switch pin connected to the switch unit, the number of switch pins being equal to or greater than the number of switch units.

According to some embodiments of the invention, the clock cycle signal is used to characterize an adjustment range of the clock cycle, the adjustment range being proportional to the digital signal.

According to some embodiments of the invention, the counting module is further configured to update the clock cycle signal according to the digital signal to control the timing control circuit to approximate the time of the transition bit by bit.

According to some embodiments of the invention, the switching element is a MOS transistor, and the on-resistance of the MOS transistor is expressed as the following formula:

；

wherein,the carrier word mobility is used for representing the MOS tube; />For characterisingThe gate oxide layer capacitor of the MOS tube unit area; />The gate width is used for representing the MOS tube; />The gate length is used for representing the MOS tube; />The voltage characterization module is used for representing the voltage between the MOS tube sources; />And the threshold voltage is used for representing the MOS tube.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and drawings.

Drawings

The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate and do not limit the invention.

FIG. 1 is a schematic diagram of a timing control circuit according to an embodiment of the present invention;

FIG. 2 is a schematic circuit diagram of a timing control circuit according to an embodiment of the present invention;

fig. 3 is a timing diagram of SAR logic provided in one example of the present invention.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

The terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order.

Among the ADC types, the high-precision Successive approximation type analog-to-Digital converter (sar ADC) has become popular in the current ADC research due to its excellent performance, such as simple structure, high degree of digitization, convenient application, low delay and low power consumption, and meanwhile, the ADC is widely applied in various fields, especially for some high-speed, high-precision and low power consumption applications. With the continuous application of electronic products, the performance requirements of the market on the electronic products are higher and higher, and the design adopted by the current time sequence control circuit is basically that RC (resistance capacitance) charges and discharges or a given constant current is mirrored to a time sequence module to generate different time sequences. For high-speed high-precision SAR ADC design, a large capacitor is externally connected outside a chip in order to improve the stability of reference voltage. However, due to parasitic capacitance and parasitic inductance on the package bonding line, vibration may occur, severely limiting ADC performance. Therefore, how to control the timing sequence of the SAR ADC under the condition that the ADC reference voltage is externally connected with a large capacitor becomes a technical problem to be solved.

In order to solve the above-mentioned problems, the present embodiment provides a timing control circuit, a count pin in a count module 100 generates a value signal, a counter counts a received clock signal according to the digital signal, so that a clock period of an output signal of the count module 100 is adjustable, and a clock period signal is output, thereby being capable of controlling a subsequent timing control circuit to approach conversion time bit by bit, reducing conversion time of an analog-to-digital converter, then performing the approach conversion bit by bit on the timing control circuit through a comparison module 200, outputting a comparison signal according to an operating state of a switch group, finally, a logic module 300 generates a switch control signal according to the clock period signal and the last comparison signal, and sends the switch control signal to the comparison module 200 to adjust the operating state of the switch group in the comparison module 200, further controlling a timing of the timing control circuit, and realizing optimization of a speed and precision of the timing control circuit.

Embodiments of the present invention will be further described below with reference to the accompanying drawings.

Referring to fig. 1, fig. 1 is a schematic block diagram of a timing control circuit according to an embodiment of the present invention.

In some embodiments, the counting module 100 includes a plurality of counting pins connected to the counter, the counting pins for generating digital signals, and a counter for counting the received clock signals according to the digital signals to adjust clock cycles and outputting clock cycle signals;

it should be noted that the counting pin is an n-bit programmable value input, in this embodiment, D0-Dn-1 is used to represent, that is, different digital signals are output by editing D0-Dn-1 digital inputs, and the COUNTER counts the clock signals through the digital signals to change the clock period of the output signals, so as to further change the conversion time of each bit of the SAR ADC, where the clock signals are generated by a clock source oscillation source, for example, a crystal oscillator, an oscillation circuit, and the like.

It should be noted that, before the counter receives the clock signal, the clock generator also performs a frequency division process on the clock source to divide the high-frequency clock source into the clock signal with a lower frequency, where the purpose of the frequency division is to generate an appropriate sampling clock and control clock according to the operation requirement of the SAR ADC.

The comparison module 200 comprises a comparator and a switch group, wherein the switch group is connected with the negative input end of the comparator, and when the ADC performs successive approximation conversion, the comparator is used for outputting a comparison signal according to the working state of the switch group;

the logic module 300 is respectively connected with the counting module 100 and the comparison module 200, and sends a switch control signal to the comparison module 200 to adjust the working state of the switch group in the comparison module 200, further control the time sequence of the time sequence control circuit, and realize the optimization of the speed and the precision of the time sequence control circuit.

It should be noted that, the logic module 300 is connected to an output terminal of the comparator in the comparing module 200 to receive the comparison signal output by the comparing module 200.

Referring to fig. 2, fig. 2 is a circuit schematic of a timing control circuit according to an embodiment of the present invention.

In some embodiments, the switch group includes a plurality of groups of switch units connected in parallel, each group of switch units includes a capacitor and a switch element connected in parallel, where the capacitor and the switch element of each group of switch units are connected in series, the capacitors in this embodiment are denoted as CO to Cn, and the switch elements are denoted as S0 to Sn.

It should be noted that, the switching element is a MOS transistor, and the on-resistance of the MOS transistor is expressed as the following formula:

wherein,the method is used for representing the mobility of the current-carrying word of the MOS tube; />The gate oxide layer capacitor is used for representing the unit area of the MOS tube; />The gate width is used for representing the MOS tube; />The method is used for representing the gate length of the MOS tube; />The method is used for representing the voltage between MOS tube sources;the method is used for representing the gate width of the MOS tube.

It should be noted that the mobility of the current-carrying word of the MOS transistor is used to describe the speed of the migration of the current carrier in the MOS transistor in the channel, which affects the conduction capability and the driving capability of the MOS transistor. Higher carrier mobility means higher drive current and better switching performance. The gate oxide layer capacitor is the capacitor between the gate electrode and the channel of the MOS tube, determines the input capacitor and the response speed of the MOS tube, and the smaller gate oxide layer capacitor is beneficial to improving the response speed and the power consumption of the MOS tube. The gate width is the width occupied by the gate in the channel width, and the gate width has a larger influence on the driving capability and the input capacitance of the MOS tube. Gate length refers to the length of gate extension in the channel. The gate length has great influence on the switching speed, power consumption and driving capability of the MOS transistor.

Notably, in order to enable the capacitor array of the SAR ADC to build up a voltage within a given time. S0 to Sn in this embodiment also satisfy Rn=Ron (1/2≡n). As the SAR ADC sampling rate is higher, SO-Sn resistance is smaller, and on-resistance of the MOS tube is smaller and smaller under the conditions of on-chip equivalent parasitic capacitance and on-package line parasitic inductance, SO that resonance is more severe when a circuit switch is switched. That is, the smaller the switching resistance, the more intense the resonance and the longer the duration, thereby affecting ADC accuracy. In practical application, the SAR ADC resonance is mainly concentrated in a charge distribution stage, and the resonance attenuation coefficient alpha is also related to the size of the MOS switch resistor R.

Specifically, since the switches S0-Sn switch to generate resonance, and the resonance attenuation coefficient is related to the switch resistance, the conversion time of each bit of the conventional SAR ADC is controlled by the signal CLK clock signal, and the CLK clock period is limited by the switch Sn resistance. Therefore, the conventional SAR ADC cannot realize high sampling rate without a buffer circuit, but the embodiment can control the clock period (clock period signal) of the output signal nu of the digital circuit COUNTER by editing D0-Dn-1 digital input according to the difference of resistances of the switching elements Sn-1, and the clock period signal controls the conversion time of each bit of the SAR ADC, so that the timing sequence of the SAR ADC is controllable.

In some embodiments, the positive input end of the comparator is connected with the reference voltage source to receive the reference level signal input by the reference voltage source, the switch group is used for outputting the voltage signal to the comparator, the comparator is used for comparing the voltage signal with the reference level signal bit by bit and outputting the comparison signal, so that the accurate value of the voltage signal can be approximated, the SAR ADC can quickly and accurately acquire the digital representation of the voltage signal, and the analog-to-digital conversion is realized.

In some embodiments, the comparison module 200 is further configured to receive a switch control signal to control an operation state of the switch group according to the switch control signal, and update the voltage signal according to the operation state of the switch group to adjust the switch control signal, so that the number of the lower electrode plates of the capacitors C0 to Cn connected to the reference voltage or the reference ground is changed, thereby updating the voltage signal.

It should be noted that the comparator compares the voltage signal with the reference level signal and outputs a comparison result (comparison signal), typically a binary logic level, indicating whether the input voltage signal is greater or less than the reference voltage. Next, the comparison signal of the comparator is processed by the logic module 300, and a switching control signal is generated according to the comparison result.

For example, if the comparator output is high, indicating that the voltage signal is greater than the reference level signal, the logic decision circuit will generate a control signal to turn on the switch of the corresponding bit;

if the comparator output is low, indicating that the voltage signal is less than the reference level signal, the logic decision circuit generates a control signal to keep the switches of the corresponding bits off.

In the process of the SAR ADC bitwise approximation, the switching state of each bit needs to be controlled successively according to the clock cycle signal, so as to adjust the ADC timing, so that the ADC timing is controllable, for example, when the clock cycle signal reaches a certain stage of the bitwise approximation conversion, the logic module 300 generates the switching control signal of the corresponding bit position according to the output of the comparison module 200 and the clock signal by logic operation.

It should be noted that the switch control signal may be a binary value, which indicates the operation state of the switching element at each bit position, such as on or off.

In some embodiments, the operating state of the switch group includes the switching elements in the switch unit being closed to connect the lower plate of the capacitor to the reference voltage or to the reference ground, and/or the switching elements in the switch unit being open to disconnect the switch unit, thereby changing the number of capacitors in the switch group connected to the reference voltage or to the reference ground to enable updating of the voltage signal.

In some embodiments, the logic module 300 includes switch pins connected with the switch units, and the number of switch pins is greater than or equal to the number of switch units.

It should be noted that, in the successive approximation stage, the logic module 300 generates the switch control signal of the corresponding bit position according to the signal output by the comparator and the clock period signal. These switch control signals are then passed to the DACs at the corresponding bit positions, which control the DACs to output the corresponding analog voltages. During each successive bit-wise approximation iteration, the DAC output voltage will be continually close to the actual value of the input signal. When the iteration is finished, the voltage formed by the DAC output of each bit position is the digital code corresponding to the input signal. In the reading stage of the conversion data, the digital codes generated in the successive approximation process form a complete digital output code according to the sequence from high order to low order.

Notably, the ADC circuit requires multiple conversions to achieve greater accuracy. After one conversion period is over, the ADC will perform the next conversion, thereby obtaining a more accurate digital output code.

In some embodiments, the clock cycle signal is used to characterize an adjustment range of the clock cycle, the adjustment range being proportional to the digital signal, wherein the adjustment range is，/>Is the clock period of signal CLK 1; />The number of bits to be input for the programmable digital signal.

In some embodiments, the counting module 100 is further configured to update the clock cycle signal according to the digital signal to control the timing control circuit to approach the time of the conversion bit by bit, so as to realize the timing controllability of the SAR ADC. Because the time sequence controllable scheme mainly comprises a digital circuit, the scheme has obvious advantages in circuit area and power consumption.

In order to more clearly and clearly describe the technical solution of the timing control circuit of the present embodiment, a specific example will be described below.

Example one:

take the circuit diagram of the timing control circuit in fig. 2 as an example.

In some embodiments, D0-Dn-1 is an n-bit programmable digital input, and the digital circuit COUNTER is controlled to count the clock signal CLK1, so that the clock period of the output signal of the COUNTER COUNTER is adjustable. The adjustable range of the clock period of the nu signal (clock period signal) isWherein->Is the clock period of signal CLK 1; />The number of bits to be input for the programmable digital signal.

The comparator comp compares the voltage signal Vx with the reference level signal Vcm signal every bit of the ADC. The output result V0 of the comparison of the comparator comp can generate signals for controlling the switches S0-Sn through the digital LOGIC LOGIC, so that the number of the lower polar plates in the capacitors C0-Cn connected with the reference voltage or connected with the GND is changed, the Vx signal voltage is updated, and the process is repeated until the ADC finishes all bit conversion.

Resonance phenomenon occurs when the switches S0-Sn are switched, and the resonance attenuation coefficient is related to the switch resistance. The conventional SAR ADC is clocked by the signal CLK per bit transition time, with the CLK clock period limited by the resistance of the switch Sn. According to the novel scheme, according to the resistance difference of the switches Sn-1, the clock period of an output signal nu of a COUNTER is controlled by editing D0-Dn-1 digital input, and the nu signal controls the conversion time of each bit of the SAR ADC, so that the time sequence of the SAR ADC is controllable. Because the time sequence controllable scheme mainly comprises a digital circuit, the scheme has obvious advantages in circuit area and power consumption.

Referring to fig. 3, fig. 3 is a SAR logic timing diagram provided in an example of the present invention, wherein fig. 3 illustrates a 2bit SAR logic timing as an example.

The scheme can complete the ADC level conversion process in a shorter time using a higher frequency signal CLK1 than the conventional timing, thereby realizing a higher sampling rate. And the SAR ADC using the scheme can still show good dynamic performance under the condition of realizing high sampling rate.

The above described apparatus embodiments are merely illustrative, wherein the units illustrated as separate components may or may not be physically separate, i.e. may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

Those of ordinary skill in the art will appreciate that all or some of the steps of the methods, systems, functional modules/units in the devices disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof.

The terms "first," "second," "third," "fourth," and the like in the description of the present application and in the above-described figures, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that embodiments of the present application described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

It should be understood that in this application, "at least one" means one or more, and "a plurality" means two or more. "and/or" for describing the association relationship of the association object, the representation may have three relationships, for example, "a and/or B" may represent: only a, only B and both a and B are present, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.

In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, the above-described division of units is merely a logical function division, and there may be another division manner in actual implementation, for example, a plurality of units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium, including multiple instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of the various embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing a program.

Preferred embodiments of the present application are described above with reference to the accompanying drawings, and thus do not limit the scope of the claims of the embodiments of the present application. Any modifications, equivalent substitutions and improvements made by those skilled in the art without departing from the scope and spirit of the embodiments of the present application shall fall within the scope of the claims of the embodiments of the present application.

Claims

1. A timing control circuit, comprising:

2. The timing control circuit of claim 1, wherein the switch sets comprise a plurality of sets of switch cells connected in parallel, each set of switch cells comprising one capacitor and one switching element connected.

3. The timing control circuit of claim 1, wherein a positive input of the comparator is connected to a reference voltage source to receive a reference level signal input by the reference voltage source, the switch set is configured to output a voltage signal to the comparator, and the comparator is configured to compare the voltage signal and the reference level signal bit by bit to output a comparison signal.

4. The timing control circuit of claim 2, wherein the comparison module is further configured to receive the switch control signal to control an operating state of the switch bank according to the switch control signal.

5. The timing control circuit of claim 4, wherein the operating state of the switch bank comprises a switching element in the switching unit being closed to connect the capacitor to a reference voltage or to a reference ground and/or a switching element in the switching unit being open to open the switching unit.

6. A timing control circuit in accordance with claim 3 wherein said comparison module is further configured to update said voltage signal to adjust said switch control signal based on an operating state of said switch bank.

7. The timing control circuit of claim 2, wherein the logic module includes switch pins, the switch pins being connected to the switch cells, the number of switch pins being greater than or equal to the number of switch cells.

8. The timing control circuit of claim 1, wherein the clock cycle signal is used to characterize an adjustment range of the clock cycle, the adjustment range being proportional to the digital signal.

9. The timing control circuit of claim 1 wherein the counting module is further configured to update the clock cycle signal based on the digital signal to control a time at which the timing control circuit approximates transitions bit by bit.

10. The timing control circuit of claim 2, wherein the switching element is a MOS transistor, and the on-resistance of the MOS transistor is expressed as the following formula:

；

wherein,the carrier word mobility is used for representing the MOS tube; />For characterizing the MOS tubeA gate oxide capacitance per unit area; />The gate width is used for representing the MOS tube; />The gate length is used for representing the MOS tube; />The voltage characterization module is used for representing the voltage between the MOS tube sources; />And the threshold voltage is used for representing the MOS tube.