CN117278034A - Method and system for measuring step length of time-to-digital converter - Google Patents
Method and system for measuring step length of time-to-digital converter Download PDFInfo
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- CN117278034A CN117278034A CN202311534693.8A CN202311534693A CN117278034A CN 117278034 A CN117278034 A CN 117278034A CN 202311534693 A CN202311534693 A CN 202311534693A CN 117278034 A CN117278034 A CN 117278034A
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- 238000006243 chemical reaction Methods 0.000 claims abstract description 29
- 238000004364 calculation method Methods 0.000 claims description 13
- 238000005259 measurement Methods 0.000 description 3
- 230000009286 beneficial effect Effects 0.000 description 2
- 238000000342 Monte Carlo simulation Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/10—Calibration or testing
- H03M1/1071—Measuring or testing
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/181—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a numerical count result being used for locking the loop, the counter counting during fixed time intervals
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/12—Analogue/digital converters
- H03M1/60—Analogue/digital converters with intermediate conversion to frequency of pulses
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Measurement Of Unknown Time Intervals (AREA)
Abstract
The invention relates to the technical field of time-to-digital converters, and discloses a method and a system for measuring the step length of a time-to-digital converter, wherein the method comprises the following steps: a time-to-digital converter of the full digital phase-locked loop is scanned, and step sizes corresponding to all measured digital code values are calculated based on the digital code values, the corresponding occurrence times and conversion coefficient values; wherein the conversion coefficient value refers to the value of the time and phase conversion coefficient of the time-to-digital converter. The invention solves the problems that the step length is difficult to measure, the accuracy of the chip clock generating chip of the full digital phase-locked loop is influenced, and the like in the prior art.
Description
Technical Field
The invention relates to the technical field of time-to-digital converters, in particular to a method and a system for measuring the step length of a time-to-digital converter.
Background
In an all-digital phase-locked loop (All Digital Phase Locked Loop, ADPLL) circuit, a Time-to-Digital Converter (TDC) is often used to measure the phase difference.
Because the units of the TDC have delay, the step length (step) is difficult to measure, and when the step length is larger than the design target value and a measuring instrument is absent, the step length is basically impossible to measure, so that the problem that the clock generating chip of the all-digital phase-locked loop is difficult to accurately position exists.
To sum up, the step length is difficult to measure in the prior art, and the accuracy of positioning of the clock generating chip of the all-digital phase-locked loop is affected.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a method and a system for measuring the step length of a time-to-digital converter, which solve the problems that the step length is difficult to measure, the accuracy of a chip full-digital phase-locked loop clock generating chip is affected and the like in the prior art.
The invention solves the problems by adopting the following technical scheme:
the measuring method of the step length of the time-digital converter scans the time-digital converter of the all-digital phase-locked loop, and calculates and obtains the step length corresponding to all measured digital coding values based on the digital coding values, the corresponding occurrence times and the conversion coefficient values; wherein the conversion coefficient value refers to the value of the time and phase conversion coefficient of the time-to-digital converter.
As a preferred technical scheme, the method comprises the following steps:
s1, obtaining a coding value and the times: a time-to-digital converter for scanning the all-digital phase-locked loop, and outputting a digital coding value and an accumulated value of the corresponding occurrence times;
s2, step length delay average value calculation: converging the conversion coefficient value, and then calculating the step delay average value of the time-to-digital converter;
s3, step size calculation: and calculating to obtain the step sizes corresponding to all the measured digital coding values.
As a preferred technical solution, step S1 includes the following steps:
s11, after the all-digital phase-locked loop is locked and stabilized, starting the time-digital converter to automatically scan, scanning the time-digital converter of the all-digital phase-locked loop, adjusting the convergence position of the time-digital converter to a set starting position and starting counting;
s12, counting N times, and accumulating the occurrence times corresponding to a certain digital code value once if the digital code value occurs once;
s13, counting the next round after finishing counting N times, counting N times after the convergence position of the time-to-digital converter is +1, and continuously accumulating the occurrence times;
s14, counting is completed until the convergence position of the time-to-digital converter reaches the end position, and the time-to-digital converter automatically scans and ends to output the digital code value and the accumulated value of the corresponding occurrence times.
As a preferable technical scheme, N is more than or equal to 10.
As a preferred technical solution, step S2 includes the following steps:
s21, completing convergence of the conversion coefficient value;
s22, calculating the step delay average value of the time-digital converter according to the conversion coefficient value in the all-digital phase-locked loop after convergence is completed.
As a preferred technical solution, in step S22, the step delay average value has a calculation formula:
conversion coefficient value = step delay mean/output clock period.
As a preferred embodiment, in step S22, the structure of convergence of the conversion coefficient value is as follows:
the method comprises a first multiplier, a second multiplier, an adder and a delay which are sequentially connected, wherein the output end of the delay is connected with the input end of the adder, the first multiplier is used for inputting a phase error and a digital code value, the second multiplier is used for inputting an updating step length u, and the output end of the u is used for outputting a conversion coefficient value.
As a preferred embodiment, u is in the range of 2 -8 ~2 -20 。
As a preferred technical solution, in step S3, the step delay average is multiplied by the length of the used digital code value, divided by the sum of the occurrence times, and multiplied by the occurrence times corresponding to each digital code value, so as to calculate and obtain the step corresponding to all the measured digital code values.
The measuring system for the step length of the time-to-digital converter is used for realizing the measuring method for the step length of the time-to-digital converter, and comprises the following modules connected in sequence:
code value and times acquisition module: the time-to-digital converter is used for scanning the all-digital phase-locked loop and outputting a digital coding value and an accumulated value of the corresponding occurrence times;
step length delay average value calculation: the step delay average value of the time-to-digital converter is calculated after the conversion coefficient value is converged;
step size calculation: and calculating to obtain the step sizes corresponding to all the measured digital coding values.
Compared with the prior art, the invention has the following beneficial effects:
the invention can automatically measure the step length without depending on a measuring instrument, and has high measuring speed and high precision.
Drawings
FIG. 1 is a flow chart of step S1 of the present invention;
FIG. 2 is a schematic diagram of a convergence loop structure for convergence of transform coefficient values.
Detailed Description
The present invention will be described in further detail with reference to examples and drawings, but embodiments of the present invention are not limited thereto.
Example 1
As shown in fig. 1 to 2, the invention designs a method and a system for measuring the step length of a time-to-digital converter, and the step length is calculated through automatic scanning, so that a measurement scheme which does not depend on a measuring instrument is realized.
The method comprises the following steps:
s1, obtaining a coding value and the times: a time-to-digital converter for scanning the all-digital phase-locked loop, and outputting a digital coding value and an accumulated value of the corresponding occurrence times;
s2, step length delay average value calculation: converging the conversion coefficient value, and then calculating the step delay average value of the time-to-digital converter;
s3, step size calculation: and calculating to obtain the step sizes corresponding to all the measured digital coding values.
As a preferred technical solution, step S1 includes the following steps:
s11, after the all-digital phase-locked loop is locked and stabilized, starting the time-digital converter to automatically scan, scanning the time-digital converter of the all-digital phase-locked loop, adjusting the convergence position of the time-digital converter to a set starting position and starting counting;
s12, counting N times, and accumulating the occurrence times corresponding to a certain digital code value once if the digital code value occurs once;
s13, counting the next round after finishing counting N times, counting N times after the convergence position of the time-to-digital converter is +1, and continuously accumulating the occurrence times;
s14, counting is completed until the convergence position of the time-to-digital converter reaches the end position, and the time-to-digital converter automatically scans and ends to output the digital code value and the accumulated value of the corresponding occurrence times.
More specifically, the following is:
the automatic scanning flow of the time-to-digital converter is shown in fig. 1.
Firstly, after the all-digital phase-locked loop is locked and stabilized, the time-digital converter is started to automatically scan, the convergence position tdc_mid of the time-digital converter is adjusted to be the set starting position, and counting is started.
Counting N times (N is more than or equal to 10) in each round, and accumulating the occurrence times tdc_code_time corresponding to a certain digital code value if the tdc_code occurs once;
after the counting is completed for N times, the next round of counting is carried out, the convergence position of the time-to-digital converter is counted for N times after being plus 1, and the occurrence times are continuously accumulated;
after the counting is completed for N times, the convergence position of the time-digital converter is continuously counted for N times after +1, the occurrence times are continuously accumulated until the convergence position of the time-digital converter reaches the end position, and the counting is completed, and the automatic scanning of the time-digital converter is ended.
After the automatic scanning of the time-to-digital converter is finished, the digital coding value and the accumulated value of the corresponding occurrence number are output.
The scanning method is similar to a Monte Carlo simulation method, different delay information is randomly projected onto the time-to-digital converter, and the time-to-digital converter is measured, and a step size proportion relation of different step sizes (the step size proportion relation corresponds to the occurrence times of different digital coding values, for example, the occurrence times of the existing two digital coding values A, B and A, B are respectively 1200 and 1000, and the step size proportion of A and B is 1200/1000, namely 1.2) can be obtained through a large number of random projections, so that the exact value of the step size can not be obtained, and the exact value of the step size needs to be determined by matching with the next step.
The convergence of the conversion coefficient values (time-to-phase conversion coefficients of the time-to-digital converter, also called Ktdc values) is then completed, and the conversion coefficient value convergence loop is shown in fig. 2.
In FIG. 2, X represents a multiplier, + represents an adder, u represents an update step (a fixed value can be set in advance), and Z -1 Representing the delay.
u is optional 2 -8 ~2 -20 。
Conversion coefficient value = step delay mean/output clock period, and output clock period is a set value, so after convergence of the conversion coefficient value in the all-digital phase-locked loop is completed, the step delay mean of the time-to-digital converter can be calculated.
And finally, multiplying the step delay average value of the time-to-digital converter by the length of the used digital code value, dividing by the sum of the occurrence times, and multiplying by the occurrence times corresponding to each digital code value to obtain the step corresponding to all the measured digital code values.
The calculation formula is as follows:
step size = (step delay mean value sum of used digital code value length/number of occurrences) number of occurrences.
Compared with the prior art, the invention has the following beneficial effects:
the existing measurement scheme needs to rely on a measuring instrument, and the invention can automatically measure the step length without depending on the measuring instrument, and has high measurement speed and high precision.
As described above, the present invention can be preferably implemented.
All of the features disclosed in all of the embodiments of this specification, or all of the steps in any method or process disclosed implicitly, except for the mutually exclusive features and/or steps, may be combined and/or expanded and substituted in any way.
The foregoing description of the preferred embodiment of the invention is not intended to limit the invention in any way, but rather to cover all modifications, equivalents, improvements and alternatives falling within the spirit and principles of the invention.
Claims (10)
1. The measuring method of the step length of the time digital converter is characterized in that the time digital converter of the full digital phase-locked loop is scanned, and the step length corresponding to all measured digital code values is calculated based on the digital code values, the corresponding occurrence times and the conversion coefficient values; wherein the conversion coefficient value refers to the value of the time and phase conversion coefficient of the time-to-digital converter.
2. A method of measuring a step size of a time-to-digital converter according to claim 1, comprising the steps of:
s1, obtaining a coding value and the times: a time-to-digital converter for scanning the all-digital phase-locked loop, and outputting a digital coding value and an accumulated value of the corresponding occurrence times;
s2, step length delay average value calculation: converging the conversion coefficient value, and then calculating the step delay average value of the time-to-digital converter;
s3, step size calculation: and calculating to obtain the step sizes corresponding to all the measured digital coding values.
3. A method for measuring a step size of a time-to-digital converter according to claim 2, wherein step S1 comprises the steps of:
s11, after the all-digital phase-locked loop is locked and stabilized, starting the time-digital converter to automatically scan, scanning the time-digital converter of the all-digital phase-locked loop, adjusting the convergence position of the time-digital converter to a set starting position and starting counting;
s12, counting N times, and accumulating the occurrence times corresponding to a certain digital code value once if the digital code value occurs once;
s13, counting the next round after finishing counting N times, counting N times after the convergence position of the time-to-digital converter is +1, and continuously accumulating the occurrence times;
s14, counting is completed until the convergence position of the time-to-digital converter reaches the end position, and the time-to-digital converter automatically scans and ends to output the digital code value and the accumulated value of the corresponding occurrence times.
4. A method of measuring a step size of a time to digital converter according to claim 3, wherein N is ≡10.
5. A method for measuring a step size of a time-to-digital converter according to claim 2, wherein step S2 comprises the steps of:
s21, completing convergence of the conversion coefficient value;
s22, calculating the step delay average value of the time-digital converter according to the conversion coefficient value in the all-digital phase-locked loop after convergence is completed.
6. The method for measuring a step size of a time-to-digital converter according to claim 5, wherein in step S22, a calculation formula of a step size delay average value is:
conversion coefficient value = step delay mean/output clock period.
7. The method according to claim 5, wherein in step S22, the convergence of the conversion coefficient value is configured as follows:
the method comprises a first multiplier, a second multiplier, an adder and a delay which are sequentially connected, wherein the output end of the delay is connected with the input end of the adder, the first multiplier is used for inputting a phase error and a digital code value, the second multiplier is used for inputting an updating step length u, and the output end of the u is used for outputting a conversion coefficient value.
8. The method of claim 6, wherein u ranges from 2 -8 ~2 -20 。
9. A method according to any one of claims 2 to 8, wherein in step S3, the step delay average is multiplied by the length of the digital code value used, divided by the sum of the number of occurrences, and multiplied by the number of occurrences corresponding to each digital code value, so as to calculate the step corresponding to all the digital code values measured.
10. A system for measuring a time-to-digital converter step size, characterized in that it comprises the following modules, connected in sequence:
code value and times acquisition module: the time-to-digital converter is used for scanning the all-digital phase-locked loop and outputting a digital coding value and an accumulated value of the corresponding occurrence times;
step length delay average value calculation: the step delay average value of the time-to-digital converter is calculated after the conversion coefficient value is converged;
step size calculation: and calculating to obtain the step sizes corresponding to all the measured digital coding values.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003092531A (en) * | 2001-09-17 | 2003-03-28 | Nec Corp | Adaptive step size control adaptive filter and adaptive scale coefficient control method |
| CN102589626A (en) * | 2012-01-20 | 2012-07-18 | 北京嘉洁能科技有限公司 | High-resolution time measurement and processing device and measurement method thereof |
| US8664994B1 (en) * | 2012-10-10 | 2014-03-04 | Department of Electronics and Information Technology | System to generate a predetermined fractional period time delay |
| CN107678333A (en) * | 2017-09-25 | 2018-02-09 | 西南科技大学 | A kind of step-length time-correcting method and device based on equivalent time sequential sampling |
| CN112054782A (en) * | 2020-08-20 | 2020-12-08 | 中国人民解放军陆军勤务学院 | Variable step size factor construction method for LMS adaptive filtering |
| US20220263517A1 (en) * | 2020-05-07 | 2022-08-18 | Advantest Corporation | Measurement unit configured to provide a measurement result value |
| CN115242242A (en) * | 2021-04-23 | 2022-10-25 | 上海禾赛科技有限公司 | Circuit for time-to-digital converter, corresponding method and laser radar |
| CN115967398A (en) * | 2022-12-30 | 2023-04-14 | 成都电科星拓科技有限公司 | Method, system and equipment for updating conversion coefficient of time-to-digital converter |
-
2023
- 2023-11-17 CN CN202311534693.8A patent/CN117278034B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003092531A (en) * | 2001-09-17 | 2003-03-28 | Nec Corp | Adaptive step size control adaptive filter and adaptive scale coefficient control method |
| CN102589626A (en) * | 2012-01-20 | 2012-07-18 | 北京嘉洁能科技有限公司 | High-resolution time measurement and processing device and measurement method thereof |
| US8664994B1 (en) * | 2012-10-10 | 2014-03-04 | Department of Electronics and Information Technology | System to generate a predetermined fractional period time delay |
| CN107678333A (en) * | 2017-09-25 | 2018-02-09 | 西南科技大学 | A kind of step-length time-correcting method and device based on equivalent time sequential sampling |
| US20220263517A1 (en) * | 2020-05-07 | 2022-08-18 | Advantest Corporation | Measurement unit configured to provide a measurement result value |
| CN112054782A (en) * | 2020-08-20 | 2020-12-08 | 中国人民解放军陆军勤务学院 | Variable step size factor construction method for LMS adaptive filtering |
| CN115242242A (en) * | 2021-04-23 | 2022-10-25 | 上海禾赛科技有限公司 | Circuit for time-to-digital converter, corresponding method and laser radar |
| CN115967398A (en) * | 2022-12-30 | 2023-04-14 | 成都电科星拓科技有限公司 | Method, system and equipment for updating conversion coefficient of time-to-digital converter |
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