CN117277761B - Driving device of integrated miller clamp protection circuit - Google Patents
Driving device of integrated miller clamp protection circuit Download PDFInfo
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- CN117277761B CN117277761B CN202311574234.2A CN202311574234A CN117277761B CN 117277761 B CN117277761 B CN 117277761B CN 202311574234 A CN202311574234 A CN 202311574234A CN 117277761 B CN117277761 B CN 117277761B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0038—Circuits or arrangements for suppressing, e.g. by masking incorrect turn-on or turn-off signals, e.g. due to current spikes in current mode control
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
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Abstract
The invention discloses a driving device of an integrated miller clamp protection circuit, which is used for driving a SiC MOSFET, and comprises: a charging module for charging the gate of the SiC MOSFET and controlling the output current to adjust the gate current I of the SiC MOSFET g Is of a size of (2); the discharging module is used for discharging the grid electrode of the SiC MOSFET and regulating the grid electrode current I of the SiC MOSFET by controlling the output current g Size of the material; the miller clamp protection module is used for generating a miller clamp voltage V f When the gate-source voltage V of the SiC MOSFET gs Greater than miller clamp voltage V f At this time, the SiC MOSFET is turned off. The method can accurately control the grid current of the SiC MOSFET and effectively inhibit the displacement current, so that the switching performance and the reliability of the SiC MOSFET are improved.
Description
Technical Field
The invention relates to a driving circuit, in particular to a driving device integrated with a miller clamp protection circuit.
Background
The SiC MOSFET is a novel power device with the advantages of high voltage, high temperature, high frequency, low switching loss and the like, and is widely applied to various power conversion systems. However, siC MOSFETs have large gate and drain capacitances, and high gate threshold voltages, which limit the increase in switching speed, increasing switching losses in high frequency applications.
Currently, there are two main methods for designing SiC MOSFET drivers: one is a voltage-driven-based method, i.e., switching control of SiC MOSFETs is achieved by controlling the gate voltage; another is a current drive based method, i.e. the switching control of SiC MOSFETs is achieved by controlling the gate current. Among them, the current source type driving circuit is more advantageous due to faster switching speed and smaller switching loss. However, the conventional current source type driving circuit has the defects of low switching performance, poor reliability and the like. In addition, the existing driving circuit can only drive SiC MOSFETs of one type, and has poor applicability. Therefore, it is an objective need to provide a high performance driving circuit to drive SiC MOSFETs and to adapt to different types of SiC MOSFETs.
Disclosure of Invention
The invention provides a driving device integrating a miller clamp protection circuit, which is used for solving the technical problems of low switch performance, poor reliability and applicability and the like in the prior art.
To achieve the object of the present invention, there is provided a driving device integrating a miller clamp protection circuit for driving a SiC MOSFET, the device comprising:
a charging module connected with the grid of the SiC MOSFET for charging the grid of the SiC MOSFET and controlling the output current to adjust the grid current I of the SiC MOSFET g Is of a size of (2); the charging module comprises a first current mirror unit with a plurality of output ends and a first switch control unit with a plurality of charging channels; wherein the rated current amount of each of the charging channels is different;
a discharging module connected with the grid electrode of the SiC MOSFET for discharging the grid electrode of the SiC MOSFET and regulating the grid electrode current I of the SiC MOSFET by controlling the output current g Size of the material; the discharging module comprises a plurality of second current mirror units with output ends and a plurality of second switch control units with discharging channels; wherein the rated current amount of each of the discharge channels is different;
a miller clamp protection module connected to the gate of the SiC MOSFET for generating a miller clamp voltage V f When the gate-source voltage V of the SiC MOSFET gs Greater than miller clamp voltage V f When the SiC MOSFET is turned off, the SiC MOSFET is prevented from being turned on by mistake; the miller clamp protection module comprises a miller clamp voltage setting circuit with a plurality of output ends and a third switch control unit with a plurality of voltage dividing channels; wherein the nominal voltage dividing resistance of each voltage dividing channel is different.
Further, the input end of the first current mirror unit inputs a first input current I 10 And the output end of the first switch control unit is connected with the grid electrode of the SiC MOSFET.
Further, the first current mirror unit includes a first PMOS tube and four second PMOS tubes, the gate and drain of the first PMOS tube respectively input a first input current I 10 The source electrode of the second PMOS tube is connected with the power supply VDD, and the grid electrodes of the second PMOS tube respectively input a first input current I 10 The source electrode of the second PMOS tube is connected with the power supply VDD, the drain electrode of the second PMOS tube is connected with the grid electrode of the SiC MOSFET through the first switch control unit, and the rated current proportion relation of the four second PMOS tubes is 1:2:4:8.
further, the first switch control unit includes four first switch control sub-units, each of the first switch control sub-units includes a third PMOS tube and a first register DH storing an external program control signal, the first switch control sub-units are in one-to-one correspondence with the second PMOS tubes, and conduction of each of the second PMOS tubes is controlled by the corresponding first switch control sub-units, a source of each of the third PMOS tubes is connected with a drain of one of the second PMOS tubes, a gate of each of the third PMOS tubes is connected with one of the first registers DH, a drain of each of the third PMOS tubes is connected with a gate of the SiC MOSFET, and when external program control signals in the plurality of first registers DH are changed, the conduction number of the second PMOS tubes is controlled by turning off the third PMOS tubes to control the magnitude of the output current of the first current mirror unit.
Further, the input end of the second current mirror unit inputs a second input current I 0 And the output end of the second switch control unit is connected with the grid electrode of the SiC MOSFET.
Further, the second current mirror unit includes a first NMOS tube and four second NMOS tubes, the grid and drain of the first NMOS tube respectively input a second input current I 0 The source electrode of the second NMOS tube is grounded, and the grid electrodes of the second NMOS tube respectively input a second input current I 0 The source electrode of the second NMOS transistor is grounded, the drain electrode of the second NMOS transistor is connected with the grid electrode of the SiC MOSFET through the second switch control unit, and the rated current ratio relation of the four second NMOS transistors is 1:2:4:8.
further, the second switch control unit includes four second switch control subunits, each second switch control subunit includes a third NMOS and a second register DL storing an external program control signal, the second switch control subunits are in one-to-one correspondence with the second NMOS, and conduction of each second NMOS is controlled by the corresponding second switch control subunit, a source of each third NMOS is connected to a drain of one second NMOS, a gate of each third NMOS is connected to one second register DL, a drain of each third NMOS is connected to a gate of the SiC MOSFET, and when external program control signals in the second registers DL are changed, the conduction number of the second NMOS is controlled by turning off the third NMOS to control the magnitude of the output current of the second current mirror unit.
Further, the miller clamp protection module comprises a first comparator A1, a miller clamp voltage setting circuit and a fourth NMOS tube, wherein the non-inverting input end of the first comparator A1 is connected with the miller clamp voltage setting circuit, the inverting input end of the first comparator A1 is connected with the grid electrode of the SiC MOSFET, the output end of the first comparator A is connected with the grid electrode of the fourth NMOS tube, the drain electrode of the fourth NMOS tube is connected with the grid electrode of the SiC MOSFET, and the source electrode of the fourth NMOS tube is connected with the digital ground VSS.
Further, the miller clamp voltage setting circuit comprises a first resistor R1 and four voltage dividing resistors, wherein one end of the first resistor R1 is connected with the non-inverting input end of the first comparator A1, the other end of the first resistor R1 is grounded, one end of the four voltage dividing resistors which are connected in series is connected with the non-inverting input end of the first comparator A1, and the other end of the four voltage dividing resistors is connected with an external input voltage end; the ratio of the resistance values of the first resistor R1 and the four voltage dividing resistors is 1:2:4:8:16.
in some embodiments, the miller clamp protection module further includes a third switch control unit, the miller clamp voltage setting circuit further includes a third switch control unit, the third switch control unit is connected in parallel with the voltage dividing resistor, the third switch control unit includes four third switch control subunits, each third switch control subunit includes a fourth PMOS transistor and a third register DT storing an external program control signal, the third switch control subunits are in one-to-one correspondence with the voltage dividing resistor, and each voltage dividing resistor is controlled by the corresponding third switch control subunit whether the voltage dividing resistor is shorted or notThe source and drain of the fourth PMOS tube are respectively connected with two ends of a divider resistor, the grid of the fourth PMOS tube is connected with a third register DT, when external program control signals in a plurality of the third registers DT are changed, the number of the divider resistors is controlled by the fourth PMOS tube to control the Miller clamp voltage V f Is of a size of (a) and (b).
The beneficial effects of the invention are as follows: according to the driving device of the integrated miller clamp protection circuit, the grid electrode of the SiC MOSFET is charged through the charging module, the grid electrode of the SiC MOSFET is discharged through the discharging module, and meanwhile, the accurate control of the grid electrode currents of the SiC MOSFETs of different types is realized by controlling the current output by the charging module and the current output by the discharging module, so that the switching performance and the power conversion efficiency of the SiC MOSFETs are improved.
On the other hand, the SiC MOSFET is protected through the Miller clamp protection module, so that effective suppression of displacement current caused by instant high voltage of the drain electrode of the SiC MOSFET is realized, and the reliability of the SiC MOSFET is improved. In addition, the invention can also control the Miller clamp voltage V f The size of the power supply is suitable for driving SiC MOSFETs of different models, and the adaptability is high.
In addition, the rated current of each charging channel, the rated current of each discharging channel and the rated voltage dividing resistance of each voltage dividing channel are different, so that the adjustment flexibility of the charging current can be improved on the basis of fixing the number of the charging channels; the adjustment flexibility of the discharge current can be improved on the basis of fixing the number of the discharge channels; the flexibility of adjusting the miller clamping voltage can be improved on the basis of the number of the fixed partial pressure channels.
The invention also has the characteristics of simple structure, high integration level, strong programmability and the like, and is suitable for power application in severe environments such as high voltage, high temperature, high frequency and the like.
Drawings
FIG. 1 is a schematic diagram of a driving device of an integrated Miller clamp protection circuit of the present invention;
FIG. 2 is a circuit diagram of a driving device of the integrated Miller clamp protection circuit of the present invention;
FIG. 3 is a control diagram of a charging module of the present invention;
FIG. 4 is a control diagram of a discharge module of the present invention;
fig. 5 is a charge-discharge waveform diagram of the driving device of the integrated miller clamp protection circuit of the present invention.
Detailed Description
The invention provides a driving device of an integrated miller clamp protection circuit, which is further described below with reference to the accompanying drawings and specific embodiments.
Referring to fig. 1, a driving device of an integrated miller clamp protection circuit of the present invention is connected to a SiC MOSFET, and includes a charging module 10, a discharging module 20 and a miller clamp protection module 30, wherein the charging module 10, the discharging module 20 and the miller clamp protection module 30 are all connected to a gate of the SiC MOSFET. According to the invention, the SiC MOSFET is charged through the charging module 10, the SiC MOSFET is discharged through the discharging module 20, the accurate control of the grid current of the SiC MOSFET is realized by controlling the current output by the charging module 10 and the current output by the discharging module 20, and the displacement current formed by the drain electrode of the SiC MOSFET is restrained through the miller clamp protection module 30, so that the switching performance and the reliability of the SiC MOSFET are improved. The invention is suitable for power application in severe environments such as high voltage, high temperature, high frequency and the like.
As shown in fig. 1, the charging module 10 is connected to the gate of the SiC MOSFET for charging the gate of the SiC MOSFET and controlling the gate current I of the SiC MOSFET by controlling the magnitude of the output current thereof g Is of a size of (a) and (b). The charging module 10 comprises a first current mirror unit 11 and a first switch control unit 12, wherein the first current mirror unit 11 is used for copying multiple output currents, and the input end of the first current mirror unit is input with a first input current I 10 The output terminal of which is connected to the gate of the SiC MOSFET via a first switching control unit 12. The first control switch unit 12 is used for controlling the switches of the plurality of second PMOS transistors in the first current mirror unit 11, so as to control the magnitude of the output current of the first current mirror unit 11.
As shown in fig. 2, the first current mirror unit 11 includes a first PMOS transistor and a plurality of second PMOS transistors, wherein the first PMOS transistorRespectively input a first input current I to the gate and the drain of the transistor 10 The source electrode of the second PMOS tube is connected with the power supply VDD, and the grid electrodes of the second PMOS tubes respectively input a first input current I 10 The source electrode of the second PMOS transistor is connected with a power supply VDD, the drain electrode of the second PMOS transistor is connected with the grid electrode of the SiC MOSFET through a first switch control unit 12, and the second PMOS transistor is controlled to be turned off through the first switch control unit 12. The first switch control unit 12 includes a plurality of first switch control sub-units, each of which includes a third PMOS transistor and a first register DH storing an external program control signal, where the number of the first switch control sub-units is the same as the number of the second PMOS transistors. The turn-off of each second PMOS transistor is controlled by a first register DH and a third PMOS transistor. The source electrode of each third PMOS tube is connected with the drain electrode of one second PMOS tube, the grid electrode of each third PMOS tube is connected with one first register DH, and the drain electrode of each third PMOS tube is connected with the grid electrode of the SiC MOSFET. The external program control signals are stored in the plurality of first registers DH, and when the external program control signals in the plurality of first registers DH are changed, the turn-off of the third PMOS tube is used for controlling the turn-on quantity of the second PMOS tube so as to control the output current of the first current mirror unit 11.
Specifically, in the embodiment shown in fig. 2, the first current mirror unit 11 is composed of a four-stage cascade including a first PMOS transistor M10 and four second PMOS transistors M11, M12, M13 and M14, and the first switch control unit 12 includes four third PMOS transistors M15, M16, M17, M18 and four first registers DH [0 ]]、DH[1]、DH[2]、DH[3]. Wherein, the grid electrode and the drain electrode of the first PMOS tube M10 are respectively connected with the first input current I 10 The source electrode of the second PMOS tube M11, the second PMOS tube M12, the second PMOS tube M13 and the second PMOS tube M14 are connected with the power supply VDD, and the grid electrodes of the second PMOS tube M11, the second PMOS tube M12 and the second PMOS tube M14 are respectively connected with the first input current I 10 The source electrode is connected with the power supply VDD, the drain electrodes are respectively connected with the source electrodes of the third PMOS tubes M15, M16, M17 and M18, the drain electrodes of the third PMOS tubes M15, M16, M17 and M18 are connected with the grid electrodes of the SiC MOSFET, and the grid electrodes are respectively connected with the first register DH [0 ]]、DH[1]、DH[2]、DH[3]And (5) connection. First register DH [0 ]]、DH[1]、DH[2]、DH[3]An external program control signal is stored. As shown in fig. 3, through a first input current I 10 Copying to obtain current I 11 、I 12 、I 13 、I 14 Current I 11 、I 12 、I 13 、I 14 Are connected together to obtain a current I Charging method Current I Charging method Directly input to the gate of the SiC MOSFET, i.e. I Charging method =I g . Wherein the current I 11 、I 12 、I 13 、I 14 Can be combined with I 10 Equal or unequal, in this embodiment, the current I 11 、I 12 、I 13 、I 14 And I 10 Equal. The output current I of the first current mirror unit 11 is controlled by controlling the turn-off of the third PMOS tube Charging method . When the third PMOS tube M15 is turned off, I 11 =0. Similarly, when the third PMOS transistors M16, M17 and M18 are turned off, the current I 12 、I 13 、I 14 Each 0. Therefore, by controlling the states of the third PMOS transistors M15, M16, M17 and M18, the gate current I of the SiC MOSFET can be realized g Thereby realizing charge control of the parasitic capacitance of the gate of the SiC MOSFET. The control signals of the third PMOS tubes M15, M16, M17 and M18 are derived from the control signals stored in the first register DH [0 ]]、DH[1]、DH[2]、DH[3]An internal external program control signal. For example, when the first register DH [0 ]]When the internal external program control signal is equal to 1, the third PMOS tube M15 is turned off, and the current flowing through the third PMOS tube M15 is 0; when the first register DH [0 ]]When the internal external program control signal is equal to 0, the third PMOS tube M15 is conducted, and the current flowing through the third PMOS tube M15 is I 11 . For the same type of SiC MOSFET, when the first register DH [0 ]]、DH[1]、DH[2]、DH[3]When the internal external program control signals are 1110 respectively, the charging current I of the SiC MOSFET gate g At the minimum, i.e. only the third PMOS tube M18 is turned on, its output current is I 14 At this time, the charging process of the SiC MOSFET gate is slowest. When the first register DH [0 ]]、DH[1]、DH[2]、DH[3]When the internal external program control signals are 0000, the charging current of the SiC MOSFET gate is maximum, namely the four third PMOS tubes M15, M16, M17 and M18 respectively output current I 11 、I 12 、I 13 、I 14 ，I Charging method =I 11 +I 12 +I 13 +I 14 The charging process of the SiC MOSFET gate is fastest at this time. By programmable means, the first register DH [0 ] is changed]、DH[1]、DH[2]、DH[3]An internal external program control signal to achieve a charging current I to the SiC MOSFET gate Charging method Thereby controlling the rate of charge to the SiC MOSFET gate. For different types of SiC MOSFETs, when one type of SiC MOSFETs with smaller grid capacitance is driven, a smaller charging current I can be selectively output Charging method So that the gate current I g Smaller; when a SiC MOSFET with higher grid threshold voltage is driven, a larger charging current I can be selectively output Charging method So that the gate current I g And is larger, so that the switching performance of the SiC MOSFET is adjusted.
Further, in order to realize refined charging current control, the rated current amount proportional relationship of the four second PMOS transistors may be 1:2:4:8 (i.e. I 11 、I 12 、I 13 、I 14 The ratio relation of (2) is 1:2:4: 8) The different rated current amounts can be realized by adopting different length-width ratios of the transistors (the second PMOS transistor), so that the sectional control of sequentially increasing the output current according to the binary relation can be realized, and the ratio of the rated current amounts can be 1:2:4:8, sixteen charging currents of multiples of 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 and 15 can be realized, so that the design of the first current mirror unit realizes uniformly subdivided current output control, and higher regulation precision is achieved.
As shown in fig. 1, the discharging module 20 is connected to the gate of the SiC MOSFET for discharging the gate of the SiC MOSFET and controlling the gate current I of the SiC MOSFET by controlling the magnitude of the output current thereof g Is of a size of (a) and (b). The discharging module 20 comprises a second current mirror unit 21 and a second switch control unit 22, wherein the second current mirror unit 21 is used for copying multiple output currents, and the input end of the second current mirror unit inputs a second input current I 0 The output of which is connected to the gate of the SiC MOSFET via a second switching control unit 22. The second control switch unit 22 is used for controlling the switch of the second NMOS transistors in the second current mirror unit 21 to controlThe magnitude of the output current of the second current mirror unit 21 is made.
As shown in fig. 2, the second current mirror unit 21 includes a first NMOS transistor and a plurality of second NMOS transistors, wherein the gate and drain of the first NMOS transistor respectively input a second input current I 0 The source electrode of the second NMOS tube is grounded GND, and the grid electrodes of the second NMOS tubes respectively input second input current I 0 The source electrode of the second NMOS transistor is grounded GND, the drain electrode of the second NMOS transistor is connected with the grid electrode of the SiC MOSFET through a second switch control unit 22, and the second NMOS transistor is controlled to be turned off through the second switch control unit 22. The second switch control unit 22 includes a plurality of second switch control subunits, each of which includes a third NMOS transistor and a second register DL, where the number of second switch control subunits is the same as the number of second NMOS transistors. The turn-off of each second NMOS transistor is controlled by a second register DL and a third NMOS transistor. The source of each third NMOS tube is connected with the drain of one second NMOS tube, the grid of each third NMOS tube is connected with one second register DL, and the drain of each third NMOS tube is connected with the grid of the SiC MOSFET. The plurality of second registers DL are stored with external program control signals, and when the external program control signals in the plurality of second registers DL are changed, the turn-off of the third NMOS transistor controls the turn-on number of the second NMOS transistor to control the magnitude of the output current of the second current mirror unit 21.
In the embodiment shown in FIG. 2, the second current mirror unit 21 is composed of a four-stage cascade including a first NMOS transistor M0 and four second NMOS transistors M1, M2, M3 and M4, and the second switch control unit 22 includes four third NMOS transistors M5, M6, M7, M8 and four second registers DL [0 ]]、DL[1]、DL[2]、DL[3]Wherein the grid electrode and the drain electrode of the first NMOS tube M0 are respectively connected with the second input current I 0 The gates of the second NMOS transistors M1, M2, M3 and M4 are respectively connected with the second input current I 0 The source electrode of the third NMOS transistor is grounded GND, the drain electrodes of the third NMOS transistors M5, M6, M7 and M8 are respectively connected with the source electrodes of the third NMOS transistors M5, M6, M7 and M8, the drain electrodes of the third NMOS transistors M5, M6, M7 and M8 are respectively connected with the grid electrodes of the SiC MOSFET, and the grid electrodes of the third NMOS transistors are respectively connected with the second register DL [0 ]]、DL[1]、DL[2]、DL[3]And (5) connection. Second register DL [0 ]]、DL[1]、DL[2]、DL[3]Is stored with an external program control signal。
As shown in fig. 4, through the second input current I 0 Copying to obtain current I 1 、I 2 、I 3 、I 4 Current I 1 、I 2 、I 3 、I 4 Are connected together to obtain a current I Discharge of electric power Current I Discharge of electric power Directly input to the gate of the SiC MOSFET, i.e. I Discharge of electric power =I g . Wherein the current I 1 、I 2 、I 3 、I 4 Can be combined with I 0 Equal or unequal, in this embodiment, the current I 1 、I 2 、I 3 、I 4 And I 0 Equal. Controlling the output current I of the second current mirror unit 21 by controlling the turn-off of the third NMOS transistor Discharge of electric power . When the third NMOS tube M5 is turned off, I 1 =0. Similarly, when the third NMOS transistors M6, M7 and M8 are turned off, the current I 2 、I 3 、I 4 Each 0. Therefore, by controlling the states of the third NMOS transistors M5, M6, M7 and M8, the gate current I to the SiC MOSFET can be realized g Thereby achieving discharge control of the parasitic capacitance of the gate of the SiC MOSFET. The third NMOS transistors M5, M6, M7 and M8 control signals are derived from the second register DL [0 ]]、DL[1]、DL[2]、DL[3]An internal external program control signal. For example, when the second register DL [0 ]]When the internal external program control signal is equal to 1, the third NMOS tube M5 is turned on, and the current flowing through the third NMOS tube M5 is I 1 The method comprises the steps of carrying out a first treatment on the surface of the When the second register DL [0 ]]When the internal external program control signal is equal to 0, the third NMOS transistor M5 is turned off, and the current flowing through the third NMOS transistor M5 is 0. For the same type of SiC MOSFET, when the second register DL [0 ]]、DL[1]、DL[2]、DL[3]When the internal external program control signals are 0001, the discharge current I of the SiC MOSFET gate g At the minimum, i.e. only the third NMOS transistor M4 is turned on, its output current is I 4 At this time, the discharge process of the SiC MOSFET gate is slowest. When the second register DL [0 ]]、DL[1]、DL[2]、DL[3]When the internal external program control signals are 1111, the discharge current of the SiC MOSFET gate is maximum, i.e. the four third NMOS transistors M1, M2, M3, M4 output current I respectively 1 、I 2 、I 3 、I 4 ，I Discharge of electric power =I 1 +I 2 +I 3 +I 4 At this time, the discharge process of the SiC MOSFET gate is fastest. By programmable means, the second register DL [0 ] is changed]、DL[1]、DL[2]、DL[3]Internal external program control signal to achieve discharge current I to SiC MOSFET gate Discharge of electric power Thereby controlling the rate of discharge to the SiC MOSFET gate. For different types of SiC MOSFETs, when one type of SiC MOSFETs with smaller grid capacitance is driven, a smaller discharge current I can be selectively output Discharge of electric power So that the gate current I g Smaller; when a SiC MOSFET with higher grid threshold voltage is driven, a larger discharge current I can be selectively output Discharge of electric power So that the gate current I g And is larger, so that the switching performance of the SiC MOSFET is adjusted.
Further, in order to achieve refined discharge current control, the rated current amount ratio relationship of the four second NMOS transistors may be 1:2:4:8 (i.e. I 1 、I 2 、I 3 、I 4 The ratio relation of (2) is 1:2:4: 8) Here, different rated current amounts can be realized by adopting different length-width ratios of transistors (second NMOS transistors), so that sectional control that input currents sequentially increase according to a binary relationship can be realized, and the ratio relationship of the rated current amounts can be 1:2:4:8, sixteen discharge currents of multiples of 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 and 15 can be realized, so that the design of the second current mirror unit realizes uniformly subdivided current input control, and higher regulation precision is achieved.
As shown in fig. 5, the working procedures of the charging module 10 and the discharging module 20 of the present embodiment are as follows: at 0-t 0 At this time, the third PMOS transistor of the first current mirror unit 11 is turned off, the third NMOS transistor of the second current mirror unit 21 is turned on, and the SiC MOSFET is in a stable off state.
At t 0 -t 1 At moment, the third PMOS tube is turned on, the third NMOS tube is turned off, and the driving current I g Charging the parasitic capacitance of the grid electrode of the SiC MOSFET, V gs_Q Start to rise when V gs_Q When the magnitude of VDD is reached,and (5) ending the charging. At this time, the driving current I can be controlled by controlling the conduction quantity of the third PMOS tube g Thereby controlling the charging speed of the parasitic capacitance of the grid electrode of the SiC MOSFET to improve the switching performance of the SiC MOSFET.
At t 1 -t 2 At this time, the third PMOS transistor is kept on, the third NMOS transistor is turned off, the SiC MOSFET is in a stable to on state, and the SiC MOSFET gate is directly connected to the power supply VDD through the first current mirror unit 11.
At t 2 -t 3 At the moment, the third PMOS tube is turned off, the third NMOS tube is turned on, and the parasitic capacitance of the grid electrode of the SiC MOSFET is discharged through the third NMOS tube. At this time, the discharging speed can be controlled by controlling the conducting quantity of the third NMOS tube, so as to improve the switching performance of the SiC MOSFET.
At t 3 -t 4 At this time, the third PMOS transistor is turned off, the third NMOS transistor is turned on, the SiC MOSFET is in a stable to off state, and the SiC MOSFET gate is grounded GND through the first current mirror unit 21.
For the SiC MOSFET at the low side, when the high side SiC MOSFET is charged in an on state, the low side SiC MOSFET is in an off state, but the drain electrode connected with the high side has an instant high voltage which passes through the Miller capacitor C gd Forming a displacement current. The displacement current may cause the gate-source voltage of the SiC MOSFET to rise, resulting in the parasitic capacitance of the SiC MOSFET turning on. In order to suppress the displacement current, the present embodiment provides a miller clamp protection module 30.
As shown in fig. 1, the miller clamp protection module 30 is connected to the gate source of the SiC MOSFET, and includes a first comparator A1, a miller clamp voltage setting circuit 31, and a fourth NMOS transistor M9. The non-inverting input terminal of the first comparator A1 is connected to the miller clamp voltage setting circuit 31, the inverting input terminal thereof is connected to the gate of the SiC MOSFET, the output terminal thereof is connected to the gate of the fourth NMOS transistor M9, the drain of the fourth NMOS transistor M9 is connected to the gate of the SiC MOSFET, and the source thereof is connected to the digital ground VSS. The miller clamp voltage setting circuit 31 is configured to generate a miller clamp voltage V f . When the gate-source voltage V of the SiC MOSFET gs Higher than the miller clamp voltage V f When the first comparator A1 outputs a high level, the fourth NMOS tube M9 is conducted, the grid electrode of the SiC MOSFET is connected to the digital ground VSS through the fourth NMOS tube M9, and the quick turn-off of the SiC MOSFET is realized, so that the parasitic capacitance conduction of the SiC MOSFET is avoided.
As shown in fig. 2, the miller clamp voltage setting circuit 31 is connected to the non-inverting input terminal of the first comparator A1 for generating the miller clamp voltage V f . The miller clamp voltage setting circuit 31 in the present embodiment is an active miller clamp voltage setting circuit, and is connected to an external input voltage of 5V. The miller clamp setting circuit 31 includes a first resistor R1 and four voltage dividing resistors. One end of the first resistor R1 is connected with the non-inverting input end of the first comparator A1, the other end of the first resistor R1 is grounded, one end of the four voltage dividing resistors connected in series is connected with the non-inverting input end of the first comparator A1, and the other end of the four voltage dividing resistors is connected with an external input voltage. Miller clamp voltage V f The external input voltage is obtained by dividing the external input voltage through a first resistor R1 and four dividing resistors.
As shown in fig. 2, the miller clamp protection module 30 is further provided with a third switch control unit 32, and the miller clamp voltage V can be controlled by the third switch control unit 32 and the voltage dividing resistor f The magnitude is controlled so as to enhance the effect of the miller clamp protection module 30 and suppress the displacement current, so that the miller clamp protection module is suitable for SiC MOSFETs with different signals.
Specifically, as shown in fig. 2, the third switch control unit 32 includes a plurality of third switch control subunits, each third switch control subunit includes a fourth PMOS transistor and a third register DT, the number of the third switch control subunits is the same as the number of the voltage dividing resistors, whether each voltage dividing resistor is shorted or not is controlled by one third register DT and one fourth PMOS transistor, the source and drain of each fourth PMOS transistor are respectively connected to two ends of one voltage dividing resistor, the gate of each fourth PMOS transistor is connected to one third register DT, the plurality of third registers DT store external program control signals, when the external program control signals in the plurality of third registers DT are changed, the miller clamp voltage V is controlled by the number of the voltage dividing resistors controlled by the turn-off of the fourth PMOS transistor f Is of a size of (a) and (b).
An implementation as shown in FIG. 2In the example, the miller clamp voltage setting circuit 31 includes a first resistor R1 and four voltage dividing resistors R2, R3, R4 and R5, and the third switch control unit 32 includes four fourth PMOS transistors M19, M20, M21, M22 and four third registers DT [0 ]]、DT[1]、DT[2]、DT[3]After the voltage dividing resistors R2, R3, R4, and R5 are connected in series, the other end of the voltage dividing resistor R2 is connected to the gate of the SiC MOSFET, and the other end of the voltage dividing resistor R5 is connected to an external input voltage. The sources and drains of the fourth PMOS tubes M19, M20, M21, M22 are respectively connected in parallel with the voltage dividing resistors R2, R3, R4, R5, and the gates of the fourth PMOS tubes M19, M20, M21, M22 are respectively connected with the third register DT [0 ]]、DT[1]、DT[2]、DT[3]And (5) connection. Third register DT [0 ]]、DT[1]、DT[2]、DT[3]An external program control signal is stored. When the fourth PMOS tube is conducted, the current does not flow through the voltage dividing resistor connected in parallel with the fourth PMOS tube, and the resistance control of the voltage dividing resistor is realized by controlling the conduction quantity of the fourth PMOS tube, so as to control the Miller clamp voltage V f Is of a size of (a) and (b).
Specifically, as shown in FIG. 2, the control signals of the fourth PMOS tubes M19, M20, M21, M22 are respectively derived from the third register DT [0 ]]、DT[1]、DT[2]、DT[3]And a third register DT [0 ]]、DT[1]、DT[2]、DT[3]Is controlled by an external program. By changing the external program control signal, the miller clamp voltage V can be realized f Is programmed to control the programming of (a). For example, when the third register DT [0 ]]、DT[1]、DT[2]、DT[3]When the internal and external program control signals are 0000, the miller clamp voltage V f Is maximum, namely, four fourth PMOS tubes M19, M20, M21 and M22 are all conducted, and the Miller clamp voltage V f Equal to the external input voltage. When the third register DT [0 ]]、DT[1]、DT[2]、DT[3]When the internal and external program control signals are 1111, the miller clamp voltage V f At the minimum, i.e. the four fourth PMOS tubes M19, M20, M21, M22 are all turned off, the Miller clamp voltage V f The external input voltage is divided by voltage dividing resistors R2, R3, R4, and R5.
Further, in order to achieve a refined miller clamp voltage selection, the ratio of the resistances of the first resistor R1, the voltage-dividing resistor R2, the voltage-dividing resistor R3, the voltage-dividing resistor R4, and the voltage-dividing resistor R5 is 1:2:4:8:16, thisThe sectional control of sequentially increasing the voltage dividing resistors according to the binary relation can be realized, sixteen different voltage dividing effects, namely sixteen different Miller clamp voltages V, can be realized according to the resistance value proportional relation of the voltage dividing resistors f And because the resistance value of the voltage dividing resistor is gradually changed, sixteen kinds of Miller clamp voltages V are realized f And uniform change can be realized, and higher adjustment precision can be achieved.
By a programmable method, the adaptive driving of SiC MOSFETs of different models and the adjustment of the switching performance of the SiC MOSFETs can be realized. For example, when driving a SiC MOSFET with a smaller gate capacitance, a smaller gate current I can be selectively output g With less gate charge and charge-discharge time; when a SiC MOSFET with higher gate threshold voltage is driven, a larger gate current I can be selectively output g To increase the gate voltage and on state. And the charging and discharging time of the same SiC MOSFET can be adjusted to adjust the switching performance of the SiC MOSFET. For example, the charging time is appropriately prolonged and the discharging time is shortened, thereby realizing accurate control of the SiC MOSFET gate current. When a SiC MOSFET with larger drain capacitance is driven, a larger miller clamping voltage V can be selected f To enhance the effect of the miller clamp protection circuit and inhibit the displacement current, thereby improving the switching performance and reliability of the SiC MOSFET.
Although the present invention has been disclosed by the above embodiments, the scope of the present invention is not limited thereto, and modifications, substitutions, etc. made to the above components will fall within the scope of the claims of the present invention without departing from the spirit of the present invention.
Claims (1)
1. A driving device of an integrated miller clamp protection circuit for driving a SiC MOSFET, the device comprising:
a charging module connected with the grid electrode of the SiC MOSFET for charging the grid electrode of the SiC MOSFET and controlling the output current to adjust the grid electrode current I of the SiC MOSFET g Is of a size of (2); wherein the charging module comprises a plurality of first current mirror units with output endsA first switch control unit of the plurality of charging channels; wherein the rated current amount of each of the charging channels is different;
a discharging module connected with the grid electrode of the SiC MOSFET for discharging the grid electrode of the SiC MOSFET and regulating the grid electrode current I of the SiC MOSFET by controlling the output current g Size of the material; the discharging module comprises a plurality of second current mirror units with output ends and a plurality of second switch control units with discharging channels; wherein the rated current amount of each of the discharge channels is different;
a miller clamp protection module connected to the gate of the SiC MOSFET for generating a miller clamp voltage V f When the gate-source voltage V of the SiC MOSFET gs Greater than miller clamp voltage V f When the SiC MOSFET is turned off, the SiC MOSFET is prevented from being turned on by mistake; the miller clamp protection module comprises a miller clamp voltage setting circuit with a plurality of output ends and a third switch control unit with a plurality of voltage dividing channels; wherein the rated voltage dividing resistance of each voltage dividing channel is different;
the input end of the first current mirror unit inputs a first input current I 10 The output end of the first switch control unit is connected with the grid electrode of the SiC MOSFET;
the first current mirror unit comprises a first PMOS tube and four second PMOS tubes, wherein the grid electrode and the drain electrode of the first PMOS tube respectively input a first input current I 10 The source electrode of the second PMOS tube is connected with the power supply VDD, and the grid electrodes of the second PMOS tube respectively input a first input current I 10 The source electrode of the second PMOS tube is connected with the power supply VDD, the drain electrode of the second PMOS tube is connected with the grid electrode of the SiC MOSFET through the first switch control unit, and the rated current proportion relation of the four second PMOS tubes is 1:2:4:8, 8;
the first switch control unit comprises four first switch control subunits, each first switch control subunit comprises a third PMOS tube and a first register DH which stores external program control signals, the first switch control subunits are in one-to-one correspondence with the second PMOS tubes, the conduction of each second PMOS tube is controlled by the corresponding first switch control subunit, the source electrode of each third PMOS tube is connected with the drain electrode of one second PMOS tube, the grid electrode of each third PMOS tube is connected with one first register DH, the drain electrode of each third PMOS tube is connected with the grid electrode of the SiC MOSFET, and when external program control signals in the first register DH are changed, the conduction quantity of the second PMOS tubes is controlled by the turn-off of the third PMOS tubes so as to control the output current of the first current mirror unit;
the input end of the second current mirror unit inputs a second input current I 0 The output end of the second switch control unit is connected with the grid electrode of the SiC MOSFET;
the second current mirror unit comprises a first NMOS tube and four second NMOS tubes, wherein the grid electrode and the drain electrode of the first NMOS tube respectively input a second input current I 0 The source electrode of the second NMOS tube is grounded, and the grid electrodes of the second NMOS tube respectively input a second input current I 0 The source electrode of the second NMOS transistor is grounded, the drain electrode of the second NMOS transistor is connected with the grid electrode of the SiC MOSFET through the second switch control unit, and the rated current ratio relation of the four second NMOS transistors is 1:2:4:8, 8;
the second switch control unit comprises four second switch control subunits, each second switch control subunit comprises a third NMOS tube and a second register DL which stores external program control signals, the second switch control subunits are in one-to-one correspondence with the second NMOS tubes, the conduction of each second NMOS tube is controlled through the corresponding second switch control subunit, the source electrode of each third NMOS tube is respectively connected with the drain electrode of one second NMOS tube, the grid electrode of each third NMOS tube is connected with the grid electrode of one second register DL, the drain electrode of each third NMOS tube is connected with the grid electrode of the SiC MOSFET, and when external program control signals in the second registers DL are changed, the conduction quantity of the second NMOS tubes is controlled through the turn-off of the third NMOS tubes so as to control the output current of the second current mirror unit;
the miller clamp protection module comprises a first comparator A1, a miller clamp voltage setting circuit and a fourth NMOS tube, wherein the non-inverting input end of the first comparator A1 is connected with the miller clamp voltage setting circuit, the inverting input end of the first comparator A1 is connected with the grid electrode of the SiC MOSFET, the output end of the first comparator A is connected with the grid electrode of the fourth NMOS tube, the drain electrode of the fourth NMOS tube is connected with the grid electrode of the SiC MOSFET, and the source electrode of the fourth NMOS tube is connected with the digital ground VSS;
the Miller clamp voltage setting circuit comprises a first resistor R1 and four voltage dividing resistors, wherein one end of the first resistor R1 is connected with the non-inverting input end of the first comparator A1, the other end of the first resistor R1 is grounded, one end of the four voltage dividing resistors which are connected in series is connected with the non-inverting input end of the first comparator A1, and the other end of the four voltage dividing resistors is connected with an external input voltage end; the ratio of the resistance values of the first resistor R1 and the four voltage dividing resistors is 1:2:4:8:16;
the miller clamp protection module further comprises a third switch control unit, the third switch control unit is connected in parallel with the voltage dividing resistors, the third switch control unit comprises four third switch control subunits, each third switch control subunit comprises a fourth PMOS tube and a third register DT storing external program control signals, the third switch control subunits are in one-to-one correspondence with the voltage dividing resistors, whether each voltage dividing resistor is in short circuit or not is controlled by the corresponding third switch control subunit, the source electrode and the drain electrode of each fourth PMOS tube are respectively connected with two ends of one voltage dividing resistor, the grid electrode of each fourth PMOS tube is connected with one third register DT, and when external program control signals in a plurality of third registers DT are changed, the number of the voltage dividing resistors is controlled by the fourth PMOS tube to control the miller clamp voltage V f Is of a size of (a) and (b).
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JP2009261020A (en) * | 2009-08-10 | 2009-11-05 | Mitsubishi Electric Corp | Semiconductor device |
| EP2688208A1 (en) * | 2011-07-07 | 2014-01-22 | Fuji Electric Co., Ltd. | Gate drive device |
| CN111404529A (en) * | 2020-04-03 | 2020-07-10 | 电子科技大学 | Segmented direct gate driving circuit of depletion type GaN power device |
| CN116559617A (en) * | 2023-04-23 | 2023-08-08 | 武汉大学 | IGBT collector current on-line detection device and method based on gate current |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US11057029B2 (en) * | 2019-11-25 | 2021-07-06 | Silicon Laboratories Inc. | Gate driver with integrated miller clamp |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2009261020A (en) * | 2009-08-10 | 2009-11-05 | Mitsubishi Electric Corp | Semiconductor device |
| EP2688208A1 (en) * | 2011-07-07 | 2014-01-22 | Fuji Electric Co., Ltd. | Gate drive device |
| CN111404529A (en) * | 2020-04-03 | 2020-07-10 | 电子科技大学 | Segmented direct gate driving circuit of depletion type GaN power device |
| US10911045B1 (en) * | 2020-04-03 | 2021-02-02 | University Of Electronic Science And Technology Of China | Segmented direct gate drive circuit of a depletion mode GaN power device |
| CN116559617A (en) * | 2023-04-23 | 2023-08-08 | 武汉大学 | IGBT collector current on-line detection device and method based on gate current |
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