CN117255401A - Multisource phase self-adaptive tracking synchronization system based on FPGA - Google Patents
Multisource phase self-adaptive tracking synchronization system based on FPGA Download PDFInfo
- Publication number
- CN117255401A CN117255401A CN202311338127.XA CN202311338127A CN117255401A CN 117255401 A CN117255401 A CN 117255401A CN 202311338127 A CN202311338127 A CN 202311338127A CN 117255401 A CN117255401 A CN 117255401A
- Authority
- CN
- China
- Prior art keywords
- signal
- phase
- phase shifter
- representing
- coupling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000012545 processing Methods 0.000 claims abstract description 36
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 7
- 238000003786 synthesis reaction Methods 0.000 claims abstract description 7
- 230000008878 coupling Effects 0.000 claims description 121
- 238000010168 coupling process Methods 0.000 claims description 121
- 238000005859 coupling reaction Methods 0.000 claims description 121
- 239000011159 matrix material Substances 0.000 claims description 60
- 238000000034 method Methods 0.000 claims description 18
- 230000003044 adaptive effect Effects 0.000 claims description 16
- 230000008569 process Effects 0.000 claims description 15
- 238000005259 measurement Methods 0.000 claims description 7
- 230000007704 transition Effects 0.000 claims description 6
- 238000013459 approach Methods 0.000 claims description 3
- 238000012544 monitoring process Methods 0.000 claims description 3
- 230000001105 regulatory effect Effects 0.000 claims description 3
- 230000017105 transposition Effects 0.000 claims description 3
- 230000004044 response Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 241000135164 Timea Species 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000010363 phase shift Effects 0.000 description 1
- 238000001308 synthesis method Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W56/00—Synchronisation arrangements
- H04W56/0035—Synchronisation arrangements detecting errors in frequency or phase
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0602—Systems characterised by the synchronising information used
- H04J3/0617—Systems characterised by the synchronising information used the synchronising signal being characterised by the frequency or phase
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Variable-Direction Aerials And Aerial Arrays (AREA)
Abstract
The invention discloses a multisource phase self-adaptive tracking synchronization system based on an FPGA (field programmable gate array), which comprises a first channel link consisting of a first phase shifter and a first coupler, a second channel link consisting of a second phase shifter and a second coupler, a phase discriminator, an information acquisition unit, an FPGA processing unit and a power combiner; the multi-source phase self-adaptive tracking synchronization system based on the FPGA provided by the invention utilizes an information acquisition unit to convert a radio frequency input signal passing through a phase shifter into a coded digital signal, and utilizes an FPGA processing unit to decode to obtain phase information of the signal, so that the signal phase is controlled adaptively; meanwhile, the FPGA processing unit has the capability of parallel operation, can acquire phase information and can perform self-adaptive tracking control synchronously, and the response efficiency and control precision of the system are improved, so that the signal synthesis efficiency and the stability of the synthesized signals are improved, and the performance of the system is improved.
Description
Technical Field
The invention relates to the fields of computer processing technology and radio frequency microwaves, in particular to a multisource phase self-adaptive tracking synchronization system based on an FPGA.
Background
The signal source (reference) or the reference clock is a key component of various electronic industries including measurement, communication, radar and the like, and is mainly used for a system working clock, a data acquisition clock, a local oscillation reference clock and the like. With the development of technology, the frequency of the acquisition clock is higher and higher, and accordingly, the signal quality of the reference clock is also required to be higher. The higher the clock signal quality, the better the performance of the system.
However, the existing signal synthesis scheme is a power synthesis method, and the problem of signal phase synchronization is not considered by only adding the power rates. Therefore, the signal synthesis efficiency is low, the output power of the synthesized signal is unstable, and the test or detection error is increased in response to the signal quality of the collected data.
Disclosure of Invention
Aiming at the defects in the prior art, the invention provides a multisource phase self-adaptive tracking synchronization system based on an FPGA, which is used for solving the problem that the prior method cannot meet the performance index requirements of certain electronic systems, thereby providing a control system for improving the signal quality.
In order to achieve the aim of the invention, the invention adopts the following technical scheme:
the multi-source phase self-adaptive tracking synchronization system based on the FPGA comprises a first channel link formed by a first phase shifter and a first coupler, a second channel link formed by a second phase shifter and a second coupler, a phase discriminator, an information acquisition unit, an FPGA processing unit and a power combiner;
the first phase shifter is used for carrying out controllable phase adjustment on an input first signal and inputting the first signal into the input end of the first coupler;
the second phase shifter is used for carrying out controllable phase adjustment on an input second signal and inputting the second signal into the input end of the second coupler;
the first coupler is used for transmitting the regulated first signal to the first input end of the power combiner through the through output end, and coupling the first signal to generate a first coupling signal, and transmitting the first coupling signal to the input end of the phase discriminator through the coupling output end;
the second coupler is used for transmitting the adjusted second signal to the second input end of the power combiner through the through output end, and coupling the second signal to generate a second coupling signal, and transmitting the second coupling signal to the input end of the phase discriminator through the coupling output end;
the phase discriminator is used for receiving the first coupling signal and the second coupling signal, carrying out linear operation on the phases of the first coupling signal and the second coupling signal to obtain a phase difference voltage indicating signal, and transmitting the phase difference voltage indicating signal to the input end of the signal acquisition unit through the phase difference indicating output end of the phase discriminator;
the information acquisition unit is used for receiving the phase difference voltage indication signal, converting the phase difference voltage indication signal into a digital coding signal and transmitting the digital coding signal to the input end of the FPGA processing unit through the output end of the information acquisition unit;
the FPGA processing unit is used for initializing the moving angles of the first phase shifter and the second phase shifter, decoding the received digital serial signals to obtain the phase difference true value of the first coupling signals and the second coupling signals, and performing compensation control on the phases of the first phase shifter and the second phase shifter by adopting an adaptive tracking synchronization algorithm;
the power combiner is used for performing power synthesis on the coupling signals output by the first coupler or the second coupler.
Further, the phase discriminator performs linear operation on the phases of the first coupling signal and the second coupling signal, and the specific process of obtaining the phase difference voltage indication signal is as follows:
the phase discriminator performs a difference according to the phase of the received first coupling signal and the phase of the second coupling signal, so as to obtain the phase difference between the first coupling signal and the second coupling signal, namely:
wherein,representing the phase difference of the first coupling signal and the second coupling signal, and (2)>Representing the phase of the first coupling signal, +.>Representing the phase of the second coupled signal;
according to the relationship between the phase difference and the voltage of the obtained first coupling signal and the second coupling signal, a phase difference voltage indication signal is obtained, namely:
wherein,representing the phase difference voltage of the first coupling signal and the second coupling signal.
Further, the specific process of converting the phase difference voltage indication signal into the digital coding signal by the information acquisition unit is as follows:
the information acquisition unit converts the phase difference voltage indication signal into a digital coding signal by using the following formula, namely:
wherein the code represents a digitally encoded signal,representing the phase difference voltage of signal 1 and signal 2, V ADC_ref Representing the reference voltage of the digital-to-analog converter of the information acquisition unit.
Further, the specific process of initializing the shift angles of the first phase shifter and the second phase shifter by the FPGA processing unit is as follows:
the FPGA processing unit controls the initial direction angle of the first phase shifter and the second phase shifter to be 0 degrees.
Further, the specific process of decoding the received digital numbered signals by the FPGA processing unit to obtain the phase difference true value of the first coupling signal and the second coupling signal is as follows:
the FPGA processing unit obtains a phase difference voltage indication signal output by the phase discriminator by inversely solving a digital coding signal, and inversely solving the relation between the phase difference of the first coupling signal and the second coupling signal and the voltage to obtain a phase difference true value of the signal 1 and the signal 2, namely:
wherein,representing the phase difference of the first coupling signal and the second coupling signal, and (2)>Representing the phase of the first coupling signal, +.>Representing the phase of the second coupled signal.
Further, the specific process of the FPGA processing unit adopting the self-adaptive tracking synchronization algorithm to carry out compensation control on the phases of the first phase shifter and the second phase shifter is as follows:
the FPGA processing unit takes the phase difference of the first coupling signal and the second coupling signal as a state variable of the phase shifter, takes the control quantity of the phase shifter as the control quantity of the model, and builds a discrete linear time-invariant dynamic system model to update the control states of the first phase shifter and the second phase shifter, namely:
X k ＝Φ k-1 X k-1 +B k-1 U k-1 +W k-1
y k ＝H k X k +V k
wherein X is k Representing the state variable, Φ, of the phase shifter at the kth time k-1 State transition matrix X representing the k-1 time k-1 Representing the state variable of the phase shifter at time k-1, B k-1 Control matrix representing the k-1 time，U k-1 Represents the control amount of the phase shifter at the k-1 time, W k-1 White noise, y, representing the k-1 time k An observation vector H representing the kth time k An observation matrix representing the kth time, V k Indicating measurement noise at the kth time;
initializing the state and covariance matrix of the phase shifter at the 0 th moment, namely:
wherein,representing the state estimation value, X, of the phase shifter at time 0 0 State variable representing phase shifter at time 0, < ->A covariance matrix representing a state estimation value and a true value of the phase shifter at the 0 th moment, wherein I represents an identity matrix, and T represents transposition;
predicting the state of the phase shifter at the kth time, namely:
wherein,state prediction value of phase shifter at kth time, < >>A state prediction value of the phase shifter at the k-1 time is represented;
predicting a prediction error covariance matrix of the phase shifter at the kth time, namely:
wherein,covariance matrix representing state predicted value and true value of phase shifter at kth time, +.>Covariance matrix representing predicted value and true value of state quantity of phase shifter at k-1 time, +.>State transition matrix Φ representing the k-1 time k-1 Transpose of Q k-1 White noise W representing the k-1 time k-1 Is a covariance matrix of (a);
calculating a Kalman gain matrix of the phase shifter at the kth time, namely:
wherein K is k A Kalman gain matrix representing the phase shifter at the kth time,observation matrix H representing the kth time k Transpose of R k Measurement noise V representing the kth time k Is a covariance matrix of (a);
estimating the state of the phase shifter at the kth time, namely:
wherein,indicating the kth timeA state estimate of the phase shifter;
estimating an estimated error covariance matrix of the phase shifter at the kth time, namely:
wherein,a covariance matrix representing a state estimation value and a true value of the phase shifter at the kth moment, wherein I represents an identity matrix;
updating the true value of the state of the phase shifter at time k-1, namely:
updating the estimated value of the state of the phase shifter at the k-1 time, namely:
updating the estimated value of the error covariance matrix of the phase shifter at the k-1 time, namely:
the process is circulated, if the phase difference between the first coupling signal and the second coupling signal approaches 0, the updating of the control state of the phase shifter is stopped, and monitoring is kept; when the phase difference deviates more greatly again, the control right of the phase shifter is restored to be updated continuously.
The invention has the following beneficial effects:
the multi-source phase self-adaptive tracking synchronization system based on the FPGA provided by the invention utilizes an information acquisition unit to convert a radio frequency input signal passing through a phase shifter into a coded digital signal, and utilizes an FPGA processing unit to decode to obtain phase information of the signal, so that the signal phase is controlled adaptively; meanwhile, the FPGA processing unit has the capability of parallel operation, can acquire phase information and can perform self-adaptive tracking control synchronously, and the corresponding efficiency and control precision of the system are improved, so that the signal synthesis efficiency and the stability of the synthesized signals are improved, and the performance of the system is improved.
Drawings
Fig. 1 is a schematic structural diagram of a multi-source phase adaptive tracking synchronization system based on an FPGA according to the present invention;
fig. 2 is a signal flow diagram of an adaptive tracking synchronization algorithm.
Detailed Description
The following description of the embodiments of the present invention is provided to facilitate understanding of the present invention by those skilled in the art, but it should be understood that the present invention is not limited to the scope of the embodiments, and all the inventions which make use of the inventive concept are protected by the spirit and scope of the present invention as defined and defined in the appended claims to those skilled in the art.
As shown in fig. 1, the multi-source phase self-adaptive tracking synchronization system based on the FPGA comprises a first channel link formed by a first phase shifter and a first coupler, a second channel link formed by a second phase shifter and a second coupler, a phase discriminator, an information acquisition unit, an FPGA processing unit and a power combiner; the first phase shifter is used for carrying out controllable phase adjustment on an input first signal and inputting the first signal into the input end of the first coupler; the second phase shifter is used for carrying out controllable phase adjustment on an input second signal and inputting the second signal into the input end of the second coupler; the first coupler is used for transmitting the regulated first signal to the first input end of the power combiner through the through output end, and coupling the first signal to generate a first coupling signal, and transmitting the first coupling signal to the input end of the phase discriminator through the coupling output end; the second coupler is used for transmitting the adjusted second signal to the second input end of the power combiner through the through output end, and coupling the second signal to generate a second coupling signal, and transmitting the second coupling signal to the input end of the phase discriminator through the coupling output end; the phase discriminator is used for receiving the first coupling signal and the second coupling signal, carrying out linear operation on the phases of the first coupling signal and the second coupling signal to obtain a phase difference voltage indicating signal, and transmitting the phase difference voltage indicating signal to the input end of the signal acquisition unit through the phase difference indicating output end of the phase discriminator; the information acquisition unit is used for receiving the phase difference voltage indication signal, converting the phase difference voltage indication signal into a digital coding signal and transmitting the digital coding signal to the input end of the FPGA processing unit through the output end of the information acquisition unit; the FPGA processing unit is used for initializing the moving angles of the first phase shifter and the second phase shifter, decoding the received digital serial signals to obtain the phase difference true value of the first coupling signals and the second coupling signals, and performing compensation control on the phases of the first phase shifter and the second phase shifter by adopting an adaptive tracking synchronization algorithm; the power combiner is used for performing power synthesis on the coupling signals output by the first coupler or the second coupler.
In this embodiment, fig. 1 is a schematic structural diagram of a multi-source phase adaptive tracking synchronization system based on FPGA. The block in the dashed line of fig. 1 is an adaptive phase synchronization system provided by this embodiment, which includes a first phase shifter, a second phase shifter, a first coupler, a second coupler, a phase discriminator, an information acquisition unit, an FPGA processing unit, and a power combiner; wherein the first phase shifter and the first coupler form a first channel link and are used for receiving and transmitting a first signal (sine wave) transmitted by the signal source 1 or the frequency source; the second phase shifter and the second coupler form a second channel link and are used for receiving and transmitting a second signal (sine wave) transmitted by the signal source 2 or the frequency source; the first signal and the second signal go through the entire channel link. In this embodiment, the FPGA processing unit controls the initial phase shift angles of the first phase shifter and the second phase shifter to be 0 respectively ° And by observing the phase information, corresponding phase compensation control is performed on the first phase shifter or the second phase shifter according to the self-adaptive tracking synchronization algorithm.
Specifically, the phase discriminator performs a linear operation on phases of the first coupling signal and the second coupling signal, and the specific process of obtaining the phase difference voltage indication signal is as follows:
the phase discriminator performs a difference according to the phase of the received first coupling signal and the phase of the second coupling signal, so as to obtain the phase difference between the first coupling signal and the second coupling signal, namely:
wherein,representing the phase difference of the first coupling signal and the second coupling signal, and (2)>Representing the phase of the first coupling signal, +.>Representing the phase of the second coupled signal.
According to the relationship between the phase difference and the voltage of the obtained first coupling signal and the second coupling signal, a phase difference voltage indication signal is obtained, namely:
wherein,representing the phase difference voltage of the first coupling signal and the second coupling signal.
In this embodiment, the first coupler and the second coupler respectively transmit the first coupling signal and the second coupling signal to the input end of the phase detector through the coupling output end thereof, and perform a linear operation on the phases of the two signals by using the phase detector, firstly according to the following stepsObtain the phase difference, and then pass the relation between the phase difference and the voltage +.>And obtaining a phase difference voltage indication signal, and transmitting the phase difference voltage indication signal to the input end of the information acquisition unit through the phase difference indication output end of the phase discriminator.
Specifically, the specific process of converting the phase difference voltage indication signal into the digital coding signal by the information acquisition unit is as follows:
the information acquisition unit converts the phase difference voltage indication signal into a digital coding signal by using the following formula, namely:
wherein the code represents a digitally encoded signal,representing the phase difference voltage of signal 1 and signal 2, V ADC_ref Representing the reference voltage of the digital-to-analog converter of the information acquisition unit.
In this embodiment, after receiving the phase difference voltage indication signal, the information acquisition unit performs the following stepsAnd converting the digital code signal into a digital code signal and transmitting the digital code signal to the FPGA processing unit.
Specifically, the specific process of initializing the shift angles of the first phase shifter and the second phase shifter by the FPGA processing unit is as follows:
the FPGA processing unit controls the initial direction angle of the first phase shifter and the second phase shifter to be 0 degrees.
Specifically, the specific process of decoding the received digital numbered signals by the FPGA processing unit to obtain the phase difference true value of the first coupling signal and the second coupling signal is as follows:
the FPGA processing unit obtains a phase difference voltage indication signal output by the phase discriminator by inversely solving a digital coding signal, and inversely solving the relation between the phase difference of the first coupling signal and the second coupling signal and the voltage to obtain a phase difference true value of the signal 1 and the signal 2, namely:
wherein,representing the phase difference of the first coupling signal and the second coupling signal, and (2)>Representing the phase of the first coupling signal, +.>Representing the phase of the second coupled signal.
Specifically, the specific process of the FPGA processing unit performing compensation control on the phases of the first phase shifter and the second phase shifter by adopting the adaptive tracking synchronization algorithm is as follows:
the FPGA processing unit takes the phase difference of the first coupling signal and the second coupling signal as a state variable of the phase shifter, takes the control quantity of the phase shifter as the control quantity of the model, and builds a discrete linear time-invariant dynamic system model to update the control states of the first phase shifter and the second phase shifter, namely:
X k ＝Φ k-1 X k-1 +B k-1 U k-1 +W k-1
y k ＝H k X k +V k
wherein X is k Representing the state variable of the phase shifter at the kth time, i.e. the phase difference between the first and second coupling signals at the kth time, phi k-1 State transition matrix X representing the k-1 time k-1 Representing the state variable of the phase shifter at time k-1, B k-1 Control matrix representing the k-1 time, U k-1 Representing the control quantity of the phase shifter at the time k-1, namely the control quantity of the first phase shifter or the second phase shifter, W k-1 White noise, y, representing the k-1 time k An observation vector H representing the kth time k An observation matrix representing the kth time, V k Indicating measurement noise at the kth time;
initializing the state and covariance matrix of the phase shifter at the 0 th moment, namely:
wherein,representing the state estimation value, X, of the phase shifter at time 0 0 State variable representing phase shifter at time 0, < ->A covariance matrix representing a state estimation value and a true value of the phase shifter at the 0 th moment, wherein I represents an identity matrix, and T represents transposition;
predicting the state of the phase shifter at the kth time, namely:
wherein,state prediction value of phase shifter at kth time, < >>A state prediction value of the phase shifter at the k-1 time is represented;
predicting a prediction error covariance matrix of the phase shifter at the kth time, namely:
wherein,covariance matrix representing state predicted value and true value of phase shifter at kth time, +.>Covariance matrix representing predicted value and true value of state quantity of phase shifter at k-1 time, +.>State transition matrix Φ representing the k-1 time k-1 Transpose of Q k-1 White noise W representing the k-1 time k-1 Is a covariance matrix of (a);
calculating a Kalman gain matrix of the phase shifter at the kth time, namely:
wherein K is k A Kalman gain matrix representing the phase shifter at the kth time,observation matrix H representing the kth time k Transpose of R k Measurement noise V representing the kth time k Is a covariance matrix of (a);
estimating the state of the phase shifter at the kth time, namely:
wherein,representing a state estimate of the phase shifter at a kth time;
estimating an estimated error covariance matrix of the phase shifter at the kth time, namely:
wherein,a covariance matrix representing a state estimation value and a true value of the phase shifter at the kth moment, wherein I represents an identity matrix;
updating the true value of the state of the phase shifter at time k-1, namely:
updating the estimated value of the state of the phase shifter at the k-1 time, namely:
updating the estimated value of the error covariance matrix of the phase shifter at the k-1 time, namely:
the process is circulated, if the phase difference between the first coupling signal and the second coupling signal approaches 0, the updating of the control state of the phase shifter is stopped, and monitoring is kept; when the phase difference deviates more greatly again, the control right of the phase shifter is restored to be updated continuously.
As shown in fig. 2, fig. 2 is a signal flow diagram of the adaptive tracking synchronization algorithm. In FIG. 2Z -1 Representing a unit time delay operator, i.e. the time minus 1. The adaptive tracking synchronization algorithm adopted in this embodiment calculates a Kalman gain matrix by predicting the state of the phase shifter at the kth time and predicting the error covariance matrix, thereby performing control adjustment on the phase shifter and estimating the kth timeThe state of the phase shifter at the k moment and the estimated error covariance matrix are updated, so that the true value of the state of the phase shifter at the k-1 moment is updated, namely the state of the phase shifter at the previous moment is updated.
The principles and embodiments of the present invention have been described in detail with reference to specific examples, which are provided to facilitate understanding of the method and core ideas of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
Those of ordinary skill in the art will recognize that the embodiments described herein are for the purpose of aiding the reader in understanding the principles of the present invention and should be understood that the scope of the invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific modifications and combinations from the teachings of the present disclosure without departing from the spirit thereof, and such modifications and combinations remain within the scope of the present disclosure.
Claims (6)
1. The multi-source phase self-adaptive tracking synchronization system based on the FPGA is characterized by comprising a first channel link formed by a first phase shifter and a first coupler, a second channel link formed by a second phase shifter and a second coupler, a phase discriminator, an information acquisition unit, an FPGA processing unit and a power combiner;
the first phase shifter is used for carrying out controllable phase adjustment on an input first signal and inputting the first signal into the input end of the first coupler;
the second phase shifter is used for carrying out controllable phase adjustment on an input second signal and inputting the second signal into the input end of the second coupler;
the first coupler is used for transmitting the regulated first signal to the first input end of the power combiner through the through output end, and coupling the first signal to generate a first coupling signal, and transmitting the first coupling signal to the input end of the phase discriminator through the coupling output end;
the second coupler is used for transmitting the adjusted second signal to the second input end of the power combiner through the through output end, and coupling the second signal to generate a second coupling signal, and transmitting the second coupling signal to the input end of the phase discriminator through the coupling output end;
the phase discriminator is used for receiving the first coupling signal and the second coupling signal, carrying out linear operation on the phases of the first coupling signal and the second coupling signal to obtain a phase difference voltage indicating signal, and transmitting the phase difference voltage indicating signal to the input end of the signal acquisition unit through the phase difference indicating output end of the phase discriminator;
the information acquisition unit is used for receiving the phase difference voltage indication signal, converting the phase difference voltage indication signal into a digital coding signal and transmitting the digital coding signal to the input end of the FPGA processing unit through the output end of the information acquisition unit;
the FPGA processing unit is used for initializing the moving angles of the first phase shifter and the second phase shifter, decoding the received digital serial signals to obtain the phase difference true value of the first coupling signals and the second coupling signals, and performing compensation control on the phases of the first phase shifter and the second phase shifter by adopting an adaptive tracking synchronization algorithm;
the power combiner is used for performing power synthesis on the coupling signals output by the first coupler or the second coupler.
2. The FPGA-based multi-source phase adaptive tracking synchronization system of claim 1, wherein the phase discriminator performs a linear operation on phases of the first coupling signal and the second coupling signal, and the specific process of obtaining the phase difference voltage indication signal is as follows:
the phase discriminator performs a difference according to the phase of the received first coupling signal and the phase of the second coupling signal, so as to obtain the phase difference between the first coupling signal and the second coupling signal, namely:
wherein,representing the phase difference of the first coupling signal and the second coupling signal, and (2)>Representing the phase of the first coupling signal, +.>Representing the phase of the second coupled signal;
according to the relationship between the phase difference and the voltage of the obtained first coupling signal and the second coupling signal, a phase difference voltage indication signal is obtained, namely:
wherein,representing the phase difference voltage of the first coupling signal and the second coupling signal.
3. The FPGA-based multisource phase adaptive tracking synchronization system of claim 1, wherein the specific process of converting the phase difference voltage indication signal into the digital encoded signal by the information acquisition unit is:
the information acquisition unit converts the phase difference voltage indication signal into a digital coding signal by using the following formula, namely:
wherein the code represents a digitally encoded signal,representing the phase of signal 1 and signal 2Differential voltage, V ADC_ref Representing the reference voltage of the digital-to-analog converter of the information acquisition unit.
4. The FPGA-based multi-source phase adaptive tracking synchronization system of claim 1, wherein the FPGA processing unit is configured to initialize a shift angle of the first phase shifter and the second phase shifter comprises:
the FPGA processing unit controls the initial shift angle of the first phase shifter and the second phase shifter to be 0 ° 。
5. The FPGA-based multi-source phase adaptive tracking synchronization system of claim 1, wherein the FPGA processing unit decodes the received digital numbered signal to obtain the phase difference true value of the first coupling signal and the second coupling signal comprises:
the FPGA processing unit obtains a phase difference voltage indication signal output by the phase discriminator by inversely solving a digital coding signal, and inversely solving the relation between the phase difference of the first coupling signal and the second coupling signal and the voltage to obtain a phase difference true value of the signal 1 and the signal 2, namely:
wherein,representing the phase difference of the first coupling signal and the second coupling signal, and (2)>Representing the phase of the first coupling signal, +.>Representing the phase of the second coupled signal.
6. The FPGA-based multi-source phase adaptive tracking synchronization system of claim 1, wherein the FPGA processing unit performs compensation control on phases of the first phase shifter and the second phase shifter by using an adaptive tracking synchronization algorithm, which comprises the following specific procedures:
the FPGA processing unit takes the phase difference of the first coupling signal and the second coupling signal as a state variable of the phase shifter, takes the control quantity of the phase shifter as the control quantity of the model, and builds a discrete linear time-invariant dynamic system model to update the control states of the first phase shifter and the second phase shifter, namely:
X k ＝Φ k-1 X k-1 +B k-1 U k-1 +W k-1
y k ＝H k X k +V k
wherein X is k Representing the state variable, Φ, of the phase shifter at the kth time k-1 State transition matrix X representing the k-1 time k-1 Representing the state variable of the phase shifter at time k-1, B k-1 Control matrix representing the k-1 time, U k-1 Represents the control amount of the phase shifter at the k-1 time, W k-1 White noise, y, representing the k-1 time k An observation vector H representing the kth time k An observation matrix representing the kth time, V k Indicating measurement noise at the kth time;
initializing the state and covariance matrix of the phase shifter at the 0 th moment, namely:
wherein,state estimation value representing phase shifter at 0 th moment，X 0 Representing the state variable of the phase shifter at time 0,a covariance matrix representing a state estimation value and a true value of the phase shifter at the 0 th moment, wherein I represents an identity matrix, and T represents transposition;
predicting the state of the phase shifter at the kth time, namely:
wherein,state prediction value of phase shifter at kth time, < >>A state prediction value of the phase shifter at the k-1 time is represented;
predicting a prediction error covariance matrix of the phase shifter at the kth time, namely:
wherein,covariance matrix representing state predicted value and true value of phase shifter at kth time, +.>Covariance matrix representing predicted value and true value of state quantity of phase shifter at k-1 time, +.>State transition matrix Φ representing the k-1 time k-1 Is transposed of (a)，Q k-1 White noise W representing the k-1 time k-1 Is a covariance matrix of (a);
calculating a Kalman gain matrix of the phase shifter at the kth time, namely:
wherein K is k A Kalman gain matrix representing the phase shifter at the kth time,observation matrix H representing the kth time k Transpose of R k Measurement noise V representing the kth time k Is a covariance matrix of (a);
estimating the state of the phase shifter at the kth time, namely:
wherein,representing a state estimate of the phase shifter at a kth time;
estimating an estimated error covariance matrix of the phase shifter at the kth time, namely:
wherein,a covariance matrix representing a state estimation value and a true value of the phase shifter at the kth moment, wherein I represents an identity matrix;
updating the true value of the state of the phase shifter at time k-1, namely:
updating the estimated value of the state of the phase shifter at the k-1 time, namely:
updating the estimated value of the error covariance matrix of the phase shifter at the k-1 time, namely:
the process is circulated, if the phase difference between the first coupling signal and the second coupling signal approaches 0, the updating of the control state of the phase shifter is stopped, and monitoring is kept; when the phase difference deviates more greatly again, the control right of the phase shifter is restored to be updated continuously.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311338127.XA CN117255401B (en) | 2023-10-16 | 2023-10-16 | Multisource phase self-adaptive tracking synchronization system based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311338127.XA CN117255401B (en) | 2023-10-16 | 2023-10-16 | Multisource phase self-adaptive tracking synchronization system based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117255401A true CN117255401A (en) | 2023-12-19 |
| CN117255401B CN117255401B (en) | 2024-04-09 |
Family
ID=89131228
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311338127.XA Active CN117255401B (en) | 2023-10-16 | 2023-10-16 | Multisource phase self-adaptive tracking synchronization system based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117255401B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2232404C1 (en) * | 2002-12-11 | 2004-07-10 | ООО "Информтехнология" | Monopulse radar with through phase channels |
| US20080207138A1 (en) * | 2006-08-04 | 2008-08-28 | Ichiro Aoki | Phase Detector |
| US20190129044A1 (en) * | 2016-07-19 | 2019-05-02 | Southeast University | Cubature Kalman Filtering Method Suitable for High-dimensional GNSS/INS Deep Coupling |
| CN110018506A (en) * | 2019-04-08 | 2019-07-16 | 南京航空航天大学 | Combine track algorithm based on the GNSS double frequency with subtractive combination Kalman filter |
| CN110531393A (en) * | 2019-07-27 | 2019-12-03 | 金华航大北斗应用技术有限公司 | Weak signal tracking based on adaptive Kalman filter |
| CN115333527A (en) * | 2022-07-21 | 2022-11-11 | 中国电子科技集团公司第二十九研究所 | Circuit and method for realizing synchronization of output signals of distributed frequency source |
-
2023
- 2023-10-16 CN CN202311338127.XA patent/CN117255401B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| RU2232404C1 (en) * | 2002-12-11 | 2004-07-10 | ООО "Информтехнология" | Monopulse radar with through phase channels |
| US20080207138A1 (en) * | 2006-08-04 | 2008-08-28 | Ichiro Aoki | Phase Detector |
| US20190129044A1 (en) * | 2016-07-19 | 2019-05-02 | Southeast University | Cubature Kalman Filtering Method Suitable for High-dimensional GNSS/INS Deep Coupling |
| CN110018506A (en) * | 2019-04-08 | 2019-07-16 | 南京航空航天大学 | Combine track algorithm based on the GNSS double frequency with subtractive combination Kalman filter |
| CN110531393A (en) * | 2019-07-27 | 2019-12-03 | 金华航大北斗应用技术有限公司 | Weak signal tracking based on adaptive Kalman filter |
| CN115333527A (en) * | 2022-07-21 | 2022-11-11 | 中国电子科技集团公司第二十九研究所 | Circuit and method for realizing synchronization of output signals of distributed frequency source |
Non-Patent Citations (1)
| Title |
|---|
| 张道东等: "多源相位控制自适应跟踪算法研究", 电子测量技术, vol. 46, no. 8, 30 April 2023 (2023-04-30) * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117255401B (en) | 2024-04-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107765270B (en) | Satellite navigation receiver tracking loop based on Kalman filtering | |
| CN100518163C (en) | Method for fast realization of soft-demodulation and soft-modulation in high-order quadrature amplitude modulation | |
| EP3503405A2 (en) | Adaptive nfc receiver | |
| CN113949607B (en) | Robust wave beam design method for intelligent reflection surface cell-free system | |
| KR20010101457A (en) | Adaptive array communication system and receiver | |
| Aoudia et al. | Towards hardware implementation of neural network-based communication algorithms | |
| CN117255401B (en) | Multisource phase self-adaptive tracking synchronization system based on FPGA | |
| JPH08242190A (en) | Compensator of frequency deviation and its method | |
| US5574751A (en) | Method for a soft-decision modulation system | |
| CN104378787A (en) | Flat rapid fading long-distance channel predicting method based on extension Prony algorithm | |
| CN104247360A (en) | Polar modulation | |
| US20160266186A1 (en) | Kalman Filter For Phase Noise Tracking | |
| CN108173624B (en) | Partial decoding polarization code serial offset decoding circuit and method thereof | |
| JPH1132092A (en) | S/n measuring circuit, transmission power controller and digital communication system | |
| CN113726416B (en) | Satellite communication carrier synchronization method and device and communication equipment | |
| CN116865903A (en) | Intelligent reflection surface-assisted concealed safe transmission method | |
| CN101573932A (en) | Decoding methods and apparatus for MIMO communication systems | |
| CN111628815A (en) | Channel estimation method of satellite VDES system | |
| CN112003626B (en) | LDPC decoding method, system and medium based on navigation message known bits | |
| CN113727283A (en) | Zero-delay correlated information source broadcast communication method | |
| CN116073853B (en) | Radio frequency self-interference elimination system and method | |
| CN107645360B (en) | OvXDM system decoding method and device and OvXDM system | |
| JPWO2005081411A1 (en) | Receiver | |
| JP2007028562A (en) | Space-time code and detection system therefor | |
| KR101483568B1 (en) | Low-complexity Cost Function Calculation for Multiple-input Multiple-output systems |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |