CN115333527A - Circuit and method for realizing synchronization of output signals of distributed frequency source - Google Patents
Circuit and method for realizing synchronization of output signals of distributed frequency source Download PDFInfo
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Abstract
The invention provides a circuit and a method for realizing the synchronization of output signals of a distributed frequency source, wherein the circuit comprises: the signal synchronization unit and the phase-locked loop unit connected with the signal synchronization unit; the signal synchronization unit comprises a first phase shifter, a second phase shifter, a CML divide-by-2 frequency divider, a microwave correlator, a first power coupler, a second power coupler and a first gating switch; the microwave correlator is used for generating a voltage signal which is in direct proportion to the error phase and feeding back the voltage signal to the first phase shifter in real time to control the phase shifting amount of the first phase shifter; and the control end of the second phase shifter is connected with the path calibration information through the first gating switch and is used for eliminating the additional phase shifting quantity of the external synchronous signal. The two phase shifters jointly ensure the synchronization of output signals in a mode of combining closed-loop self-calibration and open-loop calibration. The circuit and the method can well support the flexible reconstruction of the array scale; and a frequency source is not required to have large output driving capability and a complex local oscillator distribution network, so that the power consumption and the circuit complexity are greatly saved.
Description
Technical Field
The invention relates to the technical field of microwave radio frequency integrated circuits, in particular to a circuit and a method for realizing synchronization of output signals of a distributed frequency source.
Background
With the development of 5G communication technology and phased array radar technology, a large-scale phased array system formed by a plurality of millimeter wave phased array chips is widely applied and rapidly developed. One of the major technical challenges in large-scale phased array systems is local oscillator allocation and synchronization. Although theoretically, output signals of the same-frequency distributed integer phase-locked loops adopting the common crystal oscillator are synchronous, because the ambient temperature, the power interference, the reference signal and the radio frequency signal transmission path of the position of the array surface of each phase-locked loop are not equal to each other and are not ideal factors, in reality, the output signals of the phase-locked loops are not synchronous, and the phase difference between the output signals changes along with time. The phase difference of output signals of any two distributed frequency sources consists of a fixed phase error and a random phase error, and the two phase errors need to be calibrated in order to realize the synchronization of the output signals of the frequency sources.
At present, a relatively mature system calibration scheme is used for calibrating a fixed phase error, and for eliminating a random phase error, the method mainly adopted at present is as follows: a single frequency source is adopted to generate local oscillation signals, and local oscillations are provided for each frequency conversion channel through a local oscillation distribution network. Because each local oscillator is from the same source, the phase error of each local oscillator does not change along with the time, and the synchronization of each local oscillator signal can be completed only by calibrating the constant phase difference generated due to different signal transmission paths on the system. But as the array size increases, this approach exhibits more and more significant drawbacks. Firstly, the power consumption consumed by the circuit unit for compensating the power division and path loss of the millimeter wave local oscillator signal becomes unacceptable; secondly, the local oscillator distribution network is more and more complex, and if the processing is not good, electromagnetic interference can be caused to influence the performance of the radio frequency transceiver; thirdly, the local oscillator signals are polluted in the distribution path for long-distance transmission, thereby deteriorating the phase noise performance; finally, the development trend of large-scale arrays is to support flexible array scale reconstruction, and obviously, the scheme cannot support such reconstruction requirements.
Disclosure of Invention
The invention aims to at least solve the problem that the power consumption consumed by a circuit unit for compensating the power distribution and path loss of the millimeter wave local oscillator signal in the existing method for eliminating the random phase error in the prior art becomes unacceptable; as local oscillator distribution networks tend to be complex, the existing methods are easy to cause electromagnetic interference and influence the performance of radio frequency transceivers; the local oscillator signals are polluted in the distribution path for long-distance transmission, so that the phase noise performance is deteriorated; the method can not support the development trend of flexibly reconstructing a large-scale array to the array scale.
To this end, the invention provides a circuit for realizing the output signal synchronization of the distributed frequency source in a first aspect.
A second aspect of the invention provides a method for synchronizing output signals of distributed frequency sources.
The invention provides a circuit for realizing output signal synchronization of a distributed frequency source, which comprises: the device comprises a signal synchronization unit and a phase-locked loop unit connected with the signal synchronization unit;
the signal synchronization unit comprises a first phase shifter, a second phase shifter, a CML divide-by-2 frequency divider, a microwave correlator, a first power coupler, a second power coupler and a first gating switch;
the output end of the phase-locked loop unit is connected with the input end of a first phase shifter, the radio frequency output end of the first phase shifter is respectively connected with the radio frequency input end of a second phase shifter and the input end of the CML divide-by-2 frequency divider, and the radio frequency output end of the second phase shifter is used as the radio frequency output end of a frequency source; the output signals of the CML divide-by-2 frequency divider comprise two paths of output signals I and Q which are orthogonal to each other, the output signals I and Q are coupled to form a pair of signals on a transmission path through a first power coupler and a second power coupler respectively, and the signals are used for synchronous signal output; the output signals I and Q are also directly sent to a microwave correlator and are subjected to correlation operation with external synchronous signals I 'and Q' accessed by the microwave correlator;
the microwave correlator is used for generating a voltage signal which is in direct proportion to the phase quadrature error of two pairs of input signals, the output end of the microwave correlator is connected with the control end of the first phase shifter, and the voltage signal is used for controlling the phase shift amount of the first phase shifter;
and the control end of the second phase shifter is connected with the path calibration information through the first gating switch and is used for eliminating the additional phase shifting quantity of the external synchronous signal.
According to the circuit for realizing the synchronization of the output signals of the distributed frequency source in the technical scheme of the invention, the circuit can also have the following additional technical characteristics:
in the above technical solution, the microwave correlator includes a first mixer, a second mixer, a programmable gain amplifier, a second gating switch, a transconductance amplifier, and a loop filter;
the output signal I of the CML divide-by-2 frequency divider is connected to the first input end of the first frequency mixer, and the external synchronous signal Q' is connected to the second input end of the first frequency mixer; the output signal Q of the CML divide-by-2 frequency divider is connected to the first input end of the second frequency mixer, and the external synchronizing signal I' is connected to the second input end of the second frequency mixer; the output ends of the first frequency mixer and the second frequency mixer are subjected to difference operation to obtain phase discrimination voltage;
the phase discrimination voltage is connected to the input end of the programmable gain amplifier, the output end of the programmable gain amplifier is connected with the input end of a second gating switch, the output end of the second gating switch is connected with the input end of the transconductance amplifier, the output end of the transconductance amplifier is connected with the input end of the loop filter, and the output end of the loop filter is connected with the bias voltage V os And (4) superposing, wherein the superposed signal is accessed to the control end of the first phase shifter.
In the above technical solution, the bias voltage V os In order to make the phase shift amount of the first phase shifter be 180 degrees of voltage, the voltage signal output by the microwave correlator can control the phase shift amount of the first phase shifter to change towards the positive direction and the negative direction.
In the above technical solution, the amplitudes of the output signal I and the output signal Q of the CML divide-by-2 frequency divider are the same; the external synchronization signals I 'and Q' have the same amplitude.
In the above technical solution, the first mixer and/or the second mixer employ a gilbert cell.
In any of the above technical solutions, the path calibration information passes through the first gating switch and then is correlated with the voltage V B Are superposed and connected in parallelTo the control terminal of the second phase shifter, where V B To shift the second phase shifter by a bias voltage of 0.
In any of the above technical solutions, an output end of the second phase shifter is connected with an output driver for increasing output driving capability.
In any of the above technical solutions, the phase-locked loop unit is a type-II phase-locked loop.
In the above technical solution, the phase-locked loop unit includes a phase frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, a pre-divider, and a programmable divider; the input end of the phase frequency detector is connected with a reference input signal, and the output end of the phase frequency detector is connected with the charge pump; the charge pump is connected with a loop filter, the loop filter is connected with the input end of a voltage-controlled oscillator, the output end of the voltage-controlled oscillator is respectively connected with the input end of a first phase shifter and the input end of a pre-frequency divider, the output end of the pre-frequency divider is connected with a programmable frequency divider, and the programmable frequency divider is connected with the input end of a phase frequency detector.
The invention also provides a method for realizing the synchronization of the output signals of the distributed frequency sources.
The invention provides a method for realizing the synchronization of output signals of a distributed frequency source, which adopts a circuit for realizing the synchronization of the output signals of the distributed frequency source in any one of the technical schemes, and comprises the following steps:
s1, sequentially connecting a synchronous signal output end of a frequency source and an external synchronous signal input end of a next frequency source end to end according to the position of each distributed frequency source on the whole array surface to form a daisy chain;
s2, disconnecting the gating switches of all frequency sources to fix the control voltage of the first phase shifter at V os The control voltage of the second phase shifter is fixed at V B ；
S3, starting a phase locking function of the phase-locked loop unit, enabling each distributed phase-locked loop to complete locking, selecting any frequency source as a reference frequency source, keeping a second gating switch in a microwave correlator in the reference frequency source disconnected, simultaneously opening second gating switches in microwave correlators of other frequency sources, switching control ends of first phase shifters in other frequency sources except the reference frequency source to an output end of the microwave correlator, and enabling the distributed frequency sources to enter a phase-coherent mode;
s4, phase coherence between the frequency sources is completed after the synchronous loop is stabilized, the phase difference between any two frequency sources is constant and does not change along with time, and the synchronous loop enters a synchronous mode;
s5, sending a system self-calibration signal to a channel, and determining a fixed phase difference between frequency sources through digital baseband processing after frequency conversion sampling to generate a path calibration signal;
and S6, opening the first gating switch, sending a path calibration signal to the second phase shifter, controlling the second phase shifter to adjust the phase shift quantity, eliminating the fixed phase difference and finishing the synchronization of the distributed frequency source.
In summary, due to the adoption of the technical characteristics, the invention has the beneficial effects that:
the distributed frequency source is less limited by the placement position, can be integrated with a receiving and transmitting frequency conversion channel on a single chip, and is convenient for array scale reconstruction. Each frequency source only carries out synchronous signal output and input transmission with two frequency sources connected, and the signal is a weak signal, so that the inter-chip wiring is very regular and simple, and the radio frequency radiation can be well controlled. Because the local oscillators of the radio frequency transceiving channels all come from the local frequency source of the chip where the channels are located, strong driving force does not need to be provided for local oscillator signals, and power consumption is greatly saved. In order to realize synchronization, the circuit units introduced on the chip are all conventional circuits and are easy to integrate on the chip, and excessive additional power consumption and area overhead are not required to be increased. The first phase shifter calibrates the phase random error in a closed-loop self-calibration mode, and the second phase shifter calibrates the fixed phase error in an open-loop mode, so that the local oscillation phase synchronization precision of the system is jointly guaranteed. In addition, each distributed frequency source under the framework can also ensure the synchronization of output signals without adopting the same crystal oscillator.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
FIG. 1 is a schematic diagram of a circuit for implementing synchronization of output signals of distributed frequency sources according to an embodiment of the present invention;
FIG. 2 is a schematic circuit diagram of a microwave correlator in a circuit for synchronizing output signals of distributed frequency sources according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating interconnection of distributed frequency sources in a method for synchronizing output signals of the distributed frequency sources according to an embodiment of the present invention;
FIG. 4 is a timing diagram illustrating the timing relationship between the stages of a method for synchronizing the output signals of the distributed frequency sources according to an embodiment of the present invention;
fig. 5 is a graph of a calibration process for phase coherence between two frequency sources regardless of path errors in a method for synchronizing output signals of distributed frequency sources according to an embodiment of the present invention.
Wherein, the correspondence between the reference numbers and the component names in fig. 1 to 5 is:
11. a signal synchronization unit; 12. a first phase shifter; 13. a CML divide-by-2 frequency divider; 14. a microwave correlator; 15. a first power coupler; 16. a second power coupler; 17. a second phase shifter; 18. a first gate switch;
21. a voltage controlled oscillator; 22. a pre-divider; 23. a programmable frequency divider; 24. a phase frequency detector/charge pump/phase-locked loop filter; 25. an output driver;
31. a first mixer; 32. a second mixer; 33. a programmable gain amplifier; 34. a second gate switch; 35. a transconductance amplifier; 36. a synchronous loop filter.
Detailed Description
In order that the above objects, features and advantages of the present invention can be more clearly understood, a more particular description of the invention will be rendered by reference to the appended drawings. It should be noted that the embodiments and features of the embodiments of the present application may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, however, the present invention may be practiced otherwise than as specifically described herein, and thus the scope of the present invention is not limited by the specific embodiments disclosed below.
A circuit and method for achieving output signal synchronization of a distributed frequency source according to some embodiments of the present invention is described below with reference to fig. 1 to 5.
Some embodiments of the present application provide a circuit that achieves synchronization of output signals of distributed frequency sources.
As shown in fig. 1 to 5, a first embodiment of the present invention provides a circuit for synchronizing output signals of distributed frequency sources, and the present invention provides a circuit for synchronizing output signals of distributed frequency sources, each frequency source comprising: a signal synchronization unit 11 and a phase-locked loop unit connected thereto;
the signal synchronization unit 11 comprises a first phase shifter 12, a second phase shifter 17, a CML divide-by-2 frequency divider 13, a microwave correlator 14, a first power coupler 15, a second power coupler 16 and a first gating switch 18;
the output end of the phase-locked loop unit is connected with the input end of a first phase shifter 12, the radio frequency output end of the first phase shifter 12 is respectively connected with the input end of a second phase shifter 17 and the input end of a CML divide-by-2 frequency divider 13, the first phase shifter 12 adopts a continuous phase shifter, the output end of the second phase shifter 17 is used as the radio frequency output end of a frequency source, and the output end of the second phase shifter 17 is connected with an output driver 25 for increasing the output driving capability; the CML divide-by-2 frequency divider 13 has the characteristics of high speed and broadband, and is used for generating two paths of signals I and Q which are orthogonal to each other, wherein output signals I and Q are coupled to form a pair of weak signals on a transmission path through a first power coupler 15 and a second power coupler 16 respectively, and the weak signals are used for outputting synchronous signals; the output signals I and Q of the CML frequency divider except 2 are also directly sent to the microwave correlator 14 and are subjected to correlation operation with external synchronous signals I 'and Q' accessed by the microwave correlator 14;
the microwave correlator 14 is used for generating a voltage signal which is proportional to the phase quadrature error of two pairs of input signals and acts on the first phase shifter 12, the output end of the microwave correlator 14 is connected with the control end of the first phase shifter 12, and the voltage signal is used for controlling the phase shift amount of the first phase shifter 12;
i.e. the microwave correlator 14 is arranged to perform a microwave phase discrimination of the phase of the on-chip I/Q signal and the phase of the external synchronization signal I '/Q' to generate a phase difference dependent output voltage for controlling the first phase shifter 12.
The control terminal of the second phase shifter 17 accesses the path calibration information via the first gate switch 18 and is used to remove an additional phase shift amount of the external synchronization signal.
Since the external synchronization signals I 'and Q' come from off-chip and have different additional phase shifts due to different path lengths before entering the microwave correlator 14, the second phase shifter 17 receives the path alignment information and cancels the additional phase shifts. Specifically, the path calibration information, i.e., the control signal from the system, is coupled to the voltage V after passing through the first gate switch 18 B Are superimposed and connected to the control terminal of a second phase shifter 17, where V B To shift the second phase shifter 17 by a bias voltage of 0.
A loop formed by the first phase shifter 12, the CML divide-by-2 frequency divider 13 and the microwave correlator 14 forms a negative feedback loop, that is, if the output phase of the frequency source lags behind the external synchronizing signal, a voltage which reduces the phase shifting amount of the first phase shifter 12 is output after passing through the microwave correlator 14, so that the phase difference of the frequency source relative to the input synchronizing signal is reduced, and if the loop gain is large enough, the phase difference approaches to 0 after the loop is stable; the intensity of the synchronous output signal passing through the first coupler and the second coupler is very weak, which means that a high-frequency strong signal is only transmitted on a single chip, and a weak signal is transmitted between the single chips, so that additional power consumption is not needed for generating and transmitting the coupling signal, and signal crosstalk between the single chips is reduced; the CML divide-by-2 frequency divider 13 has I/Q signal output capability, so that an additional orthogonal signal generating circuit is not needed for correlation operation in the microwave correlator 14, and the circuit complexity is simplified; the first phase shifter 12 realizes real-time calibration of phase errors in a closed-loop mode, so that output signals of the distributed frequency source are coherent, the phase difference is fixed, the second phase shifter 17 receives calibration information from a system in an open-loop mode, synchronization of the distributed frequency source is realized, and the problem of loop instability caused by a loop where the first phase shifter 12 is located is avoided due to the fact that the second phase shifter 17 adopts open-loop calibration.
The phase-locked loop unit adopts a conventional phase-locked loop circuit, and particularly can adopt a type-II type phase-locked loop. The phase-locked loop unit comprises a phase frequency detector, a charge pump, a phase-locked loop filter, a voltage-controlled oscillator 21, a pre-frequency divider 22 and a programmable frequency divider 23; the input end of the phase frequency detector is connected with a reference input signal, and the output end of the phase frequency detector is connected with the charge pump; the charge pump is connected with a phase-locked loop filter, the phase-locked loop filter is connected with an input end of a voltage-controlled oscillator 21, an output end of the voltage-controlled oscillator 21 is respectively connected with a radio frequency input end of a first phase shifter 12 and an input end of a pre-frequency divider 22, an output end of the pre-frequency divider 22 is connected with a programmable frequency divider 23, and the programmable frequency divider 23 is connected with an input end of a phase frequency detector.
The microwave correlator 14 is shown in fig. 2 and includes a first mixer 31, a second mixer 32, a programmable gain amplifier 33, a second gating switch 34, a transconductance amplifier 35 and a synchronous loop filter 36;
the output signal I of the CML divide-by-2 frequency divider 13 is connected to a first input end of the first mixer 31, and the external synchronizing signal Q' is connected to a second input end of the first mixer 31; the output signal Q of the CML divide-by-2 frequency divider 13 is connected to the first input end of the second mixer 32, and the external synchronizing signal I' is connected to the second input end of the second mixer 32; the output ends of the first mixer 31 and the second mixer 32 perform a difference operation through a difference circuit to obtain a phase discrimination voltage;
the phase discrimination voltage is connected to the input end of the programmable gain amplifier 33, the output end of the programmable gain amplifier 33 is connected to the input end of the second gating switch 34, and the second gating switch is turned onThe over-programmable gain amplifier 33 amplifies the phase discrimination voltage, and the programmable gain amplifier 33 is used for controlling loop gain; the output terminal of the second gating switch 34 is connected to the input terminal of a transconductance amplifier 35, the output terminal of the transconductance amplifier 35 is connected to the input terminal of a synchronous loop filter 36, and the output terminal of the synchronous loop filter 36 is connected to a bias voltage V os And (4) superposing, and connecting the superposed signals to the control end of the first phase shifter 12.
Wherein the bias voltage V os In order to shift the phase of the first phase shifter 12 by 180 °, the voltage signal output from the microwave correlator 14 can control the phase shift of the first phase shifter 12 to change in both forward and reverse directions. Assuming that the phase difference between the local synchronous output signal and the external synchronous signal is Δ, the output signal will be output V after passing through the microwave correlator 14 os The voltage of + β · sin (Δ), where β is related to the gain of each circuit of the microwave correlator 14, is finally divided by 2 by the negative feedback loop to generate a signal with a phase difference of 0 ° with respect to the external synchronous input signal, thereby achieving phase synchronization.
The local phase discrimination voltage signal is directly taken out by the CML 2-dividing frequency divider 13, has higher intensity and is connected to an MOS tube used as a switch in the frequency mixer, so that the frequency mixer is ensured to have smaller insertion loss and higher linearity, while an externally input synchronous signal is coupled out and passes through a certain transmission path, has lower intensity, and is connected to a radio frequency signal input MOS tube of the frequency mixer, so that frequency mixing stray is reduced, the linearity requirement of the frequency mixer is reduced, the design difficulty of the frequency mixer is simplified, and preferably, the first frequency mixer 31 and the second frequency mixer 32 can be realized by a Gilbert unit; because two input signals of each mixer are a local large signal and an external synchronous small signal, and the amplitudes of the output signal I and the output signal Q of the CML 2-dividing frequency divider 13 are the same; the amplitudes of the external synchronous signals I 'and Q' are the same, so that the output amplitudes of the two frequency mixers are consistent, and additional amplitude modulation cannot be introduced during difference calculation; the programmable gain amplifier 33 realizes the function of flexibly adjusting the loop gain, and the bandwidth of the programmable gain amplifier 33 should be much larger than the bandwidth of the loop filter, so that the introduced pole does not change the characteristics of the loop filter; the transconductance amplifier 35 and the loop filter are used to control the loop pole-zero distribution function, thereby ensuring sufficient stability of the feedback loop while achieving high gain.
Some embodiments of the present application provide a method of achieving synchronization of distributed frequency source output signals.
A second embodiment of the present invention provides a method for synchronizing output signals of a distributed frequency source, and on the basis of any of the foregoing embodiments, as shown in fig. 1 to 5, a circuit for synchronizing output signals of a distributed frequency source according to any of the foregoing embodiments is adopted, including the following steps:
s1, sequentially connecting a synchronous signal output end of a frequency source and an external synchronous signal input end of a next frequency source end to end according to the position of each distributed frequency source on the whole array surface to form a daisy chain; namely, the first frequency source synchronizing signal output end is connected with the second frequency source external synchronizing signal input end, the second frequency source synchronizing signal output end is connected with the third frequency source external synchronizing signal input end, and the … … Nth frequency source synchronizing signal output is connected back to the first frequency source external synchronizing signal input end;
s2, disconnecting the gating switches of all frequency sources to fix the control voltage of the first phase shifter 12 at V os The control voltage of the second phase shifter 17 is fixed at V B ；
S3, starting a phase locking function of the phase-locked loop unit, enabling each distributed phase-locked loop to complete locking, selecting any frequency source as a reference frequency source, keeping a second gating switch 34 in the microwave correlator 14 in the reference frequency source disconnected, simultaneously opening second gating switches 34 in the microwave correlators 14 of other frequency sources, switching a control end of a first phase shifter 12 in other frequency sources except the reference frequency source to an output end of the microwave correlator 14, and enabling the distributed frequency sources to enter a coherent mode;
s4, phase coherence between the frequency sources is completed after the synchronous loop is stabilized, the phase difference between any two frequency sources is constant and does not change along with time, and the synchronous loop enters a synchronous mode;
s5, sending a system self-calibration signal to a channel, and determining a fixed phase difference between frequency sources through digital baseband processing after frequency conversion sampling to generate a path calibration signal;
and S6, opening the first gating switch 18, sending a path calibration signal to the second phase shifter 17, controlling the second phase shifter 17 to adjust the phase shifting quantity, eliminating the fixed phase difference, and finishing the synchronization of the distributed frequency source.
A first embodiment of the present invention provides a method for synchronizing output signals of a distributed frequency source, which employs a circuit for synchronizing output signals of a distributed frequency source, as shown in fig. 1 to 2, and includes: a signal synchronization unit 11 and a phase-locked loop unit; the signal synchronization unit 11 includes: a first phase shifter 12, a CML divide-by-2 divider 13, a microwave correlator 14, a first power coupler 15, a second power coupler 16, a second phase shifter 17 and a first gating switch 18; the phase-locked loop unit includes: a voltage-controlled oscillator 21, a prescaler 22, a programmable frequency divider 23, a phase frequency detector/charge pump/phase-locked loop filter 24;
the microwave correlator 14 includes a first mixer 31, a second mixer 32, a programmable gain amplifier 33, a second gate switch 34, a transconductance amplifier 35, and a synchronous loop filter 36.
The first gating switch 18 and the second gating switch 34 of all distributed frequency sources are turned off, and the voltage of the control end of the first phase shifter 12 is fixed to be V os The voltage at the control terminal of the second phase shifter 17 is fixed to V B In which V is os Is a control voltage, V, for shifting the phase of the first phase shifter 12 by 180 DEG B If the control voltage is such that the phase shift amount of the second phase shifter 17 is 0 °, the phase shift amount of the first phase shifter 12 is fixed to 180 ° and the phase shift amount of the second phase shifter 17 is fixed to 0 °. The type-II phase-locked loop composed of the voltage-controlled oscillator 21, the prescaler 22, the programmable frequency divider 23 and the phase frequency detector/charge pump/loop filter 24 respectively complete frequency and phase locking.
After the phase-locked loop is locked, the second gating switch 34 is turned on, and the control end of the first phase shifter 12 is connected with the output end of the microwave correlator 14, so that the coherent mode is started. At this time, the signals have random phase errors at the input of the microwave correlator 14, since the phase-locked loops are not yet coherent. Assuming that the random phase difference between the local I and Q phase detection signals passing through the CML divider-by-2 13 and the synchronous input signals I 'and Q' from off-chip at the input end of the microwave correlator 14 is θ, the signals at A, B, C, D are:
A＝A 1 cos(ωt/2+θ/2+φ)；
B＝A 1 cos(ωt/2+θ/2+π/2+φ)；
C＝A 2 cos(ωt/2-θ/2+φ)；
D＝A 2 cos(ωt/2-θ/2+π/2+φ)；
through the correlation operation of the microwave correlator 14, the change amount of the voltage at the point E is:
ΔE＝H 1 ·H 2 ·G m ·Z·A 1 ·A 2 ·sin(θ)＝βsin(θ)；
wherein H 1 For the conversion gains of the first mixer 31 and the second mixer 32, H 2 Is the gain of a variable gain amplifier, G m For transconductance amplifier 35 gain, Z is the impedance transfer function of the synchronous loop filter 36.
If the voltage-phase conversion function of the first phase shifter 12 is K, the first phase shifter 12 will generate a phase shift amount of K · β sin (θ), thereby reducing the phase error of the I and Q signals and the I 'and Q' signals at the input of the microwave correlator 14. The overall process is shown to produce a positive Δ V at point E if the I and Q signals are in phase lead with respect to I 'and Q', which increases the amount of phase shift of the first phase shifter 12, thereby retarding the phase at point F from the previous time, and reducing the phase difference between the I/Q signal and the I '/Q' signal. Because the random phase drift is slowly changed, the response speed of the feedback loop is much higher than the random phase drift speed, if the synchronous loop has enough gain, the phase difference between the I and Q signals and the I 'and Q' signals tends to 0 degrees after the loop is stabilized, and the loop gain and the loop stability are jointly ensured by the programmable gain amplifier 33, the transconductance amplifier 35 and the synchronous loop filter 36. At this time, phase coherence is achieved between the distributed frequency sources, the first phase shifter 12 dynamically calibrates the random phase error between the distributed frequency sources in real time, and the circuit starts to enter a synchronization mode.
In the synchronous mode, the system sends on-chip self-checking signals to the radio frequency input end of the frequency conversion channel, detects fixed phase errors among all distributed frequency sources through the processes of frequency conversion, sampling, digital signal processing and the like, generates corresponding phase control signals, and sends the corresponding phase control signals to the second phase shifters 17 in all frequency sources through the first gating switches 18 so as to compensate the fixed phase errors generated by non-ideal factors. The calibration process is open loop calibration, the control signal is not changed with time after being written into the second phase shifter 17, and after the phase is stable, each distributed frequency source can complete output signal synchronization.
Specifically, in the present embodiment, output signals of 4 distributed frequency sources are synchronized, and the connection relationship is as shown in fig. 3. The method for realizing the synchronization of the output signals comprises the following steps: the first frequency source couples a synchronous signal from the output end of the CML divide-by-2 frequency divider 13 through a first power coupler 15 and a second power coupler 16, and the synchronous signal is sent to the synchronous signal input end of the second frequency source through a transmission line; the second frequency source couples out a synchronous signal from the output end of the CML divide-by-2 frequency divider 13 through a power coupler and sends the synchronous signal to the synchronous signal input end of a third frequency source; the third frequency source couples out a synchronous signal from the output end of the CML divide-by-2 frequency divider 13 through the power coupler and sends the synchronous signal to the synchronous signal input end of the fourth frequency source; finally, the fourth frequency source synchronous output signal is sent back to the first frequency source synchronous signal input end. The first gate switch 18 and the second gate switch 34 of each frequency source are turned off, and the control level of the first phase shifter 12 is fixed to V os The phase shift amount is fixed at 180 DEG, and the control level of the second phase shifter 17 is fixed at V B The phase shift amount is fixed at 0 degree; starting the phase-locked loop to complete locking, keeping the second gating switch 34 of the first frequency source off, switching on the second gating switches 34 of the other frequency sources, and connecting the control ends of the first phase shifters 12 in the second to fourth frequency sources to the output end of the microwave correlator 14, wherein the second frequency source is coherent with the first frequency source as a reference, the third frequency source is coherent with the second frequency source as a reference, and the fourth frequency source is coherent with the third frequency source as a referenceRow coherent; after the coherent mode is completed, phase difference among all distributed frequency sources is fixed, system self-calibration signals are sent to different frequency sources through a strain frequency channel, the fixed phase errors are determined through the processes of frequency conversion, sampling, digital processing and the like, and corresponding control signals are generated; and (3) the first gating switch 18 is conducted, a control signal is sent to the first gating switch 18, the phase shifting amount of the second phase shifter 17 is controlled, the calibration of the fixed phase error is completed, and the synchronization of the output signal of the frequency source is realized. The timing relationship of the whole process is shown in fig. 4.
Fig. 5 shows the phase calibration of two of the 4 distributed frequency sources, where the technique of performing phase synchronization with fixed phase difference is well-established, and only the coherent calibration of the output signals of the two frequency sources with initial phase difference and random phase drift is shown here, and the phase fixed difference caused by the path error of the synchronization signal is ignored here because the path error can be calibrated in the synchronization stage. Assuming that the initial phase difference of the two signals is 50 °, the phase difference drifts randomly with time without the circuit and method of the present invention, when the circuit and method of the present invention are used, the phase error of the two signals is calibrated to a fixed phase difference (here 0 °) associated only with the path inconsistency of the synchronization signal in a very short time, and the phase difference does not change with time for a sufficiently long time.
In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (10)
1. A circuit for synchronizing output signals of distributed frequency sources, comprising: a signal synchronization unit (11) and a phase-locked loop unit connected thereto;
the signal synchronization unit (11) comprises a first phase shifter (12), a second phase shifter (17), a CML divide-by-2 frequency divider (13), a microwave correlator (14), a first power coupler (15), a second power coupler (16) and a first gating switch (18);
the output end of the phase-locked loop unit is connected with the radio frequency input end of a first phase shifter (12), the radio frequency output end of the first phase shifter (12) is respectively connected with the radio frequency input end of a second phase shifter (17) and the input end of a CML divide-by-2 frequency divider (13), and the output end of the second phase shifter (17) is used as the radio frequency output end of a frequency source; the output signal of the CML divide-by-2 frequency divider (13) comprises two paths of output signals I and Q which are orthogonal to each other, the output signals I and Q are respectively coupled to a pair of signals on a transmission path through a first power coupler (15) and a second power coupler (16), and the signals are used for synchronous signal output; the output signals I and Q are also directly sent to a microwave correlator (14) and are operated with external synchronous signals I 'and Q' accessed by the microwave correlator (14);
the microwave correlator (14) is used for generating a voltage signal which is proportional to the phase quadrature error of two pairs of input signals, the output end of the microwave correlator (14) is connected with the control end of the first phase shifter (12), and the voltage signal is used for controlling the phase shifting amount of the first phase shifter (12);
the control terminal of the second phase shifter (17) is connected to the path calibration information via a first gating switch (18) and is used for eliminating the additional phase shift amount of the external synchronization signal.
2. A circuit for synchronizing output signals of distributed frequency sources according to claim 1, wherein the microwave correlator (14) comprises a first mixer (31), a second mixer (32), a programmable gain amplifier (33), a second gating switch (34), a transconductance amplifier (35) and a synchronization loop filter (36);
the output signal I of the CML divide-by-2 frequency divider (13) is connected to the first input end of the first mixer (31), and the external synchronous signal Q' is connected to the second input end of the first mixer (31); the output signal Q of the CML divide-by-2 frequency divider (13) is connected to the first input end of the second mixer (32), and the external synchronizing signal I' is connected to the second input end of the second mixer (32); the output ends of the first mixer (31) and the second mixer (32) are subjected to difference operation to obtain phase discrimination voltage;
the phase detection voltage is connected to the input end of a programmable gain amplifier (33), the output end of the programmable gain amplifier (33) is connected with the input end of a second gating switch (34), the output end of the second gating switch (34) is connected with the input end of a transconductance amplifier (35), the output end of the transconductance amplifier (35) is connected with the input end of a synchronous loop filter (36), and the output end of the synchronous loop filter (36) is connected with a bias voltage V os And (3) superposing, and connecting the superposed signals to a control end of the first phase shifter (12).
3. The circuit of claim 2, wherein the bias voltage V is greater than the voltage V os In order to shift the phase of the first phase shifter (12) by 180 degrees, the voltage signal output by the microwave correlator (14) controls the phase shift of the first phase shifter (12) to change towards the positive direction and the negative direction.
4. The circuit for realizing the output signal synchronization of the distributed frequency source as recited in claim 2, characterized in that the output signal I and the output signal Q of the CML divide-by-2 frequency divider (13) have the same amplitude; the external synchronization signals I 'and Q' have the same amplitude.
5. A circuit for synchronizing output signals of distributed frequency sources according to claim 2, characterized in that the first mixer (31) and/or the second mixer (32) is implemented as a gilbert cell.
6. A circuit for synchronizing output signals of distributed frequency sources according to any one of claims 1 to 5, characterized in that the path calibration information is synchronized with the voltage V after passing through the first gating switch (18) B Are superimposed and connected to the control terminal of a second phase shifter (17), where V B The second phase shifter 17 shifts the bias voltage by 0.
7. A circuit for realizing output signal synchronization of distributed frequency sources according to any one of claims 1 to 5, characterized in that an output driver (25) for increasing output driving capability is connected to the output end of the second phase shifter (17).
8. The circuit for realizing the output signal synchronization of the distributed frequency source according to any one of claims 1 to 5, wherein the phase-locked loop unit is a type-II phase-locked loop.
9. The circuit for realizing output signal synchronization of a distributed frequency source according to claim 8, wherein the phase-locked loop unit comprises a phase frequency detector, a charge pump, a phase-locked loop filter, a voltage-controlled oscillator (21), a prescaler (22) and a programmable frequency divider (23); the input end of the phase frequency detector is connected with a reference input signal, and the output end of the phase frequency detector is connected with a charge pump; the charge pump is connected with a phase-locked loop filter, the phase-locked loop filter is connected with the input end of a voltage-controlled oscillator (21), the output end of the voltage-controlled oscillator (21) is respectively connected with the input end of a first phase shifter (12) and the input end of a pre-frequency divider (22), the output end of the pre-frequency divider (22) is connected with a programmable frequency divider (23), and the programmable frequency divider (23) is connected with the input end of a phase frequency detector.
10. A method for synchronizing output signals of distributed frequency sources, wherein a circuit for synchronizing output signals of distributed frequency sources according to any one of claims 1 to 9 is adopted, and the method comprises the following steps:
s1, sequentially connecting a synchronous signal output end of a frequency source and an external synchronous signal input end of a next frequency source end to end according to the position of each distributed frequency source on the whole array surface to form a daisy chain;
s2, switching off the gating switches of all frequency sources to fix the control voltage of the first phase shifter (12) at V os The control voltage of the second phase shifter (17) is fixed at V B ；
S3, starting a phase locking function of the phase-locked loop unit, enabling each distributed phase-locked loop to complete locking, selecting any frequency source as a reference frequency source, keeping a second gating switch (34) in a microwave correlator (14) in the reference frequency source disconnected, simultaneously opening second gating switches (34) in microwave correlators (14) of other frequency sources, switching a control end of a first phase shifter (12) in other frequency sources except the reference frequency source to an output end of the microwave correlator (14), and enabling the distributed frequency sources to enter a coherent mode;
s4, after the synchronous loop is stabilized, phase coherence between the frequency sources is completed, the phase difference between any two frequency sources is constant and does not change along with time, and the synchronous loop enters a synchronous mode;
s5, sending a system self-calibration signal to a channel, and determining a fixed phase difference between frequency sources through digital baseband processing after frequency conversion sampling to generate a path calibration signal;
and S6, opening the first gating switch (18), sending a path calibration signal to the second phase shifter (17), controlling the second phase shifter (17) to adjust the phase shift quantity, eliminating the fixed phase difference and finishing the synchronization of the distributed frequency source.
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| CN117255401A (en) * | 2023-10-16 | 2023-12-19 | 四川轻化工大学 | Multisource phase self-adaptive tracking synchronization system based on FPGA |
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| CN117255401A (en) * | 2023-10-16 | 2023-12-19 | 四川轻化工大学 | Multisource phase self-adaptive tracking synchronization system based on FPGA |
| CN117255401B (en) * | 2023-10-16 | 2024-04-09 | 四川轻化工大学 | Multisource phase self-adaptive tracking synchronization system based on FPGA |
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