CN117254802A - Phase-locked loop circuit, chip, module equipment and electronic equipment - Google Patents
Phase-locked loop circuit, chip, module equipment and electronic equipment Download PDFInfo
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- CN117254802A CN117254802A CN202311277191.1A CN202311277191A CN117254802A CN 117254802 A CN117254802 A CN 117254802A CN 202311277191 A CN202311277191 A CN 202311277191A CN 117254802 A CN117254802 A CN 117254802A
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- 238000000034 method Methods 0.000 claims description 24
- 230000008569 process Effects 0.000 claims description 14
- 238000004891 communication Methods 0.000 claims description 11
- 230000009471 action Effects 0.000 claims description 9
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- 238000004590 computer program Methods 0.000 description 9
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- 238000012986 modification Methods 0.000 description 6
- 230000004048 modification Effects 0.000 description 6
- 230000001105 regulatory effect Effects 0.000 description 6
- 230000001276 controlling effect Effects 0.000 description 5
- 238000012545 processing Methods 0.000 description 5
- 230000008878 coupling Effects 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- 238000005859 coupling reaction Methods 0.000 description 3
- 238000013016 damping Methods 0.000 description 3
- 230000003287 optical effect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 238000001228 spectrum Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000002277 temperature effect Effects 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
- H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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Abstract
The application discloses a phase-locked loop circuit, a chip, module equipment and electronic equipment, relates to the circuit field, and can reduce the in-band noise of the phase-locked loop circuit. A phase locked loop circuit comprising: the feedback unit comprises a reference input end, a feedback output end and a feedback end, wherein a proportional path loop and an integral path loop which are connected in parallel are arranged between the reference input end and the feedback output end, the integral path loop is used for providing a first bias current for the feedback output end under the driving of a reference signal and a feedback signal, and the proportional path loop is used for providing a second bias current for the feedback output end under the driving of the reference signal and the feedback signal; the feedback unit is used for adjusting the frequency of the output signal output by the feedback output end under the control of the first bias current and the second bias current so as to reduce the difference between the frequency of the feedback signal and the frequency of the reference signal and/or reduce the difference between the phases of the feedback signal and the reference signal.
Description
Technical Field
The present disclosure relates to the field of circuit technologies, and in particular, to a phase-locked loop circuit, a chip, a module device, and an electronic device.
Background
At present, PLL (Phase Locked Loop ) is widely used as a clock generator in various SOCs (System on Chip). The high performance phase locked loop design needs to take into account the effects of PVT (process, voltage, temperature, process, voltage and temperature). As integrated circuit processes enter deep submicron, the design of wideband, high-speed, low-jitter, low-power phase-locked loops using conventional structures presents a significant challenge. However, in the conventional phase-locked loop structure, in-band noise is large.
Disclosure of Invention
The embodiment of the application provides a phase-locked loop circuit, a chip, a module device and electronic equipment, which can reduce in-band noise of the phase-locked loop circuit.
In a first aspect of an embodiment of the present application, there is provided a phase-locked loop circuit, including:
the feedback unit comprises a reference input end, a feedback output end and a feedback end, wherein the reference input end is used for providing a reference signal, the feedback output end is used for outputting an output signal, and the feedback end is used for providing a feedback signal;
a proportional path loop and an integral path loop which are connected in parallel are arranged between the reference input end and the feedback output end, the integral path loop is used for providing a first bias current to the feedback output end under the driving of the reference signal and the feedback signal, and the proportional path loop is used for providing a second bias current to the feedback output end under the driving of the reference signal and the feedback signal;
The feedback unit is used for adjusting the frequency of the output signal output by the feedback output end under the control of the first bias current and the second bias current so as to reduce the difference between the frequency of the feedback signal and the frequency of the reference signal and/or reduce the difference between the phases of the feedback signal and the reference signal.
In some embodiments, the feedback unit includes: the device comprises a phase frequency detector, a voltage-controlled oscillator and a frequency divider, wherein the output end of the voltage-controlled oscillator is connected with the feedback output end, the reference input end and the feedback end are respectively connected with the input end of the phase frequency detector, and the frequency divider is arranged between the feedback output end and the feedback end;
the frequency divider is used for dividing the output signal output by the voltage-controlled oscillator to obtain the feedback signal, and the phase frequency detector is used for receiving the reference signal and the feedback signal;
the proportional path loop and the integral path loop which are connected in parallel are arranged between the output end of the phase frequency detector and the input end of the voltage-controlled oscillator, the integral path loop is used for providing the first bias current for the voltage-controlled oscillator under the action of the output signal of the phase frequency detector, and the proportional path loop is used for providing the second bias current for the voltage-controlled oscillator under the action of the output signal of the phase frequency detector;
The voltage controlled oscillator is configured to adjust a frequency of an output signal under control of the first bias current and the second bias current to reduce a difference between frequencies of the feedback signal and the reference signal and/or to reduce a difference between phases of the feedback signal and the reference signal.
In some embodiments, the voltage controlled oscillator is configured to adjust the frequency of the output signal under control of the first bias current and the second bias current to match the frequency of the feedback signal to the reference signal and/or to match the phase of the feedback signal to the reference signal.
In some embodiments, the integrating path loop includes a first charge pump, a first charge storage, and a first current scaling circuit, the first charge storage disposed between the first charge pump and the first current scaling circuit, the first charge pump electrically connected to the phase frequency detector, the first current scaling circuit electrically connected to the voltage controlled oscillator;
the proportional path loop comprises a second charge pump and a second current proportional circuit, wherein the second charge pump is electrically connected with the phase frequency detector, and the second current proportional circuit is electrically connected with the voltage-controlled oscillator.
In some embodiments, the phase-locked loop circuit further comprises:
a second charge storage electrically connected to the first current scaling circuit, the second current scaling circuit, and the voltage controlled oscillator;
the first charge pump is used for controlling the charge and discharge of the first charge storage according to the output signal of the phase frequency detector;
the first bias current and the second bias current are used for controlling charging and discharging of the second charge storage, and the second charge storage is used for noise reduction filtering of the phase-locked loop circuit in the charging and discharging process.
In some embodiments, the input end of the first charge pump is electrically connected with the phase frequency detector, the output end of the first charge pump, the input end of the first current proportion circuit and one input end of the second current proportion circuit are all electrically connected with a first potential point, one end of the first charge storage is electrically connected with the first potential point, and the other end of the first charge storage is used for being connected with a fixed potential;
the output end of the first current proportion circuit, the output end of the second current proportion circuit and the input end of the voltage-controlled oscillator are all electrically connected to a second potential point, one end of the second charge storage is electrically connected with the second potential point, and the other end of the second charge storage is grounded.
In some embodiments, the phase-locked loop circuit further comprises:
a starting circuit, one end of which is electrically connected with the first potential point, and the other end of which is used for accessing an enabling signal;
the starting circuit is used for controlling the charge and discharge of the first charge storage under the control of the enabling signal, and the starting circuit is used for rapidly pulling the potential of the first potential point from a high level to a threshold voltage under the control of the enabling signal so as to rapidly start the phase-locked loop circuit.
In some embodiments, the first current scaling circuit has a circuit coefficient greater than a circuit coefficient of the second current scaling circuit; and/or the number of the groups of groups,
the first charge storage and/or the second charge storage comprises a capacitor.
In some embodiments, the output signal of the phase frequency detector comprises a first pulse signal and a second pulse signal;
in the case that the frequency of the reference signal is greater than the frequency of the feedback signal, the pulse width of the first pulse signal is greater than the pulse width of the second pulse signal;
in the case that the frequency of the reference signal is smaller than the frequency of the feedback signal, the pulse width of the first pulse signal is smaller than the pulse width of the second pulse signal.
In some embodiments, where the first and second charge storages include capacitors, the capacitance value of the first charge storage is greater than the capacitance value of the second charge storage.
In some embodiments, the voltage controlled oscillator comprises a single-ended inverter chain voltage controlled oscillator comprising three or more odd number of inverters electrically connected end to end in sequence; and/or the number of the groups of groups,
the first current scaling circuit and the second current scaling circuit each comprise a plurality of parallel current branches, each current branch comprising a current source and a switch.
In a second aspect of embodiments of the present application, there is provided a chip, including:
a phase locked loop circuit as claimed in the first aspect.
In a second aspect of the embodiments of the present application, there is provided a module apparatus, including:
the communication module is used for carrying out internal communication of the module equipment or carrying out communication between the module equipment and external equipment;
the power supply module is used for providing electric energy for the module equipment;
the storage module is used for storing data and instructions;
the chip of the second aspect.
In a fourth aspect of embodiments of the present application, there is provided an electronic device, including:
The chip as claimed in the second aspect and/or the modular device as claimed in the third aspect.
According to the phase-locked loop circuit, the proportional path loop and the integral path loop which are connected in parallel are arranged, and the self-bias effect can be generated by utilizing the first bias current generated by the integral path loop and the second bias current generated by the proportional path loop. A phase locked loop circuit with self-bias can achieve a wider operating frequency range and low input tracking jitter, thereby reducing phase errors. The oscillation frequency of the voltage controlled oscillator is adjusted by the bias current, thereby changing the phase of the feedback signal. Finally, the difference between the frequencies of the feedback signal and the reference signal is reduced by the negative feedback principle. According to the phase-locked loop circuit, the frequency of the output signal of the voltage-controlled oscillator is regulated by utilizing the control of the first bias current and the second bias current, so that the difference between the frequency of the feedback signal and the frequency of the reference signal is reduced, the difference between the phase of the feedback signal and the phase of the reference signal is reduced, the stability of the phase-locked loop circuit can be ensured, in-band noise can be greatly reduced or eliminated, and then the clock jitter of the phase-locked loop circuit is reduced.
Drawings
Fig. 1 is a schematic block diagram of a phase-locked loop circuit according to an embodiment of the present application;
fig. 2 is a schematic block diagram of another phase-locked loop circuit according to an embodiment of the present application;
fig. 3 is a schematic block diagram of a phase-locked loop circuit according to an embodiment of the present application;
fig. 4 is a schematic block diagram of a phase-locked loop circuit according to an embodiment of the present application;
fig. 5 is a schematic block diagram of another phase-locked loop circuit according to an embodiment of the present application;
fig. 6 is a schematic diagram of a load-symmetric differential delay buffer stage circuit according to an embodiment of the present application;
FIG. 7 is a schematic block diagram of a single-ended inverter chain provided in an embodiment of the present application;
FIG. 8 is a schematic diagram of a current scaling circuit according to an embodiment of the present disclosure;
fig. 9 is a schematic diagram of a phase noise spectrum of a phase-locked loop circuit according to an embodiment of the present disclosure;
FIG. 10 is a schematic block diagram of a chip according to an embodiment of the present application;
FIG. 11 is a schematic block diagram of a module device according to an embodiment of the present disclosure;
FIG. 12 is a schematic block diagram of an electronic device according to an embodiment of the present application;
fig. 13 is a schematic block diagram of another electronic device according to an embodiment of the present application.
Detailed Description
In order to better understand the technical solutions provided by the embodiments of the present specification, the following detailed description of the technical solutions of the embodiments of the present specification is made through the accompanying drawings and the specific embodiments, and it should be understood that the specific features of the embodiments of the present specification are detailed descriptions of the technical solutions of the embodiments of the present specification, and not limit the technical solutions of the present specification, and the technical features of the embodiments of the present specification may be combined with each other without conflict.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. The term "two or more" includes two or more cases.
At present, the phase-locked loop is widely applied to various system-level chips as a clock generator. High performance phase locked loop designs need to take into account process, voltage and temperature effects. As integrated circuit processes enter deep submicron, the design of wideband, high-speed, low-jitter, low-power phase-locked loops using conventional structures presents a significant challenge. However, in the conventional phase-locked loop structure, in-band noise is large.
In view of the above, embodiments of the present application provide a pll circuit, a chip, a module device, and an electronic device, which can reduce in-band noise of the pll circuit.
In a first aspect of the embodiments of the present application, a phase-locked loop circuit is provided, and fig. 1 is a schematic block diagram of the phase-locked loop circuit provided in the embodiments of the present application. As shown in fig. 1, the phase-locked loop circuit includes: a feedback unit 10, the feedback unit 10 including a reference input 11, a feedback output 12 and a feedback terminal 13, the reference input 11 being used for providing a reference signal fref, the feedback output 12 being used for outputting an output signal fvco, the feedback terminal 13 being used for providing a feedback signal fbk; a proportional path loop 400 and an integral path loop 500 are arranged in parallel between the reference input 11 and the feedback output 12, the integral path loop 500 being configured to provide a first bias current to the feedback output 12 driven by the reference signal fbk and the feedback signal fbk, the proportional path loop 400 being configured to provide a second bias current to the feedback output 12 driven by the reference signal fref and the feedback signal fbk; the feedback unit 10 is configured to adjust the frequency of the output signal output by the feedback output terminal 12 under the control of the first bias current and the second bias current, so as to reduce the difference between the frequencies of the feedback signal fbk and the reference signal fref, and/or reduce the difference between the phases of the feedback signal fbk and the reference signal fbk.
The phase-locked loop circuit provided by the embodiment of the application, through arranging the proportional path loop 400 and the integral path loop 500 which are connected in parallel, can generate a self-bias effect by utilizing the first bias current generated by the integral path loop 500 and the second bias current generated by the proportional path loop 400, and can allow the circuit to select the optimal direct current working point to work. The bias point is established substantially by the operating frequency of the phase locked loop circuit by reference to other bias voltages and currents that have been generated. The phase-locked loop circuit with self-bias can limit WN/WREF to be constant, WREF and WN refer to the angular frequency of the reference clock and the loop bandwidth respectively, a wider working frequency range and low input tracking jitter can be obtained, and further phase errors are reduced. The oscillation frequency of the voltage controlled oscillator is adjusted by the bias voltage, thereby changing the phase of the feedback signal. Finally, the difference between the frequencies of the feedback signal and the reference signal is reduced by the negative feedback principle. According to the phase-locked loop circuit provided by the embodiment of the application, the frequency of the output signal is regulated by utilizing the control of the first bias current and the second bias current, so that the difference between the frequencies of the feedback signal fbk and the reference signal fref is reduced, the difference between the phases of the feedback signal fbk and the reference signal fref is reduced, the stability of the phase-locked loop circuit can be ensured, in-band noise can be greatly reduced or eliminated, and then the clock jitter of the phase-locked loop circuit is reduced.
In some embodiments, fig. 2 is a schematic block diagram of another phase-locked loop circuit provided in an embodiment of the present application. As shown in fig. 2, the phase-locked loop circuit includes: a phase frequency detector 100, a voltage controlled oscillator 200, and a frequency divider 300; the output end of the voltage-controlled oscillator 200 is connected with the feedback output end 12, the reference input end 11 and the feedback end 13 are respectively connected with the input end of the phase frequency detector 100, and the frequency divider 300 is arranged between the feedback output end 12 and the feedback end 13; the frequency divider 300 is configured to divide the output signal fvco output by the voltage-controlled oscillator 200 to obtain the feedback signal fbk, and the phase frequency detector 100 is configured to receive the reference signal fref and the feedback signal fbk. The proportional path loop 400 and the integral path loop 500 connected in parallel are arranged between the output end of the phase frequency detector 100 and the input end of the voltage-controlled oscillator 200, the integral path loop 500 is used for providing a first bias current to the voltage-controlled oscillator 200 under the action of the output signal of the phase frequency detector 100, and the proportional path loop 400 is used for providing a second bias current to the voltage-controlled oscillator 200 under the action of the output signal of the phase frequency detector 100; the voltage controlled oscillator 200 is configured to adjust the frequency of the output signal under the control of the first bias current and the second bias current to reduce the difference between the frequencies of the feedback signal fbk and the reference signal fref and/or to reduce the difference between the phases of the feedback signal fbk and the reference signal fref. The output signal of the phase frequency detector 100 includes a first pulse signal up and a second pulse signal down, which are both input into the proportional path loop 400 and the integral path loop 500; the voltage controlled oscillator is used to adjust the frequency of the output signal under the control of the first bias current and the second bias current to reduce the difference between the frequencies of the feedback signal fbk and the reference signal fref. The voltage controlled oscillator for adjusting the frequency of the output signal under control of the first bias current and the second bias current may also reduce the difference in phase of the feedback signal fbk and the reference signal fref.
It should be noted that fig. 3 is a schematic block diagram of still another phase-locked loop circuit according to an embodiment of the present application. As shown in fig. 3, in the conventional phase-locked loop structure, a loop filter needs a passive resistor with a large resistance value, which limits the reduction of in-band noise. The first capacitor c1, the second capacitor c2 and the first resistor r1 can form a low-pass filter to play a role in filtering and noise reduction, and an output signal of the charge pump is expressed as vctrl. For a conventional phase locked loop, the current of the charge pump, the voltage controlled gain, and the low pass filter resistance are all constant, and the low pass filter can be capacitive and resistive, which makes both the damping coefficient and the loop bandwidth constant. This limits the implementation of a wide operating frequency range and low input tracking jitter. Considering that the phase locked loop is by adjusting the frequency, when the frequency is disturbed, the phase error accumulates for a period proportional to WREF/WN, which refer to the angular frequency of the reference clock and the loop bandwidth, respectively. Therefore, in the pll circuit structure shown in fig. 3, the first capacitor c1, the second capacitor c2, and the first resistor r1 have limited in-band noise reduction capability, and the in-band noise of the conventional pll circuit structure is still relatively large, so that it is difficult to meet the market demand.
In view of the above problems, the phase-locked loop circuit provided in the embodiments of the present application may generate a self-bias effect by setting the proportional path loop 400 and the integral path loop 500 in parallel, and using the first bias current generated by the integral path loop 500 and the second bias current generated by the proportional path loop 400, and the self-bias may allow the circuit to select an optimal dc operating point to operate. The bias point is established substantially by the operating frequency of the phase locked loop circuit by reference to other bias voltages and currents that have been generated. The phase-locked loop circuit with self-bias can limit WN/WREF to be constant, can obtain a wider working frequency range and low input tracking jitter, and further reduces phase error. The oscillation frequency of the voltage controlled oscillator is adjusted by the bias voltage, thereby changing the phase of the feedback signal. Finally, the difference between the frequencies of the feedback signal and the reference signal is reduced through a negative feedback principle, and the frequency fvco=fref×n of the output signal of the phase-locked loop, wherein fvco and fref refer to the frequency of the voltage-controlled oscillator and the frequency of the reference signal respectively, and N refers to the frequency division ratio of the frequency divider. According to the phase-locked loop circuit provided by the embodiment of the application, the frequency of the output signal of the voltage-controlled oscillator 200 is regulated by utilizing the control of the first bias current and the second bias current, so that the difference between the frequency of the feedback signal fbk and the frequency of the reference signal fref is reduced, the difference between the phase of the feedback signal fbk and the phase of the reference signal fref is reduced, the stability of the phase-locked loop circuit can be ensured, in-band noise can be greatly reduced or eliminated, and then the clock jitter of the phase-locked loop circuit is reduced.
In some embodiments, the voltage controlled oscillator 200 is configured to adjust the frequency of the output signal under the control of the first bias current and the second bias current so that the feedback signal fbk coincides with the frequency of the reference signal fref, and may also coincide the phase of the feedback signal fbk with the reference signal fref. In the case that the frequency of the feedback signal fbk is consistent with the frequency of the reference signal fref, or in the case that the phase of the feedback signal fbk is consistent with the frequency of the reference signal fref, the in-band noise of the phase-locked loop circuit can be reduced, the working frequency range can be increased, the clock jitter can be reduced, and the stability of the phase-locked loop circuit can be further improved.
It should be noted that fig. 4 is a schematic block diagram of still another phase-locked loop circuit according to an embodiment of the present application. As shown in fig. 4, the integrating path loop includes a first charge pump, a first capacitor c1 and a bias circuit, and the proportional path loop includes a second charge pump, so as to solve the problem that the phase-locked loop is affected by the process, the voltage and the temperature. The phase frequency detector converts the phase difference between the input reference signal and the feedback clock into a voltage pulse, thereby controlling the conduction of the charge pump. The first capacitor c1 converts the first charge pump output current into a control voltage vctrl for generating bias currents and bias voltages vbp and vbn. The second charge pump is used for generating a left half plane zero point by using an active resistor of a Metal-Oxide-Semiconductor Field-Effect Transistor (Metal Oxide semiconductor field effect transistor) to ensure the stability of a loop. The oscillation frequency of the voltage-controlled oscillator is adjusted by the bias voltage vbp, thereby changing the phase of the feedback clock. Finally, the frequency consistency of the feedback clock and the reference clock is ensured through the negative feedback principle. The key to self-biasing is to allow the circuit to select the best dc operating point to operate. The bias point is established substantially by the PLL operating frequency by reference to other bias voltages and currents that have been generated. For a conventional PLL, the charge pump current, voltage controlled gain and low pass filter resistance are all constant, which makes both the damping coefficient and loop bandwidth constant. This limits the implementation of a wide operating frequency range and low input tracking jitter. Considering that the PLL is by adjusting the frequency, when the frequency is disturbed, the phase error accumulates for a period proportional to WREF/WN. The advantage of a self-biasing PLL is that WN/WREF is constant, a wider operating frequency range and low input tracking jitter can be obtained, thus reducing phase errors.
In some embodiments, the output of the integrating path loop and the output of the proportional path loop are both connected to the same potential point.
Fig. 5 is a schematic block diagram of a phase-locked loop circuit according to an embodiment of the present application. As shown in fig. 5, the integrating path loop 500 includes a first charge pump 510, a first charge storage, and a first current scaling circuit 521, where the first charge storage may include an integrating capacitor c3, the first charge storage is disposed between the first charge pump 510 and the first current scaling circuit 521, the first charge pump 510 is electrically connected to the phase frequency detector 100, and the first current scaling circuit 521 is electrically connected to the voltage controlled oscillator 200. The proportional path loop 400 includes a second charge pump 410 and a second current proportional circuit 420, the second charge pump 410 being electrically coupled to the phase frequency detector 100 and the second current proportional circuit 420 being electrically coupled to the voltage controlled oscillator 200. The phase-locked loop circuit further includes: a second charge storage, which may include a filter capacitor c4, is electrically connected to the first current scaling circuit 521, the second current scaling circuit 420, and the voltage controlled oscillator 200. Both the integrating capacitor c3 and the filter capacitor c4 can play a role in filtering and noise reduction. The first charge pump 510 is configured to control charging and discharging of the first charge storage according to an output signal of the phase frequency detector 100; the first bias current and the second bias current are used to control charging and discharging of the second charge storage. That is, the first charge pump 510 may be used to control the charging and discharging of the integrating capacitor c3 according to the output signal of the phase frequency detector 100; the first bias current and the second bias current are used to control the charge and discharge of the filter capacitor c4.
Referring to fig. 5, an input terminal of the first charge pump 510 is electrically connected to the phase frequency detector 100, an output terminal of the first charge pump 510, an input terminal of the first current scaling circuit 521, and one input terminal of the second current scaling circuit 420, and one end of the integrating capacitor c3 are all electrically connected to the first potential point N1, and the other end of the first charge memory is used for accessing a fixed potential, that is, the other end of the integrating capacitor c3 is used for accessing a fixed potential. The output terminal of the first current scaling circuit 521, the output terminal of the second current scaling circuit 420 and the input terminal of the voltage-controlled oscillator 200 are all electrically connected to the second potential point N2, one end of the second charge storage is electrically connected to the second potential point, and the other end of the second charge storage is grounded, i.e. one end of the filter capacitor c4 is electrically connected to the second potential point N2, and the other end is grounded. The second charge storage can be used for noise reduction and filtering of the phase-locked loop circuit in the process of charging and discharging, and particularly can be used for filtering and noise reduction of signals flowing to the second potential point N2. The proportional path loop may form a proportional path of the signal and the integral path loop may form an integral path of the signal, as shown in dashed lines in fig. 5.
Referring to fig. 5, the phase-locked loop circuit further includes a start-up circuit 600, where the start-up circuit 600 controls the charge and discharge of the integrating capacitor c3 under the control of the enable signal en, and specifically may be implemented by controlling the potential of the first potential point N1 by the start-up circuit 600. One end of the start-up circuit 600 is electrically connected to the first potential point N1, and the other end is used for accessing the enable signal en. The start-up circuit 600 is configured to quickly pull down the potential of the first potential point N1 from a high level to a threshold voltage under the control of the enable signal en to quickly start up the phase-locked loop circuit.
In some embodiments, the circuit coefficients of the first current scaling circuit 521 are greater than the circuit coefficients of the second current scaling circuit 420. Referring to fig. 5, the output signal of the phase frequency detector 100 includes a first pulse signal up and a second pulse signal down; in case that the frequency of the reference signal fref is greater than the frequency of the feedback signal fbk, the pulse width of the first pulse signal up is greater than the pulse width of the second pulse signal down; in case the frequency of the reference signal fref is smaller than the frequency of the feedback signal fbk, the pulse width of the first pulse signal up is smaller than the pulse width of the second pulse signal down.
In some embodiments, the capacitance value of the first charge storage is greater than the capacitance value of the second charge storage, i.e., the capacitance value of the integrating capacitor c3 is greater than the capacitance value of the filter capacitor c 4.
In the pll circuit provided in the embodiment of the present application, the phase frequency detector 100 detects a phase difference between the input reference signal fref and the feedback signal fbk, and outputs a first pulse signal up and a second pulse signal down to the first charge pump 510 and the second charge pump 410, respectively; the first charge pump 510 outputs a current pulse signal to charge and discharge the integrating capacitor c3, so that the integrating capacitor c3 is converted into a control voltage vctrl, and bias currents are respectively generated by the first current proportional circuit 521 and the second current proportional circuit 420; the sum of the output currents of the first current proportion circuit 521 and the second current proportion circuit 420 is input to the filter capacitor c4 and the voltage-controlled oscillator 200, so that the frequency of the output signal of the voltage-controlled oscillator 200 is adjusted, the frequency divider 300 divides the output signal of the voltage-controlled oscillator 200 by N, and the divided feedback signal fbk is used as the input signal of the phase frequency detector 100; the start-up circuit 600 rapidly pulls down the control voltage vctrl from a high level to a suitable voltage value when en is high, ensuring a normal rapid start-up of the phase locked loop. From the open loop transfer function formula, the self-biased PLL has two poles at the dc operating point, a left half plane zero, and a high frequency pole, and the pole zero position needs to be set reasonably to ensure the stability of the system.
Fig. 6 is a schematic diagram of a load-symmetric differential delay buffer stage according to an embodiment of the present application. As shown in fig. 6, the conventional self-biased phase-locked loop is implemented as a voltage-controlled oscillator based on the load-symmetric differential delay buffer stage shown in fig. 6, which limits the application of the self-biased phase-locked loop in a single-ended inverter chain voltage-controlled oscillator. V in differential delay buffer stage circuit as load symmetry for voltage controlled oscillator 200 I+ And V I- Are all input terminals and are 180 DEG out of phase with V O+ And V O- Are output terminals and are 180 degrees out of phase. V (V) BP Can be used for receiving vbp, V BN May be used to receive vbn.
Fig. 7 is a schematic block diagram of a single-ended inverter chain according to an embodiment of the present application. The single-ended inverter chain is superior to a voltage-controlled oscillator realized by a differential delay buffer stage in aspects of area, power consumption, control voltage generation mode, phase noise and the like, and can be widely applied to a ring oscillator structure. A single-ended inverter chain may be used as the voltage-controlled oscillator 200, the current source shown in fig. 7 has a current I D Three groups of loops which are connected in series by two transistors are led out from the middle and then are connected end to form a loop, and any two groups of loop connection points can be led out as input and output of the voltage-controlled oscillator 200. Referring to fig. 7, the voltage controlled oscillator includes a single-ended inverter chain voltage controlled oscillator including three or more odd number of inverters electrically connected end to end in sequence.
It should be noted that, the conventional self-biased phase-locked loop needs to use a relatively complex bias generating circuit for generating the bias voltages vbp and vbn. The phase-locked loop circuit provided by the embodiment of the application does not need to be provided with a bias generating circuit, and utilizes the bias current and the bias voltage generated by the proportional path loop 400 and the integral path loop 500 to generate a bias effect, so as to realize the adjustment of the frequency and the phase of the output signal of the voltage-controlled oscillator 200.
It should be noted that, regarding the advantages and disadvantages of the load symmetric delay buffer stage voltage controlled oscillator and the single-ended inverter chain voltage controlled oscillator, the actual performance comparison is performed in terms of area, power consumption and phase noise, and the results are shown in table 1, where table 1 is the parameters of the load symmetric delay buffer stage voltage controlled oscillator and the single-ended inverter chain voltage controlled oscillator.
TABLE 1
In some embodiments, first current scaling circuit 521 and second current scaling circuit 420 each include a plurality of parallel current branches, each current branch including a current source and a switch.
Fig. 8 is a schematic diagram of a current proportional circuit according to an embodiment of the present application. As shown in fig. 8, the first current scaling circuit 521 and the second current scaling circuit 420 each include a plurality of parallel current branches, each including a current source and a switch, and the second current scaling circuit 420 is connected to the second charge pump 410. Based on the single-ended inverter chain voltage-controlled oscillator structure of fig. 7, a new self-biased phase-locked loop architecture is proposed, and in conjunction with fig. 7 and fig. 4, the self-biased phase-locked loop provided in the embodiments of the present application includes a phase frequency detector 100, a first charge pump 510, a second charge pump 410, an integrating capacitor c3, a first current proportional circuit 521, a second current proportional circuit 420, a voltage-controlled oscillator 200, a frequency divider 300, a start-up circuit 600, and so on. In practical designs, the number of current sources of the first current scaling circuit 521 and the second current scaling circuit 420 may be determined by considering the oscillation frequency, the loop stability and the pll performance. Wherein vsupply acts as the power supply for the voltage controlled oscillator.
Fig. 9 is a schematic diagram of a phase noise spectrum of a phase-locked loop circuit according to an embodiment of the present application. As shown in fig. 9, the abscissa is frequency fbenchmark, the unit is Hz, the ordinate is Phase Noise, the unit is dBc/Hz, and dBc is the logarithm of the ratio of the carrier-to-frequency point output highway to the carrier frequency output power. The overall phase noise is Total, the phase noise of the voltage-controlled oscillator is vco, the phase noise of the phase frequency detector 100, the charge pump and the capacitor is pcl, the reference phase noise is ref, and the phase noise spectrum of the phase-locked loop can keep a very low value due to the fact that no passive resistor is adopted and the random jitter obtained by integrating the phase noise of the loop.
The phase-locked loop circuit provided by the embodiment of the application adopts an integral path and a proportional path, so that the loop stability is ensured; the loop filter does not need to adopt passive resistors, so that the area is reduced; meanwhile, in-band noise caused by the passive resistor is eliminated, so that clock jitter of the phase-locked loop is reduced. In addition, the bias generating circuit is not needed, and the bias current can be directly generated by the control voltage vctrl; by adjusting the current proportion of the first current proportion circuit and the second current proportion circuit, the damping coefficient and the ratio of bandwidth to reference frequency of the phase-locked loop can be flexibly controlled, so that a wider working frequency range and low input tracking jitter are obtained. Compared with the traditional self-bias phase-locked loop which controls voltage through a double loop, the proposal adopts the proportional current to control the voltage-controlled oscillator, thereby simplifying the design of the bias circuit. The left half plane zero point is generated by the integrating path and the proportional path for loop frequency compensation, so that the use of passive resistors is avoided, and in-band thermal noise is reduced.
In a second aspect of the embodiments of the present application, a chip is provided, and fig. 10 is a schematic structural block diagram of a chip provided in the embodiments of the present application. As shown in fig. 10, the chip 2000 includes: the phase-locked loop circuit 1000 as described in the first aspect.
According to the chip provided by the embodiment of the application, the proportional path loop and the integral path loop which are connected in parallel are arranged in the phase-locked loop circuit, and the self-bias effect can be generated by utilizing the first bias current generated by the integral path loop and the second bias current generated by the proportional path loop. A phase locked loop circuit with self-bias can achieve a wider operating frequency range and low input tracking jitter, thereby reducing phase errors. The oscillation frequency of the voltage controlled oscillator is adjusted by the bias current, thereby changing the phase of the feedback signal. Finally, the difference between the frequencies of the feedback signal and the reference signal is reduced by the negative feedback principle. According to the phase-locked loop circuit, the frequency of the output signal of the voltage-controlled oscillator is regulated by utilizing the control of the first bias current and the second bias current, so that the difference between the frequency of the feedback signal and the frequency of the reference signal is reduced, the difference between the phase of the feedback signal and the phase of the reference signal is reduced, the stability of the phase-locked loop circuit can be ensured, in-band noise can be greatly reduced or eliminated, and then the clock jitter of the phase-locked loop circuit is reduced.
In a third aspect of the embodiments of the present application, a module apparatus is provided, and fig. 11 is a schematic structural block diagram of the module apparatus provided in the embodiments of the present application. As shown in fig. 11, the module apparatus 3000 includes: a communication module 710 for performing internal communication of the module device or for performing communication between the module device and an external device; a power module 720 for providing power to the module device; a storage module 730 for storing data and instructions; the chip 2000 as described in the second aspect.
According to the module device provided by the embodiment of the application, the proportional path loop and the integral path loop which are connected in parallel are arranged in the phase-locked loop circuit of the chip, and the self-bias effect can be generated by utilizing the first bias current generated by the proportional path loop and the second bias current generated by the integral path loop. A phase locked loop circuit with self-bias can achieve a wider operating frequency range and low input tracking jitter, thereby reducing phase errors. The oscillation frequency of the voltage controlled oscillator is adjusted by the bias current, thereby changing the phase of the feedback signal. Finally, the difference between the frequencies of the feedback signal and the reference signal is reduced by the negative feedback principle. According to the phase-locked loop circuit, the frequency of the output signal of the voltage-controlled oscillator is regulated by utilizing the control of the first bias current and the second bias current, so that the difference between the frequency of the feedback signal and the frequency of the reference signal is reduced, the difference between the phase of the feedback signal and the phase of the reference signal is reduced, the stability of the phase-locked loop circuit can be ensured, in-band noise can be greatly reduced or eliminated, and then the clock jitter of the phase-locked loop circuit is reduced.
In a fourth aspect of the embodiments of the present application, an electronic device is provided, and fig. 12 is a schematic block diagram of a structure of an electronic device provided in the embodiments of the present application. As shown in fig. 12, the electronic device includes: the chip 2000 as described in the second aspect.
Fig. 13 is a schematic block diagram of another electronic device according to an embodiment of the present application. As shown in fig. 13, the electronic device includes: the module apparatus 3000 according to the third aspect.
According to the electronic device provided by the embodiment of the application, the proportional path loop and the integral path loop which are connected in parallel are arranged in the phase-locked loop circuit, and the self-bias effect can be generated by utilizing the first bias current generated by the integral path loop and the second bias current generated by the proportional path loop. A phase locked loop circuit with self-bias can achieve a wider operating frequency range and low input tracking jitter, thereby reducing phase errors. The oscillation frequency of the voltage controlled oscillator is adjusted by the bias current, thereby changing the phase of the feedback signal. Finally, the difference between the frequencies of the feedback signal and the reference signal is reduced by the negative feedback principle. According to the phase-locked loop circuit, the frequency of the output signal of the voltage-controlled oscillator is regulated by utilizing the control of the first bias current and the second bias current, so that the difference between the frequency of the feedback signal and the frequency of the reference signal is reduced, the difference between the phase of the feedback signal and the phase of the reference signal is reduced, the stability of the phase-locked loop circuit can be ensured, in-band noise can be greatly reduced or eliminated, and then the clock jitter of the phase-locked loop circuit is reduced.
In the foregoing embodiments, the descriptions of the embodiments are focused on, and for those portions of one embodiment that are not described in detail, reference may be made to the related descriptions of other embodiments.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-readable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions in accordance with embodiments of the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). Computer readable storage media can be any available media that can be stored by a computer or data storage devices such as servers, data centers, etc. that contain an integration of one or more available media. Usable media may be magnetic media (e.g., floppy disks, hard disks, magnetic tapes), optical media (e.g., DVDs), or semiconductor media (e.g., solid State Disks (SSDs)), among others.
It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.
In the several embodiments provided in this application, it should be understood that the disclosed apparatus, device, and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of elements is merely a logical functional division, and there may be additional divisions of actual implementation, e.g., multiple elements or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
The above embodiments are only for illustrating the technical solution of the present application, and are not limiting thereof; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the corresponding technical solutions.
While preferred embodiments of the present description have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the disclosure.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present specification without departing from the spirit or scope of the specification. Thus, if such modifications and variations of the present specification fall within the scope of the claims and the equivalents thereof, the present specification is also intended to include such modifications and variations.
Claims (14)
1. A phase locked loop circuit comprising:
the feedback unit comprises a reference input end, a feedback output end and a feedback end, wherein the reference input end is used for providing a reference signal, the feedback output end is used for outputting an output signal, and the feedback end is used for providing a feedback signal;
a proportional path loop and an integral path loop which are connected in parallel are arranged between the reference input end and the feedback output end, the integral path loop is used for providing a first bias current to the feedback output end under the driving of the reference signal and the feedback signal, and the proportional path loop is used for providing a second bias current to the feedback output end under the driving of the reference signal and the feedback signal;
the feedback unit is used for adjusting the frequency of the output signal output by the feedback output end under the control of the first bias current and the second bias current so as to reduce the difference between the frequency of the feedback signal and the frequency of the reference signal and/or reduce the difference between the phases of the feedback signal and the reference signal.
2. The phase locked loop circuit of claim 1, wherein the feedback unit comprises: the device comprises a phase frequency detector, a voltage-controlled oscillator and a frequency divider, wherein the output end of the voltage-controlled oscillator is connected with the feedback output end, the reference input end and the feedback end are respectively connected with the input end of the phase frequency detector, and the frequency divider is arranged between the feedback output end and the feedback end;
The frequency divider is used for dividing the output signal output by the voltage-controlled oscillator to obtain the feedback signal, and the phase frequency detector is used for receiving the reference signal and the feedback signal;
the proportional path loop and the integral path loop which are connected in parallel are arranged between the output end of the phase frequency detector and the input end of the voltage-controlled oscillator, the integral path loop is used for providing the first bias current for the voltage-controlled oscillator under the action of the output signal of the phase frequency detector, and the proportional path loop is used for providing the second bias current for the voltage-controlled oscillator under the action of the output signal of the phase frequency detector;
the voltage controlled oscillator is configured to adjust a frequency of an output signal under control of the first bias current and the second bias current to reduce a difference between frequencies of the feedback signal and the reference signal and/or to reduce a difference between phases of the feedback signal and the reference signal.
3. The phase-locked loop circuit of claim 2, wherein,
the voltage controlled oscillator is used for adjusting the frequency of the output signal under the control of the first bias current and the second bias current so as to enable the feedback signal to be consistent with the frequency of the reference signal and/or enable the feedback signal to be consistent with the phase of the reference signal.
4. The phase-locked loop circuit of claim 2, wherein,
the integrating path loop comprises a first charge pump, a first charge storage and a first current proportion circuit, wherein the first charge storage is arranged between the first charge pump and the first current proportion circuit, the first charge pump is electrically connected with the phase frequency detector, and the first current proportion circuit is electrically connected with the voltage-controlled oscillator;
the proportional path loop comprises a second charge pump and a second current proportional circuit, wherein the second charge pump is electrically connected with the phase frequency detector, and the second current proportional circuit is electrically connected with the voltage-controlled oscillator.
5. The phase-locked loop circuit of claim 4, further comprising:
a second charge storage electrically connected to the first current scaling circuit, the second current scaling circuit, and the voltage controlled oscillator;
the first charge pump is used for controlling the charge and discharge of the first charge storage according to the output signal of the phase frequency detector;
the first bias current and the second bias current are used for controlling charging and discharging of the second charge storage, and the second charge storage is used for noise reduction filtering of the phase-locked loop circuit in the charging and discharging process.
6. The phase-locked loop circuit of claim 5, wherein,
the input end of the first charge pump is electrically connected with the phase frequency detector, the output end of the first charge pump, the input end of the first current proportional circuit and one input end of the second current proportional circuit are all electrically connected with a first potential point, one end of the first charge storage is electrically connected with the first potential point, and the other end of the first charge storage is used for being connected with a fixed potential;
the output end of the first current proportion circuit, the output end of the second current proportion circuit and the input end of the voltage-controlled oscillator are all electrically connected to a second potential point, one end of the second charge storage is electrically connected with the second potential point, and the other end of the second charge storage is grounded.
7. The phase-locked loop circuit of claim 6, further comprising:
a starting circuit, one end of which is electrically connected with the first potential point, and the other end of which is used for accessing an enabling signal;
the starting circuit is used for controlling the charge and discharge of the first charge storage under the control of the enabling signal, and the starting circuit is used for rapidly pulling the potential of the first potential point from a high level to a threshold voltage under the control of the enabling signal so as to rapidly start the phase-locked loop circuit.
8. The phase-locked loop circuit of claim 5, wherein,
the circuit coefficient of the first current proportion circuit is larger than that of the second current proportion circuit; and/or the number of the groups of groups,
the first charge storage and/or the second charge storage comprises a capacitor.
9. The phase-locked loop circuit of claim 8, wherein,
the output signal of the phase frequency detector comprises a first pulse signal and a second pulse signal;
in the case that the frequency of the reference signal is greater than the frequency of the feedback signal, the pulse width of the first pulse signal is greater than the pulse width of the second pulse signal;
in the case that the frequency of the reference signal is smaller than the frequency of the feedback signal, the pulse width of the first pulse signal is smaller than the pulse width of the second pulse signal.
10. The phase-locked loop circuit of claim 8, wherein,
in the case where the first charge storage and the second charge storage include capacitors, a capacitance value of the first charge storage is larger than a capacitance value of the second charge storage.
11. The phase-locked loop circuit of claim 5, wherein,
The voltage-controlled oscillator comprises a single-ended inverter chain voltage-controlled oscillator, and the single-ended inverter chain voltage-controlled oscillator comprises three or more odd inverters which are electrically connected end to end in sequence; and/or the number of the groups of groups,
the first current scaling circuit and the second current scaling circuit each comprise a plurality of parallel current branches, each current branch comprising a current source and a switch.
12. A chip, comprising:
a phase locked loop circuit as claimed in any one of claims 1 to 11.
13. A modular apparatus, comprising:
the communication module is used for carrying out internal communication of the module equipment or carrying out communication between the module equipment and external equipment;
the power supply module is used for providing electric energy for the module equipment;
the storage module is used for storing data and instructions;
the chip of claim 12.
14. An electronic device, comprising:
the chip of claim 12 and/or the modular device of claim 13.
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