CN117254791A - Clock gating implementation method and gating clock circuit - Google Patents

Clock gating implementation method and gating clock circuit Download PDF

Info

Publication number
CN117254791A
CN117254791A CN202311170914.8A CN202311170914A CN117254791A CN 117254791 A CN117254791 A CN 117254791A CN 202311170914 A CN202311170914 A CN 202311170914A CN 117254791 A CN117254791 A CN 117254791A
Authority
CN
China
Prior art keywords
clock
signal
clock signal
gating
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202311170914.8A
Other languages
Chinese (zh)
Inventor
李冰华
刘扬帆
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Guangzhou Guangdong Hong Kong Macao Greater Bay Area Frontier Innovation Technology Research Institute
Original Assignee
Guangzhou Guangdong Hong Kong Macao Greater Bay Area Frontier Innovation Technology Research Institute
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Guangzhou Guangdong Hong Kong Macao Greater Bay Area Frontier Innovation Technology Research Institute filed Critical Guangzhou Guangdong Hong Kong Macao Greater Bay Area Frontier Innovation Technology Research Institute
Priority to CN202311170914.8A priority Critical patent/CN117254791A/en
Publication of CN117254791A publication Critical patent/CN117254791A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/012—Modifications of generator to improve response time or to decrease power consumption
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Manipulation Of Pulses (AREA)

Abstract

The invention provides a clock gating implementation method and a clock gating circuit, wherein the method comprises the following steps: acquiring an output clock signal of each trigger in a current time period; exclusive OR processing is carried out on the data input signal and the output clock signal of each trigger to generate a first clock signal; acquiring a first clock signal of each trigger for carrying out or processing, and generating a second clock signal; turning over the input clock signal of the gating clock according to the level of the input enabling signal by taking the second clock signal as the input enabling signal of the gating clock, and switching the output clock signal of the gating clock; an output clock signal of the gating clock is sent to an input clock signal terminal of each flip-flop. The invention correlates the signal states of the plurality of triggers with the input enabling signals of the gating clock and sends the output clock signals of the gating clock to the clock signal end of the triggers, thereby reducing the clock turnover times and the power consumption of the chip.

Description

Clock gating implementation method and gating clock circuit
Technical Field
The present invention relates to the field of clock gating application technologies, and in particular, to a clock gating implementation method and a clock gating circuit.
Background
Most socs are severely limited by power budget and therefore it is desirable to reduce power consumption as much as possible. In computer architecture, clock gating is a common technique for optimizing chip power consumption, and is used in many synchronous circuits, where the clock signal is removed to disable the clock input signal of some of the flip-flops by not using or ignoring the clock signal in the circuit, so that the flip-flops do not switch states. When the trigger is not switched, the switching power consumption is zero, and only leakage current is generated, so that the dynamic power consumption can be reduced. The existing clock gating implementation method generally has the following two methods: the first is the introduction of a logic description of clock gating by an engineer in the RTL code as part of the function into the design of clock gating; the second is that the synthesis tool automatically inserts the gate clock through the hardware description grammar conforming to the specification of the synthesis tool, and the trigger outputs the input signal at the last moment and keeps the output value unchanged under other conditions.
However, the use of different signals in the design process of the synchronous circuit has timing alignment requirements, and due to the personal code writing habit of the engineer, it is difficult to accurately acquire the condition of the input enable signal in the second method. Furthermore, a large number of flip-flops exist in the chip as a simple beat function, and in this case, the gating clock cannot be inserted into the current flip-flop either by the first implementation method or the second implementation method, so that the input clock signal of the flip-flop can only turn over along with the global clock signal in each clock cycle, and a large amount of power consumption is generated.
Disclosure of Invention
The invention aims to provide a clock gating implementation method and a clock gating circuit, which are used for solving the technical problems, relating the signal states of a plurality of triggers to the input enabling signals of a clock gating, and sending the output clock signals of the clock gating to the clock signal end of each trigger, so that the clock turnover times are reduced, and the power consumption of a chip is reduced.
In order to solve the above technical problems, the present invention provides a clock gating implementation method, which is applied to a gated clock circuit, and includes:
acquiring an output clock signal of each trigger in a current time period;
exclusive OR processing is carried out on the data input signal and the output clock signal of each trigger to generate a first clock signal;
acquiring a first clock signal of each trigger for carrying out or processing, and generating a second clock signal;
taking the second clock signal as an input enabling signal of a gating clock;
turning over an input clock signal of the gating clock according to the level of the input enabling signal, and switching an output clock signal of the gating clock; the input clock signal is a global clock signal which is turned over every preset clock frequency;
and sending the output clock signal of the gating clock to the input clock signal end of each trigger.
In the above scheme, the data input signal and the clock output signal of each trigger are collected, exclusive-or processing results are obtained, or operation is performed, a second clock signal is generated, the second clock signal is used as an input enabling signal of the gating clock, and the input enabling signal of the gating clock is associated with the signal state of each trigger. Further, the output clock signal of the gating clock is sent to the input clock signal end of each trigger, based on the fact that the clock input signal of each trigger is not a clock signal which can be turned over every time period, but a clock signal modulated according to the input enabling signal of the gating clock, from the aspect of time length, a plurality of clock signals which are turned over by a plurality of triggers in one time period can be reduced to one clock signal which is turned over in one time period and a plurality of controlled clocks, so that the clock turning times of the triggers are reduced, and the power consumption of a chip is further reduced.
In one implementation manner, the obtaining the output clock signal of each flip-flop in the current time period specifically includes:
acquiring a data input signal of each trigger in a last time period;
and acquiring an output clock signal of each trigger in the current time period based on the data input signal of each trigger in the last time period.
In one implementation manner, the exclusive-or processing is performed on the data input signal and the output clock signal of each flip-flop, so as to generate a first clock signal, and the first clock signal of each flip-flop is obtained for performing or processing, so as to obtain a second clock signal, which specifically includes:
respectively inputting a data input signal and an output clock signal of each trigger into an exclusive-OR gate to perform exclusive-OR processing, and generating a first clock signal;
and collecting a first clock signal of each trigger, inputting each first clock signal into an OR gate for carrying out or processing, and generating a second clock signal.
In one implementation manner, the switching the output clock signal of the gating clock according to the level of the input enable signal to flip the input clock signal of the gating clock specifically includes:
when the input enabling signal is in a high level, turning over based on an input clock signal of the gating clock, and switching an output clock signal of the gating clock into the turned-over input clock signal;
when the input enabling signal is at a low level, switching an output clock signal of the gating clock to a fixed level signal; wherein the fixed level signal is any one of a 0 level and a 1 level.
In one implementation, after sending the output clock signal of the gating clock to the input clock signal end of each flip-flop, the method further includes:
and switching the output clock signal of each trigger according to the signal received by each trigger at the input clock signal end.
In a second aspect, the present application further provides a gating clock circuit including at least two flip-flops and a gating clock including:
each trigger is connected with an exclusive-OR gate respectively; the data input end of each trigger is connected with the first input end of the exclusive-OR gate, and the signal output end of each trigger is connected with the second input end of the exclusive-OR gate;
the output end of each exclusive-OR gate is connected with the input end of one AND gate;
the output end of the AND gate is connected with the input enabling end of the gating clock;
and the signal output end of the gating clock is connected with the clock signal end of each trigger.
In the scheme, under the condition that the functions of the multi-trigger circuit are not changed, the input enabling end of the gating clock is associated with the state of the signal output end of each trigger through the exclusive OR gate and the AND gate, and the signal output end of the gating clock is connected with the clock signal end of each trigger, so that the output clock of one gating clock is used for replacing the input clock signals of a plurality of triggers, and the overall clock power consumption is reduced. The structure is simple and easy to realize, and can be widely applied to various digital chips such as general processors, digital signal processors, special processors and the like.
In one implementation, the flip-flop is a D flip-flop and the clock signal of the gating clock is accessed to a global clock signal.
In a third aspect, the present application also provides a terminal device comprising a processor, a memory and a computer program stored in the memory and configured to be executed by the processor, the processor implementing the clock gating implementation method as above when executing the computer program.
In a fourth aspect, the present application further provides a computer readable storage medium, where the computer readable storage medium includes a stored computer program, where the computer program when executed controls a device in which the computer readable storage medium is located to perform the clock gating implementation method as described above.
Drawings
FIG. 1 is a flow chart of a clock gating implementation method according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a connection relationship of a gating clock circuit according to an embodiment of the invention.
Detailed Description
The following describes in further detail the embodiments of the present invention with reference to the drawings and examples. The following examples are illustrative of the invention and are not intended to limit the scope of the invention.
The terms first and second and the like in the description and in the claims and drawings of the present application are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
Example 1
Referring to fig. 1, fig. 1 is a flowchart of a clock gating implementation method according to an embodiment of the present invention. The embodiment of the invention provides a clock gating implementation method, which comprises steps 101 to 106, wherein the steps are as follows:
step 101: an output clock signal of each flip-flop at a current time period is acquired.
In the embodiment of the invention, the output clock signal of each trigger in the current time period is collected. In an embodiment, the obtaining the output clock signal of each flip-flop in the current time period specifically includes: acquiring a data input signal of each trigger in a last time period; and acquiring an output clock signal of each trigger in the current time period based on the data input signal of each trigger in the last time period. The output clock signal of the flip-flop is related to the data input clock signal of the previous time period, but the working principle of the flip-flop of different types is not the same, and the invention is not limited herein. Preferably, the embodiment of the present invention is illustrated with a D flip-flop, where the output clock signal is reset to 0 when the data input clock signal of the previous time period is at a high level, and is set to 0 when the data input clock signal of the previous time period is at a low level.
Step 102: and performing exclusive OR processing on the data input signal and the output clock signal of each trigger respectively to generate a first clock signal.
Step 103: acquiring a first clock signal of each trigger for carrying out or processing, and generating a second clock signal;
in an embodiment, the exclusive-or processing is performed on the data input signal and the output clock signal of each of the flip-flops to generate a first clock signal, and the obtaining the first clock signal of each of the flip-flops to perform or processing to obtain a second clock signal specifically includes: respectively inputting a data input signal and an output clock signal of each trigger into an exclusive-OR gate to perform exclusive-OR processing, and generating a first clock signal; and collecting a first clock signal of each trigger, inputting each first clock signal into an OR gate for carrying out or processing, and generating a second clock signal.
In the embodiment of the invention, the data input signal and the output clock signal of each trigger are input to an exclusive or gate for exclusive or processing to generate the first clock signal of each trigger, and then the first clock signal of each trigger is input to the or gate for or processing to generate the second clock signal.
Step 104: the second clock signal is used as an input enabling signal of a gating clock.
In the embodiment of the invention, the data input signal and the clock output signal of each trigger are collected, exclusive OR processing results are carried out, OR operation is carried out, a second clock signal is generated, the second clock signal is used as an input enabling signal of a gating clock, and the input enabling signal of the gating clock is associated with the signal state of each trigger.
Step 105: turning over an input clock signal of the gating clock according to the level of the input enabling signal, and switching an output clock signal of the gating clock; the input clock signal is a global clock signal which is turned over every preset clock frequency;
in an embodiment, the switching the output clock signal of the gating clock according to the level of the input enable signal turns over the input clock signal of the gating clock, specifically includes: when the input enabling signal is in a high level, turning over based on an input clock signal of the gating clock, and switching an output clock signal of the gating clock into the turned-over input clock signal; when the input enabling signal is at a low level, switching an output clock signal of the gating clock to a fixed level signal; wherein the fixed level signal is any one of a 0 level and a 1 level.
The output clock signal in the gate clock is determined by the input enable signal and the input clock signal. When the input enable signal is at a high level, the inverted input clock signal is output at the clock edge at the next time. If the input enable signal is at a low level, the output clock signal is fixed to be 0 or 1, and the output clock signal at the moment does not flip every other clock cycle along with the global clock signal of the input end.
Step 106: and sending the output clock signal of the gating clock to the input clock signal end of each trigger.
In one embodiment, after sending the output clock signal of the gating clock to the input clock signal end of each flip-flop, the method further includes: and switching the output clock signal of each trigger according to the signal received by each trigger at the input clock signal end. According to the embodiment of the invention, the output clock signal of the gating clock is sent to the input clock signal end of each trigger, and based on the output clock signal, the clock input signal of each trigger is not a clock signal which can be turned over every time period, but a clock signal modulated according to the input enabling signal of the gating clock, and from the time length, a plurality of clock signals turned over by a plurality of triggers in one time period can be reduced to one clock signal turned over in one time period and a plurality of controlled clocks, so that the clock turning times of the triggers are reduced, and the power consumption of a chip is further reduced.
In an embodiment of the present invention, a clock gating implementation apparatus is provided, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, where the processor implements the data collection method based on the scanning apparatus when executing the computer program.
In an embodiment of the present invention, a computer readable storage medium is further provided, where the computer readable storage medium includes a stored computer program, and when the computer program runs, a device where the computer readable storage medium is located is controlled to perform the data collection based on the scanning device. For example, a computer program may be split into one or more modules, one or more modules stored in memory and executed by a processor to perform the present invention. One or more of the modules may be a series of computer program instruction segments capable of performing particular functions to describe the execution of a computer program in a clock gating implementation.
The clock gating implementation device can be a computing device such as a desktop computer, a notebook computer, a palm computer, a cloud server and the like. Clock gating implementation devices may include, but are not limited to, processors, memory, displays. Those skilled in the art will appreciate that the above components are merely examples of clock gating implementation devices and do not constitute a limitation of clock gating implementation devices, and may include more or fewer components than components, or may combine certain components, or different components, e.g., a clock gating implementation device may also include input and output devices, network access devices, buses, etc.
The processor may be a central processing unit (Central Processing Unit, CPU), other general purpose processors, digital signal processors (Digital Signal Processor, DSP), application specific integrated circuits (Application Specific Integrated Circuit, ASIC), off-the-shelf programmable gate arrays (Field-Programmable Gate Array, FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like, the processor being a control center of the clock gating implementation, the various interfaces and lines being used to connect the various parts of the overall clock gating implementation.
The memory may be used to store computer programs and/or modules, and the processor implements the various functions of the device by running or executing the computer programs and/or modules stored in the memory, and invoking data stored in the memory. The memory may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program (such as a sound playing function, a text conversion function, etc.) required for at least one function, and the like; the storage data area may store data (such as audio data, text message data, etc.) created according to the use of the cellular phone, etc. In addition, the memory may include high-speed random access memory, and may also include non-volatile memory, such as a hard disk, memory, plug-in hard disk, smart Media Card (SMC), secure Digital (SD) Card, flash Card (Flash Card), at least one disk storage device, flash memory device, or other volatile solid-state storage device.
Wherein the modules of the clock gating implementation device integration, if implemented in the form of software functional units and sold or used as separate products, may be stored in a computer readable storage medium. Based on such understanding, the present invention may implement all or part of the flow of the method of the above embodiment, or may be implemented by a computer program to instruct related hardware, and the computer program may be stored in a computer readable storage medium, where the computer program, when executed by a processor, may implement the steps of each of the method embodiments described above. Wherein the computer program comprises computer program code, which may be in the form of source code, object code, executable files or in some intermediate form, etc. The computer readable medium may include: any entity or device capable of carrying computer program code, a recording medium, a U disk, a removable hard disk, a magnetic disk, an optical disk, a computer Memory, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), an electrical carrier signal, a telecommunications signal, a software distribution medium, and so forth. It should be noted that the content of the computer readable medium can be appropriately increased or decreased according to the requirements of the jurisdiction's jurisdiction and the patent practice, for example, in some jurisdictions, the computer readable medium does not include electrical carrier signals and telecommunication signals according to the jurisdiction and the patent practice. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
The embodiment of the invention provides a clock gating implementation method, which is used for collecting the data input signal and the clock output signal of each trigger, carrying out exclusive OR processing result and OR operation, generating a second clock signal, taking the second clock signal as the input enabling signal of a gating clock, and associating the input enabling signal of the gating clock with the signal state of each trigger. Further, the output clock signal of the gating clock is sent to the input clock signal end of each trigger, based on the fact that the clock input signal of each trigger is not a clock signal which can be turned over every time period, but a clock signal modulated according to the input enabling signal of the gating clock, from the aspect of time length, a plurality of clock signals which are turned over by a plurality of triggers in one time period can be reduced to one clock signal which is turned over in one time period and a plurality of controlled clocks, so that the clock turning times of the triggers are reduced, and the power consumption of a chip is further reduced.
Example 2
The embodiment of the invention provides a gating clock circuit, which comprises at least two triggers and a gating clock, and comprises: each trigger is connected with an exclusive-OR gate respectively; the data input end of each trigger is connected with the first input end of the exclusive-OR gate, and the signal output end of each trigger is connected with the second input end of the exclusive-OR gate; the output end of each exclusive-OR gate is connected with the input end of one AND gate; the output end of the AND gate is connected with the input enabling end of the gating clock; and the signal output end of the gating clock is connected with the clock signal end of each trigger. In an embodiment, the flip-flop is a D flip-flop, hereinafter referred to as DFF. The clock signal of the gating clock is accessed to a global clock signal.
Referring to fig. 2, fig. 2 is a schematic diagram illustrating a connection relationship of a gating clock circuit according to an embodiment of the invention. The embodiment of the invention is exemplified by a gating clock circuit comprising four flip-flops and one gating clock circuit. It should be noted that, the number of the flip-flops connected in the gating clock circuit depends on the time sequence interval of the data input signals of the flip-flops, preferably, the number of the flip-flops in the gating clock circuit is not more than 20, so that the time sequence deterioration of the data input signals caused by connecting a plurality of flip-flops in one gating clock is avoided, which is unfavorable for the operation of the circuit structure.
The gating clock circuit comprises a trigger D0, a trigger D1, a trigger D2, a trigger D3 and a gating clock ICGcell. Wherein the data input IN and the signal output OUT of the flip-flop are connected to an exclusive or gate XOR. The data input IN and the signal output OUT of each flip-flop are exclusive-ored by an exclusive-or gate XOR. The output of each exclusive OR gate is then connected to the input of an and gate OR-icg_en, the output of which is connected to the enable signal terminal EN of the gating clock ICG cell. The input enable signal EN of the gate clock ICG cell is derived from the data input signals IN of the 4 DFF flip-flops, and the result of the exclusive or of the output clock signal OUT signal is further added up, and the available logic expression of the input enable signal EN is expressed as follows: en= (d0_inxord0_out) | (d1_inxord1_out) | (d2_inxord2_out) | (d3_inxord3_out).
The gate clock ICG cell has an output determined according to the input enable signal EN and the input global clock signal GCLK. When the input enable signal EN is at a high level, the inverted clock signal OCLK starts to be output at the clock edge of the next time, and if the input enable signal EN is 0, the output clock signal OCLK is fixed to 0 or 1, which is equivalent to that the clock signal OCLK does not complete the inversion once according to each clock cycle. The signal output terminal of the gating clock ICG cell is connected to the clock input terminal of each flip-flop, and the clock signal OCLK is connected to the clock input terminal of each flip-flop. At this time, the clock input of the flip-flop is no longer the clock signal GCLK flipped over at the time, but is one clock signal LCLK modulated according to the input enable signal.
The gating clock circuit structure provided by the embodiment of the invention has the same functions as the trigger circuit structure without the gating clock circuit, and the time sequence function truth tables of the two circuit structures are analyzed for facilitating understanding. Wherein IN represents the value of the input IN port signal of the DFF at the current time; OUT represents the value of the output OUT port signal of the DFF at the current time; OUT represents the value of the output OUT port signal of the DFF at the next time; EN represents the value of the driving EN port signal of the gate clock at the current time, LCLK represents the value of the clock signal LCLK port signal of the DFF.
See table 1:
IN OUT OUT
0 0 0
0 1 0
1 0 1
1 1 1
table 1 is a timing function truth table for a flip-flop circuit configuration without a gating clock circuit.
In the trigger circuit structure without the gate clock circuit, the trigger is used for realizing the beating function, so that the output signal of the trigger at the next moment and the output signal of the trigger at the current moment have no association relation, and the output signal of the trigger at the next moment is only determined by the value of the data input signal at the last moment.
See table 2:
IN OUT EN LCLK OUT
0 0 0 clock-free edge 0
0 1 1 With clock edges 0
1 0 1 With clock edges 1
1 1 0 Clock-free edge 1
Table 2 is a truth table of the timing functions of the gated clock circuit structure.
Because the 4 DFFs in the gating clock circuit structure provided by the embodiment of the invention are exclusive-ored and then are subjected to OR operation, a single DFF is analyzed. When IN andOUTwhen the value of the input IN at the current moment is different from the value stored IN the DFF at the previous moment, the output EN signal of the exclusive OR gate is 1, the input LCLK clock signal of the DFF is inverted to generate a clock edge, and the DFF samples according to the clock edge and outputs the input IN to the OUT at the next moment; if the EN signal is 0, i.e. the value of the input IN is the same as the value stored IN the previous DFF, then LCLK does not flip, which corresponds to the DFF having no clock edge transition input, the DFF remains the original value, andOUTthe values are the same.
As can be seen from the two timing function truth tables of table 1 and table 2, IN the flip-flop circuit structure without the gate clock circuit, the OUT and IN of the flip-flop remain identical; in the gated clock circuit structure, the flip-flop OUT and the flip-flop are not clocked at allOUTKeeping consistent, the OUT and IN of the flip-flop stay consistent when the clock edge is generated. However, the output OUT of the flip-flop is relative to all input cases, whether there is no gated clock structureIN、OUTThe value behavior of (2) is consistent. The introduction of the gating clock structure in the multi-flip-flop circuit does not change the circuit function of the original circuit.
As an optimization scheme of the embodiment of the invention, when the circuit structure is applied to actual items such as chips, DD without gating clock control can be grouped. Grouping according to the redundancy degree of the IN-end time sequence interval contained IN the comprehensive tool, grouping the DFFs with consistent time sequence intervals after the DFFs are IN a group, and adopting the structure of the gating clock circuit provided by the embodiment of the invention. Based on the grouping basis, the circuit can be ensured not to cause the time sequence to be unable to converge due to the introduction of additional logic at the IN end. Meanwhile, when the number of DFFs after grouping is small, the effect of little benefit may be generated, which is equivalent to the benefit that DFFs with small timing intervals drag DFFs with large timing intervals. The grouping basis can also select to divide the flip probability and the flip time into one group according to the chip world function requirement, and can ensure that the probability of EN signal 1 generated after the DFFs in the same group pass through logic is consistent with the probability of exclusive OR 1 of the data input end and the signal output end of the DFF, so that the probability of EN signal 1 generated by a plurality of DFFs or signals can be kept low, and the probability of LCLK flip is low.
The embodiment of the invention provides a gating clock circuit, which is characterized in that under the condition of not changing the functions of a multi-trigger circuit, an input enabling end of a gating clock is associated with the state of a signal output end of each trigger through an exclusive OR gate and an AND gate, and the signal output end of the gating clock is connected with a clock signal end of each trigger, so that the output clock of one gating clock is adopted to replace the input clock signals of a plurality of triggers, and the overall clock power consumption is reduced. The structure is simple and easy to realize, and can be widely applied to various digital chips such as general processors, digital signal processors, special processors and the like.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that modifications and substitutions can be made by those skilled in the art without departing from the technical principles of the present invention, and these modifications and substitutions should also be considered as being within the scope of the present invention.

Claims (9)

1. A clock gating implementation method, applied to a gated clock circuit, comprising:
acquiring an output clock signal of each trigger in a current time period;
exclusive OR processing is carried out on the data input signal and the output clock signal of each trigger to generate a first clock signal;
acquiring a first clock signal of each trigger for carrying out or processing, and generating a second clock signal;
taking the second clock signal as an input enabling signal of a gating clock;
turning over an input clock signal of the gating clock according to the level of the input enabling signal, and switching an output clock signal of the gating clock; the input clock signal is a global clock signal which is turned over every preset clock frequency;
and sending the output clock signal of the gating clock to the input clock signal end of each trigger.
2. The method for implementing clock gating according to claim 1, wherein the obtaining the output clock signal of each flip-flop in the current time period is specifically:
acquiring a data input signal of each trigger in a last time period;
and acquiring an output clock signal of each trigger in the current time period based on the data input signal of each trigger in the last time period.
3. The method for implementing clock gating according to claim 1, wherein the performing exclusive-or processing on the data input signal and the output clock signal of each flip-flop respectively generates a first clock signal, and obtaining the first clock signal of each flip-flop for performing or processing to obtain a second clock signal specifically includes:
respectively inputting a data input signal and an output clock signal of each trigger into an exclusive-OR gate to perform exclusive-OR processing, and generating a first clock signal;
and collecting a first clock signal of each trigger, inputting each first clock signal into an OR gate for carrying out or processing, and generating a second clock signal.
4. The clock gating implementation method according to claim 1, wherein the switching the output clock signal of the gating clock by flipping the input clock signal of the gating clock according to the level of the input enable signal specifically includes:
when the input enabling signal is in a high level, turning over based on an input clock signal of the gating clock, and switching an output clock signal of the gating clock into the turned-over input clock signal;
when the input enabling signal is at a low level, switching an output clock signal of the gating clock to a fixed level signal; wherein the fixed level signal is any one of a 0 level and a 1 level.
5. The method according to claim 1, further comprising, after sending the output clock signal of the gate clock to the input clock signal end of each flip-flop:
and switching the output clock signal of each trigger according to the signal received by each trigger at the input clock signal end.
6. A gated clock circuit comprising at least two flip-flops and a gated clock, comprising:
each trigger is connected with an exclusive-OR gate respectively; the data input end of each trigger is connected with the first input end of the exclusive-OR gate, and the signal output end of each trigger is connected with the second input end of the exclusive-OR gate;
the output end of each exclusive-OR gate is connected with the input end of one AND gate;
the output end of the AND gate is connected with the input enabling end of the gating clock;
and the signal output end of the gating clock is connected with the clock signal end of each trigger.
7. The gated clock circuit of claim 6 wherein the flip-flop is a D flip-flop and the clock signal of the gated clock is coupled to a global clock signal.
8. A terminal device comprising a processor, a memory and a computer program stored in the memory and configured to be executed by the processor, the processor implementing the clock gating implementation method according to any one of claims 1 to 5 when executing the computer program.
9. A computer readable storage medium, characterized in that the computer readable storage medium comprises a stored computer program, wherein the computer program when run controls a device in which the computer readable storage medium is located to perform the clock gating implementation method according to any one of claims 1 to 5.
CN202311170914.8A 2023-09-12 2023-09-12 Clock gating implementation method and gating clock circuit Pending CN117254791A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202311170914.8A CN117254791A (en) 2023-09-12 2023-09-12 Clock gating implementation method and gating clock circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202311170914.8A CN117254791A (en) 2023-09-12 2023-09-12 Clock gating implementation method and gating clock circuit

Publications (1)

Publication Number Publication Date
CN117254791A true CN117254791A (en) 2023-12-19

Family

ID=89136181

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202311170914.8A Pending CN117254791A (en) 2023-09-12 2023-09-12 Clock gating implementation method and gating clock circuit

Country Status (1)

Country Link
CN (1) CN117254791A (en)

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030006806A1 (en) * 2001-07-03 2003-01-09 Elappuparackal Tony T. Data-driven clock gating for a sequential data-capture device
CN101303711A (en) * 2008-07-10 2008-11-12 北京中星微电子有限公司 Gating clock for on-site programmable gate array and implementing method thereof
CN104769841A (en) * 2012-09-19 2015-07-08 高通股份有限公司 Clock gating circuit for reducing dynamic power
CN104852712A (en) * 2015-05-19 2015-08-19 中国电子科技集团公司第四十七研究所 Low-power-consumption gated clock circuit structure based on data variation
CN109314506A (en) * 2016-06-02 2019-02-05 高通股份有限公司 Low clock power data gated FF
CN112751560A (en) * 2019-10-30 2021-05-04 三星电子株式会社 Clock gating unit and integrated circuit
CN114417758A (en) * 2022-01-28 2022-04-29 杭州士兰微电子股份有限公司 Trigger unit for clock gating based on data comparison
US20220247411A1 (en) * 2021-02-04 2022-08-04 Nuvoton Technology Corporation Clock-gating synchronization circuit and method of clock-gating synchronization
CN116388748A (en) * 2021-12-22 2023-07-04 英特尔公司 Self-gating flip-flop for dynamic power reduction

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030006806A1 (en) * 2001-07-03 2003-01-09 Elappuparackal Tony T. Data-driven clock gating for a sequential data-capture device
CN101303711A (en) * 2008-07-10 2008-11-12 北京中星微电子有限公司 Gating clock for on-site programmable gate array and implementing method thereof
CN104769841A (en) * 2012-09-19 2015-07-08 高通股份有限公司 Clock gating circuit for reducing dynamic power
CN104852712A (en) * 2015-05-19 2015-08-19 中国电子科技集团公司第四十七研究所 Low-power-consumption gated clock circuit structure based on data variation
CN109314506A (en) * 2016-06-02 2019-02-05 高通股份有限公司 Low clock power data gated FF
CN112751560A (en) * 2019-10-30 2021-05-04 三星电子株式会社 Clock gating unit and integrated circuit
US20220247411A1 (en) * 2021-02-04 2022-08-04 Nuvoton Technology Corporation Clock-gating synchronization circuit and method of clock-gating synchronization
CN116388748A (en) * 2021-12-22 2023-07-04 英特尔公司 Self-gating flip-flop for dynamic power reduction
CN114417758A (en) * 2022-01-28 2022-04-29 杭州士兰微电子股份有限公司 Trigger unit for clock gating based on data comparison

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
刘欢等: "一种新型低功耗触发器的设计", 《沈阳化工学院学报》, vol. 21, no. 3, 30 September 2007 (2007-09-30), pages 218 - 220 *

Similar Documents

Publication Publication Date Title
JP5905243B2 (en) Integrated circuit, clock gate circuit, and method
Struharik Implementing decision trees in hardware
US20220188073A1 (en) Data-type-aware clock-gating
Pinto et al. Low-power modified shift-add multiplier design using parallel prefix adder
CN108133005B (en) Environment model simulation method based on memory database, terminal equipment and storage medium
CN113408222A (en) File generation method and device, electronic equipment and storage medium
CN111047037B (en) Data processing method, device, equipment and storage medium
CN110569038B (en) Random verification parameter design method, device, computer equipment and storage medium
CN117254791A (en) Clock gating implementation method and gating clock circuit
CN114996638A (en) Configurable fast Fourier transform circuit with sequential architecture
CN106133838A (en) A kind of expansible configurable FPGA storage organization and FPGA device
US9984187B1 (en) Switching activity estimation for a multi-clock domain for power consumption estimation
CN117271953A (en) In-memory calculation acceleration circuit and method for optimizing fast Fourier transform
CN108322542B (en) Data updating method, system, device and computer readable storage medium
Palumbo et al. Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse‐Grained Reconfigurable Architectures
Tan et al. Clock gating implementation on commercial field programmable gate array (FPGA)
CN111027196B (en) Simulation analysis task processing method and device for power equipment and storage medium
CN115543317A (en) Front-end page development method and device
CN112148470B (en) Parameter synchronization method, computer device and readable storage medium
CN209803659U (en) Clock control system in GPU server
CN113935264A (en) Low power consumption synthesis method and device thereof
Tong et al. Activity correlation-based clustering clock-gating technique for digital filters
John Alex et al. Energy efficient BEC modified carry select adder based PTMAC architecture for biomedical processors
Singh et al. IO standard based low power design of RAM and implementation on FPGA
CN105874712A (en) Skippable one-bit full adder and FPGA device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination