CN117253520A

CN117253520A - Read clock and programming clock and method for distinguishing operation of NVM chip

Info

Publication number: CN117253520A
Application number: CN202310079206.7A
Authority: CN
Inventors: 王祎磊; 薛立成; 高百通; 王晨阳
Original assignee: Beijing Starblaze Technology Co ltd
Current assignee: Beijing Starblaze Technology Co ltd
Priority date: 2023-01-18
Filing date: 2023-01-18
Publication date: 2023-12-19
Anticipated expiration: 2043-01-18
Also published as: CN117253520B

Abstract

The present application provides a method of operating an NVM chip and an interface circuit of a control unit, the method including generating DQ signals based on a first clock signal control, and applying the generated DQ signals to DQ signal lines of the control unit for coupling the NVM chip; and controlling generation of the DQS signal based on the first clock signal and applying the generated DQS signal to DQS signal lines of the control component for coupling the NVM chip; generating an RE signal based on the second clock signal control and applying the generated RE signal to an RE signal line of the control unit for coupling the NVM chip, wherein the frequency of the second clock signal is smaller than the frequency of the first clock signal.

Description

Read clock and programming clock and method for distinguishing operation of NVM chip

Technical Field

The present application relates to memory technology, and in particular, to interface circuits that distinguish between control components that operate a read clock and a program clock of an NVM chip and methods of operating an NVM chip.

Background

FIG. 1A illustrates a block diagram of a solid state storage device. The solid state storage device 102 is coupled to a host for providing storage capability for the host. The host and solid state storage device 102 may be coupled by a variety of means including, but not limited to, connecting the host to the solid state storage device 102 via, for example, SATA (Serial Advanced Technology Attachment ), SCSI (Small Computer System Interface, small computer system interface), SAS (Serial Attached SCSI ), IDE (Integrated Drive Electronics, integrated drive electronics), USB (Universal Serial Bus ), PCIE (Peripheral Component Interconnect Express, PCIE, peripheral component interconnect Express), NVMe (NVM Express), ethernet, fibre channel, wireless communications network, and the like. The host may be an information processing device capable of communicating with the storage device in the manner described above, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, or the like. The memory device 102 includes an interface 103, a control unit 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory ) 110.

NAND flash memory, phase change memory, feRAM (Ferroelectric RAM, ferroelectric memory), MRAM (Magnetic Random Access Memory, magnetoresistive memory), RRAM (Resistive Random Access Memory, resistive memory), XPoint memory, etc. are common NVM.

The interface 103 may be adapted to exchange data with a host by way of, for example, SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.

The control unit 104 is used to control data transfer among the interface 103, NVM chip 105, and DRAM 110, and also for memory management, host logical address to flash physical address mapping, erase balancing, bad block management, etc. The control component 104 can be implemented in a variety of ways, such as software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of an FPGA (Field-programmable gate array, field programmable gate array), an ASIC (Application Specific Integrated Circuit, application-specific integrated circuit), or a combination thereof. The control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands. Control unit 104 may also be coupled to DRAM 110 and may access data of DRAM 110. FTL tables and/or cached data of IO commands may be stored in the DRAM.

Fig. 1B shows a detailed block diagram of the control components of the storage device.

The host accesses the storage device in IO commands that follow the storage protocol. The control component generates one or more storage commands based on the IO commands from the host and provides the storage commands to the media interface controller. The media interface controller generates storage media access commands (e.g., program commands, read commands, erase commands) that follow the interface protocol of the NVM chip from the storage commands. The control unit also keeps track of all storage commands generated from one IO command being executed and indicates to the host the result of processing the IO command.

Referring to fig. 1B, the control means includes, for example, a host interface, a host command processing unit, a storage command processing unit, a media interface controller (or flash interface controller, flash channel controller), and a storage media management unit. The host interface acquires an IO command provided by the host and generates a storage command to be provided to the storage command processing unit. The storage commands, for example, access the same size of storage space, e.g., 4KB. The data unit of the data accessed by the corresponding one of the storage commands recorded in the NVM chip is referred to as a data frame. The physical page records one or more frames of data. For example, a physical page is 17664 bytes in size and a data frame is 4KB in size, and one physical page can store 4 data frames.

The storage medium management unit maintains a logical address to physical address translation for each storage command. For example, the storage medium management unit includes FTL tables. For a read command, the storage medium management unit outputs a physical address corresponding to a logical address accessed by the storage command, for a program command, the storage medium management unit allocates an available physical address to the storage medium management unit, and records a mapping relationship between the accessed logical address and the allocated physical address. The storage medium management unit also maintains functions required to manage the NVM chip, such as garbage collection, wear leveling, etc.

The storage command processing unit operates the medium interface controller to issue a storage medium access command to the NVM chip according to the physical address provided by the storage medium management unit. For the sake of clarity, the commands sent by the storage command processing unit to the media interface controller are referred to as media interface commands, while the commands sent by the media interface controller to the NVM chip are referred to as storage media access commands. The storage medium access command follows the interface protocol of the NVM chip.

The media interface controller couples the NVM chip through a Flash Channel (Flash Channel) and issues commands to the NVM chip in a manner conforming to an interface protocol of the NVM chip to operate the NVM chip and receive command execution results output from the NVM chip. The flash memory channel includes a plurality of signal lines defined by NVM chip interface protocols, for example, known NVM chip interface protocols include "Toggle", "ONFI", etc.; also for example, the ONFI protocol defines that the flash channel includes signal lines for CE, CLE, ALE, WE, RE, DQS and/or DQ signals.

Taking NAND flash as an example, a Logical UNit (LUN) is the smallest UNit for the NVM chip to independently execute commands and report status. The memory Target (Target) is one or more Logical Units (LUNs) of a shared Chip Enable (CE) signal within the NMV Chip package. One or more dies (Die) may be included within the NAND flash package. Typically, the logic unit corresponds to a single die. In "Open NAND Flash Interface Specification", available from https:// www.onfi.org/specifications, meanings concerning target, logical unit, LUN are provided, which are part of the prior art.

In order to conform to the signal waveform pattern defined by the NVM chip interface protocol (e.g., ONFI protocol), the set of signals transmitted between the control unit and the NVM chip via the flash memory channel includes, for example, CE, CLE, ALE, WE, RE, DQS and DQ signals. The flash memory channel transmits signals in units of cycles. The signals transmitted by the respective periods have different meanings, and the meaning of the signals transmitted by the respective periods is indicated by a period Type (Cycle Type). The Cycle types include, for example, a command Cycle (CMD Cycle), an address Cycle (ADDR Cycle), a Data input Cycle (Data In Cycle), and a Data output Cycle (Data Out Cycle), etc.

The media interface controller includes an interface circuit. The interface circuit is an interface in the control unit coupled to the NVM chip, for example for controlling the signal waveforms transmitted for each Cycle (Cycle). Since the control unit transmits Data to be written to the NVM chip during a Data input period (Data In Cycle), the NVM chip transmits read Data to the control unit during a Data output period (Data Out Cycle), and the quality of a signal transmitted on the flash memory channel during the Data input period (Data In Cycle) or the Data output period (Data Out Cycle) directly affects the write/read performance of the memory device. The interface circuit is mainly controlled by waveforms of signals transmitted by a Data input period (Data In Cycle) and a Data output period (Data Out Cycle). It should be understood that the interface circuit may also control the signal waveforms of other periods, and is not limited herein.

The interface circuit typically includes a physical layer circuit (PHY), a Drive circuit (Drive), and/or a PAD. In some cases, the division of the physical layer circuit (PHY) and the driving circuit (Drive) is ambiguous or integrated together to appear as a circuit unit of one.

PAD is a circuit structure that connects the internal signals of the integrated circuit die to the external pins of the package of the chip in which the integrated circuit is located. PAD is part of the die for signal interaction of the chip with external pins. The PAD may be divided into an input PAD, an output PAD and a bidirectional PAD. The input PAD is used to receive signals from the external pins, the output PAD is used to apply signals to the external pins, and the bidirectional PAD can be used as both an input PAD and an output PAD.

And the Drive circuit is coupled between the PHY (physical layer circuit) and the PAD and used for guaranteeing the driving capability when the integrated circuit is connected with an external circuit. The driving circuit drives the PAD to generate a signal applied to an external pin according to a signal supplied from the PHY, or receives a signal from the external pin and supplies the signal to the PHY.

PHY (physical layer circuit) converts between digital domain signals inside an integrated circuit and the physical form of signals required by external circuits. The PHY is coupled to a Drive (driving circuit), and an output of the PHY controls the Drive to Drive the PAD.

Fig. 1C shows waveforms of a Data input period (Data In Cycle) defined by the ONFI protocol.

During a Data In Cycle, 8 bits of Data (D0, D1, … …, DN) for example, are present on the DQ signal lines to be transferred to the NVM chip while the CLE signal is low, the ALE signal is low, and the DQs signal toggles while Data is present on the DQ signal lines. Thus, the resulting signal sequence of data input cycles includes setting both the CLE signal and the ALE signal low and holding them low for a specified time, the time for which the CLE signal and the ALE signal are held low being dependent on the length of data (the number of data input cycles) that the control unit is to transmit to the NVM chip. The control unit needs to generate a sequence of data input cycles (the number of data input cycles is related to the length of the data to be written) through the interface circuit for transferring the data to be written to the NVM chip. In each data input cycle, the DQS signal is set to flip and simultaneously data transferred to the NVM chip is output to the DQ signal lines. Since the DQ signal is data-on-sync with the DQS signal toggling, the number of DQS signal toggling is related to the number of data input cycles in the sequence of data input cycles to be generated. The interface circuit at least needs to control the DQ signal and the DQS signal to generate the DQS signal that toggles at least once and to present, for example, 8 bits of data on the DQ signal lines to be transferred to the NVM chip at each occurrence of a flip of the DQS signal.

Fig. 1D shows waveforms of a Data Out Cycle defined by the ONFI protocol.

During a Data Out Cycle, the NVM chip outputs DQS signals and DQ signals. In each data output cycle, the DQ signal is output, for example, 8 bits of data (e.g., D0, D1, … …, DN as shown in FIG. 1D), and the flip of the DQS signal is aligned with the edges of the DQ signal. Thus, the interface circuit samples the DQ signal line after a delay period in response to capturing a signal flip on the DQS signal line every data output period. In addition, before outputting the DQS signal and the DQ signal, the interface circuit also needs to generate the RE signal on the RE signal line coupled to the NVM chip, and after receiving the specified number of RE signal inversions, the NVM chip outputs the DQS signal on the DQS signal line and outputs the DQ signal on the DQ signal line. Therefore, for the Data Out Cycle, the interface circuit needs to control at least the DQ signal, DQS signal and RE signal.

It will be appreciated that the interface protocol may be different for NVM chips of different vendors or different specifications relative to the ONFI standard. The interface circuit divides the data input/output cycle into a plurality of phases according to the waveform of the data input/output cycle of the interface protocol required by the NVM chip to be operated, and drives the corresponding signal line in a designated state at each phase. Alternatively, for example, for different timing patterns, the data input/output cycles have different signal sequences, and the signal sequences to be controlled by the interface circuit are also different, but coincide with the signal sequences required for the corresponding timing patterns.

FIG. 2 illustrates a block diagram of the control component of the memory device in connection with the NVM chip.

To control costs, the number of flash channels that can be provided by a control unit (e.g., the control unit of fig. 1A, 1B) is limited, e.g., the control unit can provide 4 or 8 flash channels. As shown in fig. 2. To increase the storage capacity of the storage device and increase the storage density and balance the pin count of the control component chips, it is common to couple, for example, 2 or more NVM chips (or to flash channels in Logical Units (LUNs) or targets) in a single flash channel. Multiple targets (targets) coupled to the same flash channel share a bus (including, for example, a control bus and a data bus) to reduce the number of pins used to couple the NVM chip to the control component. The flash channel provides its dedicated Chip Enable (CE) signal for each Target (Target) coupled to the channel to avoid transmitting signals to more than one Target within the same flash channel at any time. Each NVM chip coupled to the same flash channel is typically of the same type so that the media interface controller can operate all NVM chips in the same manner. In addition, for an NVM chip, the flash channel coupled thereto will be connected to all targets inside the NVM chip. Thus, on one flash channel, all NVM chips coupled thereto and all targets inside all NVM chips are electrically connected to the flash channel. In operation, all targets connected to a flash channel time-division multiplex the flash channel. For example, each Target (Target) coupled to the channel is provided with its dedicated Chip Enable (CE) signal via the flash channel to select the Target occupying the flash channel (the Target marked with shading as shown in fig. 2). At this point, the selected Target can exchange electrical signals with the control unit via the flash channel, while none of the other non-selected targets (targets without shading marks as shown in fig. 2) are active (e.g., in a high-impedance state) with pins coupled to the flash channel, i.e., at this point the control unit can exchange electrical signals with the selected Target in the NVM chip via the flash channel, while the non-selected targets cannot exchange electrical signals with the control unit. Although the unselected targets cannot exchange electrical signals with the control unit at this time, the wires (wires marked with dashed lines as shown in fig. 2) connecting the unselected targets are still physically connected to the flash memory channel, so that the number of NVM chips or targets coupled to the flash memory channel is different for different storage devices, and thus the load of the flash memory channel is changed, so that the port of the flash memory channel coupled to the control unit or the port of the flash memory channel coupled to the selected Target needs to have a strong driving capability. For example, when executing a program command, an electrical signal is output to the flash memory channel by the control unit, a driving voltage and current are provided to each lead of the flash memory channel, and the electrical signal is received by the selected Target, thereby requiring a stronger driving capability of the port of the control unit coupled to the flash memory channel to effectively drive the flash memory channel in the case of different NVM chip configurations (number of NVM chips connected to the same flash memory channel, and/or number of targets within each NVM chip). For example, when a read command of the storage medium access command is executed, data is read from the selected Target, and in response to the read command of the storage medium access command, the selected Target outputs an electric signal to the flash memory channel, supplies a driving voltage and a current to each lead of the flash memory channel, and the control unit receives the electric signal. At this time, the ports of the coupled flash memory channels of the selected Target are required to have a strong driving capability so that the flash memory channels can be effectively driven in the case of different NVM chip configurations (the number of NVM chips connected to the same flash memory channel, the number of targets in each NVM chip).

Disclosure of Invention

The types of NVM chips such as flash memory chips are varied, and the driving capability of the NVM chips is designed by NVM chip manufacturers, and the driving capability of the NVM chips designed by different NVM chip manufacturers is also different. The drive capability of the NVM chip cannot be predicted when designing the control components and/or the memory device. In order to provide a storage device with multiple storage capacities, a manufacturer of a control unit needs to enable the control unit to flexibly adapt to multiple NVM chips when designing the control unit, and can provide a strong flash channel driving capability to optimize the mass storage device. However, in some cases, the NVM chips used in the memory devices may not be optimized for mass storage devices, and accordingly, their ability to drive the flash channels is weak, which is insufficient to accommodate all cases of NVM chip configuration (number of NVM chips connected to the same flash channel, and/or number of targets within each NVM chip), thereby resulting in the selected targets being poor in terms of driving capability during read commands in response to storage medium access commands (hereinafter, as is not specifically stated, the read commands refer to read commands of storage medium access commands), which in turn affects the proper reception of data read from the NVM chips by the control unit. Since the driving capability of the coupled NVM chips cannot be predicted, the embodiments of the present application provide different clock frequencies for programming command processing and read command processing by improving the interface circuitry of the control unit, in the case of memory devices having different NVM chip configurations. For example, the clock frequency for programming command processing is higher than the clock frequency for read command processing. To increase the speed of processing programming commands by higher clock frequencies; the read command is processed by the clock frequency lower than the programming command, so that the signal quality is improved in the process of reading data, the requirement on the driving capability of the NVM chip in the process of processing the read command is reduced, and the problem that the quality of signals transmitted on a flash memory channel is poor due to the insufficient driving capability of the NVM chip, and the correct receiving of the data read from the NVM chip by a control part is affected is avoided.

According to a first aspect of the present application, there is provided an interface circuit of a control unit operating an NVM chip according to the first aspect of the present application, the interface circuit comprising: the DQ interface circuit is connected with the DQ signal PAD through the RE interface circuit; wherein the first clock couples the DQ interface circuit, the DQS interface circuit, the DQ signal PAD, and the DQS signal PAD; the second clock couples the RE interface circuit and the RE signal PAD; the DQ interface circuit is coupled with the DQ signal PAD; the DQS interface circuit is coupled with the DQS signal PAD; the RE interface circuit couples the DQ signal PAD.

An interface circuit of a control unit of a first operational NVM chip according to a first aspect of the present application provides an interface circuit of a control unit of a second operational NVM chip according to the first aspect of the present application, the interface circuit further comprising: a selector; the first clock and the second clock are coupled to an input of the selector; the output of the selector couples the DQ interface circuit, the DQS interface circuit, the DQ signal PAD, and the DQS signal PAD.

An interface circuit of a control unit of a first or second operation NVM chip according to the first aspect of the present application, which includes a DQ physical layer circuit for transmission, a DQ driver for transmission, a DQ physical layer circuit for reception, and a DQ driver for reception, is provided; the DQ physical layer circuit for transmitting is coupled with the DQ driver for transmitting; the DQ driver for transmitting couples the DQ signal PAD; the DQ physical layer circuit for receiving is coupled with the DQ driver for receiving; the DQ driver for receiving couples the DQ signal PAD.

An interface circuit of a control component of a third operational NVM chip according to the first aspect of the present application provides an interface circuit of a control component of a fourth operational NVM chip according to the first aspect of the present application, the DQS interface circuit comprising DQS physical layer circuitry for transmitting, DQS driver for transmitting, DQS physical layer circuitry for receiving and DQS driver for receiving; the DQS physical layer circuit for transmitting is coupled with the DQS driver for transmitting; the DQS driver for transmitting couples the DQS signal PAD; the DQS physical layer circuit for receiving couples the DQS driver for receiving; the DQS driver for receiving couples to the DQS signal PAD.

An interface circuit for operating a control component of an NVM chip according to one of the first to fourth aspects of the present application, the interface circuit comprising an RE physical layer circuit and an RE driver, is provided according to a fifth aspect of the present application; the RE physical layer circuit is coupled to the RE driver; the RE driver is coupled to the RE signal PAD.

According to a second aspect of the present application, there is provided an interface circuit of a control unit of a first operation NVM chip according to the second aspect of the present application, the interface circuit comprising: the DQ interface circuit is connected with the DQ signal PAD through the RE interface circuit; wherein the first clock provides a first clock signal and the second clock provides a second clock signal, the frequency of the second clock signal being less than the frequency of the first clock signal; the DQ interface circuit generates a DQ signal based on the first clock signal, and drives the DQ signal PAD based on the first clock signal to apply the DQ signal to DQ signal lines of the NVM chip; the DQS interface circuit generating a DQS signal based on the first clock signal and driving the DQS signal PAD based on the first clock signal to apply the DQS signal to DQS signal lines of the control component for coupling to the NVM chip; the RE interface circuit generates an RE signal based on the second clock signal and drives the RE signal PAD to apply the RE signal to RE signal lines of the NVM chip based on the second clock signal.

An interface circuit of a control unit of a first operation NVM chip according to a second aspect of the present application, which further drives the DQ signal PAD to collect a DQ signal from a DQ signal line of the NVM chip; the DQS interface circuit also drives the DQS signal PAD to collect DQS signals from DQS signal lines of the NVM chip.

An interface circuit of a control section of a first or second operation NVM chip according to a second aspect of the present application, the interface circuit of a control section of a third operation NVM chip according to the second aspect of the present application including a DQ physical layer circuit for transmission and a DQ driver for transmission; wherein the first clock provides the first clock signal for the DQ physical layer circuit for transmitting and the DQ driver for transmitting; the DQ physical layer circuit for transmitting controls the DQ driver for transmitting to output data to be written to an NVM chip to the DQ signal PAD based on the first clock signal.

An interface circuit of a control component operating an NVM chip according to one of the first to third aspects of the present application, an interface circuit of a control component operating an NVM chip according to the fourth aspect of the present application is provided, the DQS interface circuit including DQS physical layer circuitry for transmitting and a DQS driver for transmitting; the DQS physical layer for transmitting circuit controls the DQS driver for transmitting to output the generated DQS signal to the DQS signal PAD based on the first clock signal.

According to an interface circuit of a control section of a fourth operation NVM chip of the second aspect of the present application, there is provided an interface circuit of a control section of a fifth operation NVM chip of the second aspect of the present application, the DQS physical layer circuit for transmitting controls the DQ driver for transmitting to output the data to be written to the NVM chip to the DQ signal PAD while the DQS signal is inverted.

An interface circuit for operating a control component of an NVM chip according to one of the first to fifth aspects of the present application provides an interface circuit for operating a control component of an NVM chip according to the sixth aspect of the present application, the RE interface circuit comprising: RE physical layer circuitry and RE driver; wherein the second clock provides the second clock signal to the RE physical layer circuit and the RE driver; the RE physical layer circuit controls the RE driver to output the generated RE signal to the RE signal PAD based on the second clock signal.

An interface circuit of a control component of a sixth operational NVM chip according to the second aspect of the present application, providing an interface circuit of a control component of a seventh operational NVM chip according to the second aspect of the present application, the DQS interface circuit further comprising DQS physical layer circuitry for receiving; the DQ interface circuit also comprises a DQ physical layer circuit for receiving and a DQ driver for receiving; the DQS physical layer circuit for receiving controls the DQS signal PAD to collect DQS signals from DQS signal lines of the control component for coupling the NVM chips, and responds to the DQS signals in a flip mode, the DQ physical layer circuit for receiving controls the DQ driver for receiving to drive the DQ signal PAD to collect DQ signals from DQ signal lines of the control component for coupling the NVM chips, and data read from the NVM chips are obtained from the DQ signals.

According to an interface circuit of a control unit of a seventh operation NVM chip of the second aspect of the present application, there is provided an interface circuit of a control unit of an eighth operation NVM chip of the second aspect of the present application, the DQ physical layer circuit for transmitting controls the DQ driver for transmitting to be turned off before the DQ driver for receiving drives the DQ signal PAD to collect a DQ signal from a DQ signal line of the control unit for coupling the NVM chip.

An interface circuit of a control component of an NVM chip according to the seventh or eighth aspect of the present application, providing an interface circuit of a control component of an NVM chip according to the ninth aspect of the present application, the DQS interface circuit further comprising DQS physical layer circuitry for receiving and DQS driver for receiving; the DQS physical layer circuit for receiving drives the DQS signal PAD by controlling the DQS driver for receiving to acquire DQS signals from DQS signal lines of the control component for coupling with the NVM chip; and the DQ physical layer circuit for receiving captures the inversion of the DQS signal and provides the DQ physical layer circuit for receiving, and the DQ physical layer circuit for receiving responds to the inversion of the DQS signal to control the DQ driver for receiving to drive the DQ signal PAD to acquire the DQ signal from the DQ signal line of the NVM chip.

According to an interface circuit of a control component of a ninth operation NVM chip of the second aspect of the present application, there is provided an interface circuit of a control component of a tenth operation NVM chip of the second aspect of the present application, the DQS physical layer circuit for transmitting controls the DQS driver for transmitting to be turned off before the DQS signal PAD is driven by controlling the DQS driver for receiving to collect the DQS signal from a DQS signal line of the control component for coupling the NVM chip.

An interface circuit for operating a control unit of an NVM chip according to one of the seventh to tenth aspects of the present application provides an interface circuit for operating a control unit of an NVM chip according to the eleventh aspect of the present application, the interface circuit further comprising: a sending buffer and/or a receiving buffer; the transmission buffer is coupled with the DQ physical layer circuit for transmission, and provides data for generating DQ signals for the physical layer circuit of the DQ signals; the receiving buffer is coupled with the DQ physical layer circuit for receiving and is used for storing DQ signals acquired by the DQ physical layer circuit for receiving from DQ signal lines of the NVM chip.

An interface circuit for operating a control unit of an NVM chip according to one of the first to eleventh aspects of the present application provides an interface circuit for operating a control unit of an NVM chip according to the twelfth aspect of the present application, the interface circuit further comprising: a selector; the selector is coupled with the first clock and the second clock, and an output of the selector is coupled with the DQ interface circuit and the DQS interface circuit; the selector is configured to select whether to provide the first clock signal or the second clock signal to the DQ interface circuit and the DQs interface circuit.

An interface circuit of a control unit operating an NVM chip according to one of the first to twelfth aspects of the present application provides an interface circuit of a control unit operating an NVM chip according to the thirteenth aspect of the present application, the frequencies of the first clock signal and the second clock signal being set based on the frequency of a specified clock signal configured by the NVM chip.

According to a third aspect of the present application, there is provided an interface circuit of a control unit operating an NVM chip according to the first aspect of the present application, the interface circuit comprising: a first clock, a second clock, a physical layer circuit for transmitting data, a DQS driver for transmitting, a DQ driver for transmitting, a physical layer circuit for receiving data, a DQS driver for receiving, a DQ driver for receiving, a RE driver, a DQ signal PAD, a DQS signal PAD, and a RE signal PAD; wherein the first clock couples the physical layer circuit for transmitting data, DQS driver for transmitting, and DQ driver for transmitting; the second clock couples the physical layer circuit for receiving data, DQS driver for receiving, DQ driver for receiving and RE driver; the DQ driver for transmitting and the DQ driver for receiving couple the DQ signal PAD; the DQS driver for transmitting and the DQS driver for receiving couple the DQS signal PAD; the RE driver is coupled to the RE signal PAD.

An interface circuit of a control unit of a first operation NVM chip according to a third aspect of the present application, an interface circuit of a control unit of a second operation NVM chip according to the third aspect of the present application is provided, the interface circuit further comprising a selector; the first clock and the second clock are coupled to an input of the selector; the output of the selector couples the physical layer circuit for transmitting data, DQS driver for transmitting, and DQ driver for transmitting.

According to an interface circuit of a control section of a second operation NVM chip of a third aspect of the present application, there is provided an interface circuit of a control section of a third operation NVM chip of the third aspect of the present application, a physical layer circuit for transmitting data controls the DQS driver for transmitting to output a generated DQS signal to the DQS signal PAD based on the first clock signal, and controls the DQ driver for transmitting to output the generated DQ signal to the DQS signal PAD while the DQS signal is inverted.

An interface circuit of a control unit of a third operational NVM chip according to the third aspect of the present application, providing an interface circuit of a control unit of a fourth operational NVM chip according to the third aspect of the present application, the interface circuit further comprising a transmit buffer; the transmission buffer is coupled to the physical layer circuit for transmitting data, and is used for providing the data for generating DQ signals to the physical layer circuit for transmitting data.

An interface circuit of a control section of an NVM chip according to one of first to fourth aspects of the present application is provided, and an interface circuit of a control section of an NVM chip according to a fifth aspect of the present application is provided, a physical layer circuit for receiving data controls the RE driver to output a generated RE signal to the RE signal PAD based on the second clock signal, controls the DQS driver for receiving DQS signal from the DQS signal PAD, and controls the DQ driver for receiving transmission to acquire DQ signal from the DQ signal PAD in response to occurrence of flip of the DQS signal.

An interface circuit of a control unit of a fifth operational NVM chip according to the third aspect of the present application, providing an interface circuit of a control unit of a sixth operational NVM chip according to the third aspect of the present application, the interface circuit further comprising a receive buffer; the receiving buffer is coupled to the physical layer circuit for receiving data and is used for receiving the acquired DQ signals from the physical layer circuit for receiving data.

An interface circuit for operating a control unit of an NVM chip according to one of the first to sixth aspects of the present application provides an interface circuit for operating a control unit of an NVM chip according to the seventh aspect of the present application, the frequency of the first clock signal being greater than the frequency of the second clock signal.

According to a fourth aspect of the present application, there is provided an interface circuit of a first control unit operating an NVM chip according to the fourth aspect of the present application, the interface circuit operating the control unit of the NVM chip, the interface circuit comprising: a first clock, a second clock, a physical layer circuit for transmitting data, a DQS driver for transmitting, a DQ driver for transmitting, a physical layer circuit for receiving data, a DQ driver for receiving, a RE driver, a DQ signal PAD, a DQS signal PAD, and a RE signal PAD; wherein the first clock couples the physical layer circuit for transmitting data, DQS driver for transmitting, and DQ driver for transmitting; the second clock is coupled with the physical layer circuit for receiving data, the DQ driver and the RE driver for receiving; the DQ driver for transmitting and the DQ driver for receiving couple the DQ signal PAD; the DQS driver for transmitting couples the DQS signal PAD; the DQ driver, the RE driver, and the DQS signal PAD for receiving couple the physical layer circuitry for receiving data; the RE driver is coupled to the RE signal PAD.

An interface circuit of a control unit of a first operation NVM chip according to a fourth aspect of the present application, providing an interface circuit of a control unit of a second operation NVM chip according to the fourth aspect of the present application, the interface circuit further comprising a selector; the first clock and the second clock are coupled to an input of the selector; the output of the selector couples the physical layer circuit for transmitting data, DQS driver for transmitting, and DQ driver for transmitting.

According to an interface circuit of a control section of a second operation NVM chip of the fourth aspect of the present application, there is provided an interface circuit of a control section of a third operation NVM chip of the fourth aspect of the present application, a physical layer circuit for transmitting data controls the DQS driver for transmitting to output a generated DQS signal to the DQS signal PAD based on the first clock signal, and controls the DQ driver for transmitting to output the generated DQ signal to the DQ signal PAD while the DQS signal is inverted.

An interface circuit of a control unit of a third operational NVM chip according to a fourth aspect of the present application, the interface circuit further comprising a transmit buffer; the transmission buffer is coupled to the physical layer circuit for transmitting data, and is used for providing the data for generating DQ signals to the physical layer circuit for transmitting data.

An interface circuit of a control section of an NVM chip according to one of first to fourth aspects of the present application is provided, and an interface circuit of a control section of an NVM chip according to a fifth aspect of the present application is provided, the physical layer circuit for receiving data controls the RE driver to output the generated RE signal to the RE signal PAD based on the second clock signal, and receives the DQS signal from the DQS signal PAD, and the DQ driver for receiving transmission acquires the DQ signal from the DQ signal PAD in response to occurrence of flip of the DQS signal.

An interface circuit of a control unit of a fifth operational NVM chip according to the fourth aspect of the present application, providing an interface circuit of a control unit of a sixth operational NVM chip according to the fourth aspect of the present application, the interface circuit further comprising a receive buffer; the receiving buffer is coupled to the physical layer circuit for receiving data and is used for receiving the acquired DQ signals from the physical layer circuit for receiving data.

An interface circuit of a control unit operating an NVM chip according to one of the first to sixth aspects of the present application provides an interface circuit of a control unit operating an NVM chip according to the seventh aspect of the present application, the frequency of the first clock signal being greater than the frequency of the second clock signal.

According to a fifth aspect of the present application, there is provided a method of operating an NVM chip according to the fifth aspect of the present application, the method comprising: generating a DQ signal based on the first clock signal control and applying the generated DQ signal to DQ signal lines of the control component for coupling the NVM chip; and controlling generation of a DQS signal based on the first clock signal and applying the generated DQS signal to DQS signal lines of the control component for coupling the NVM chip; generating an RE signal based on a second clock signal control, and applying the generated RE signal to an RE signal line of the control unit for coupling to the NVM chip, wherein the second clock signal has a frequency that is less than a frequency of the first clock signal.

According to a first method of operating an NVM chip of a fifth aspect of the present application, there is provided a second method of operating an NVM chip according to the fifth aspect of the present application, controlling DQ signal lines coupling data to be written to the NVM chip while controlling the DQS signal flip based on the first clock signal.

According to a first or second method of operating an NVM chip of a fifth aspect of the present application, there is provided a third method of operating an NVM chip according to the fifth aspect of the present application, further comprising: responsive to coupling the generated RE signal to an RE signal line of the NVM chip based on the second clock signal, collecting a DQS signal from a DQS signal line of the NVM chip; and acquiring DQ signals from DQ signal lines of the NVM chip in response to the acquired DQS signal flip.

A method of operating an NVM chip according to one of the first to third aspects of the present application provides a fourth method of operating an NVM chip according to the fifth aspect of the present application, further comprising: generating a DQ signal based on the second clock signal control and applying the generated DQ signal to DQ signal lines of the control component for coupling the NVM chip; and controlling generation of a DQS signal based on the second clock signal and applying the generated DQS signal to DQS signal lines of the control component for coupling the NVM chip.

According to a sixth aspect of the present application, there is provided a control unit according to the sixth aspect of the present application, the control unit comprising: the interface circuit according to one of the first to fourth aspects.

According to a seventh aspect of the present application, there is provided a storage device according to the seventh aspect of the present application, the storage device comprising: the control unit according to the sixth aspect.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following description will briefly introduce the drawings that are required to be used in the embodiments or the description of the prior art, and it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings may also be obtained according to these drawings for a person having ordinary skill in the art.

FIG. 1A is a block diagram of a prior art memory device;

FIG. 1B is a block diagram of a control component of a prior art memory device;

FIG. 1C illustrates waveforms of a Data In Cycle (Data In Cycle) defined by the ONFI protocol;

FIG. 1D illustrates waveforms of a Data Out Cycle defined by the ONFI protocol;

FIG. 2 illustrates a block diagram of a control component of a memory device in connection with an NVM chip;

FIG. 3A is a schematic diagram illustrating an interface circuit of a control unit according to an embodiment of the present disclosure;

fig. 3B illustrates a schematic structure of a DQ interface circuit according to an embodiment of the present application;

FIG. 3C illustrates a schematic diagram of a DQS interface circuit as provided by an embodiment of the present application;

fig. 3D illustrates a schematic structural diagram of an RE interface circuit according to an embodiment of the present application;

FIG. 4 is a schematic diagram of an interface circuit of another control unit according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of an interface circuit of another control unit according to an embodiment of the present disclosure;

fig. 6 illustrates a flowchart of a method for operating an NVM chip according to an embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application, taken in conjunction with the accompanying drawings, clearly and completely describes the technical solutions of the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

Fig. 3A shows a schematic structural diagram of an interface circuit of a control unit according to an embodiment of the present application.

By way of example, as shown in FIG. 3A, the interface circuits include a clock A, a clock B, DQ interface circuit, a DQS interface circuit, an RE interface circuit, a DQ signal PAD, a DQS signal PAD, and an RE signal PAD. The DQ signal PAD is located within the control unit for coupling to DQ signal lines of the NVM chip for applying generated DQ signals to the DQ signal lines (e.g., during processing of a program command) or for collecting DQ signals from the DQ signal lines (e.g., during processing of a read command). The DQS signal PAD is located within the control component for coupling to the DQS signal line for applying the generated DQS signal to the DQS signal line or collecting the DQS signal from the DQS signal line. The RE signal PAD is located inside the control section for coupling the RE signal line for applying the generated RE signal to the RE signal line. The DQ interface circuit is coupled with the DQ signal PAD and is used for generating DQ signals and controlling the DQ signal PAD to couple the generated DQ signals to the DQ signal line; or for controlling the DQ signal PAD to collect DQ signals from the DQ signal line. The DQS interface circuit is coupled with the DQS signal PAD and is used for generating a DQS signal and controlling the DQS signal PAD to couple the generated DQS signal to the DQS signal line; or for controlling the DQS signal PAD to collect the DQS signal from the DQS signal line. The RE interface circuit is coupled to the RE signal PAD for generating an RE signal and controlling the RE signal PAD to couple the generated RE signal to the RE signal line.

With continued reference to FIG. 3A, clock A is coupled to DQ interface circuitry, DQS interface circuitry, DQ signal PAD, and DQS signal PAD for providing clock signal 1 to DQ interface circuitry, DQS interface circuitry, DQ signal PAD, and DQS signal PAD. The DQ interface circuit generates a DQ signal waveform shown in fig. 1C, for example, based on the clock signal 1, and the DQ interface circuit drives the DQ signal PAD based on the clock signal 1 to apply the generated DQ signal to the DQ signal line of the control block for coupling the NVM chip. The DQS interface circuit generates a DQS signal based on the clock signal 1, and drives the DQS signal PAD based on the clock signal 1 to apply the generated DQS signal to DQS signal lines of the control component for coupling the NVM chip, and the DQS interface circuit controls the DQ interface circuit to output data to be written to the NVM chip to the DQ signal PAD while the DQS signal is flipped.

It should be appreciated that for the DQ interface circuit and DQS interface circuit to be applied at clock frequencies that do not affect the waveforms of the DQ signals generated by the DQ interface circuit and the DQS signals generated by the DQ interface circuit, the DQ interface circuit and DQS interface circuit to be applied with clock signals of different clock frequencies always conform to the signal waveforms defined by the NVM chip interface protocol (e.g. ONFI protocol). For example, waveforms of the DQ signal and DQS signal are in accordance with the ONFI protocol as defined in FIG. 1C. Although the clock frequency of the clock signal 1 applied to the DQ interface circuit and the DQs interface circuit does not affect the waveforms of the DQ and DQs signals, the duration of each data input period is affected. For example, the DQ interface circuit scales the DQ signal generated from the clock signal 1 and the DQs signal generated by the DQs interface circuit based on the clock signal 1 equally by the waveforms of the DQ signal and the DQs signal defined by the ONFI protocol as shown in fig. 1C.

With continued reference to FIG. 3A, a clock B is coupled to the RE interface circuit and the RE signal PAD for providing a clock signal 2 to the RE interface circuit and the RE signal PAD. The RE interface circuit generates an RE signal waveform, such as shown in fig. 1D, based on clock signal 2, and the RE interface circuit drives RE signal PAD based on clock signal 2 to apply the generated RE signal to the RE signal lines of the control component for coupling the NVM chip. It should be appreciated that for clock frequency of clock signal 2 applied to the RE interface circuit that does not affect the waveform of the RE signal generated by the RE interface circuit, the RE interface circuit and the RE signal generated by the RE interface circuit applying clock signals of different clock frequencies always conform to the signal waveform defined by the NVM chip interface protocol (e.g., ONFI protocol). For example, the waveform of the RE signal as defined by the ONFI protocol as shown in fig. 1D. Although the clock frequency of the clock signal 2 applied to the RE interface circuit does not affect the waveform of the RE signal, it affects the duration of each data output period. For example, the RE interface circuit scales the RE signal generated from clock signal 2 equally based on the RE signal generated from clock signal 2 as defined by the ONFI protocol as shown in fig. 1D.

As shown in fig. 1C and 1D, the waveforms of signals transmitted between the control unit and the NVM chip are different during the read command processing and the program processing. For example, in processing a program command, in order to transfer data to be written to an NVM chip, an interface circuit of a control unit needs to generate DQ signals and DQs signals as shown in fig. 1C and transfer the data to be written to the NVM chip based on the DQ signals. In processing the read command, the interface circuit of the control unit needs to generate the RE signal as shown in fig. 1D, and the NVM chip generates the DQ signal and the DQs signal based on the signal frequency of the received RE signal so that the data read from the NVM chip is transferred based on the DQ signal. For ease of understanding, the following briefly describes the operation of the interface circuit of the embodiments of the present application during the processing of a program command and during the processing of a read command, respectively.

As an example, for the program command processing, the DQ interface circuit as shown in fig. 3A generates a DQ signal of the waveform shown in fig. 1C based on the clock signal 1 supplied from the clock a, and drives the DQ signal PAD based on the clock signal 1 to apply the generated DQ signal to the DQ signal line of the control section for coupling the NVM chip; and DQS interface circuitry generates a DQS signal of the waveform shown in FIG. 1C based on clock signal 1 and drives DQS signal PAD based on clock signal 1 to apply the generated DQS signal to DQS signal lines of the control component for coupling the NVM chip. In the process that the DQS interface circuit generates the DQS signal with the waveform shown in fig. 1C based on the clock signal 1, the DQS interface circuit outputs data to be written into the NVM chip to the DQ signal PAD while controlling the DQS signal to turn over, the data to be written into the NVM chip is coupled to the DQ signal line used for coupling the NVM chip through the DQ signal PAD by the control part, the NVM chip obtains the data to be written into the NVM chip through the DQ signal line, and programming operation is performed to write the data to be written into the NVM chip.

Also by way of example, for read command processing, an RE interface circuit as shown in FIG. 3A generates an RE signal based on clock signal 2 provided by clock B, and drives RE signal PAD based on clock signal 2 to apply the RE signal to RE signal lines of the control component for coupling to the NVM chip. The NVM chip taking over the DQ signal line to generate a DQ signal and coupling the generated DQ signal onto the DQ signal line in response to receiving the RE signal from the RE signal line; and taking over the DQS signal line to generate the DQS signal and coupling the generated DQS signal to the DQS signal line. The DQS interface circuit also drives the DQS signal PAD to collect DQS signals from DQS signal lines of the NVM chip, responds to the DQS signal inversion, and after a delay time (the delay time is the time from the edge to the center of the DQ signals as shown in FIG. 1D), the DQS interface circuit also drives the DQ signal PAD to collect DQ signals from DQ signal lines of the NVM chip, and acquires data read from the NVM chip from the DQ signals.

As can be seen from the above, when the control unit sends data to be written to the NVM chip, the DQ interface circuit needs to generate DQ signals, and when the NVM chip sends data read from the NVM chip to the control unit, the DQ interface circuit needs to collect DQ signals from the DQ signal lines, i.e. the DQ interface circuit shown in fig. 3A can generate DQ signals, or collect DQ signals from the DQ signal lines; the DQ interface circuit includes both a circuit for generating DQ signals and a circuit for acquiring DQ signals. Like the DQ interface circuit, the DQS interface circuit as shown in FIG. 3A includes both a circuit that generates the DQS signal and a circuit that gathers the DQS signal.

Fig. 3B illustrates a schematic structure of a DQ interface circuit according to an embodiment of the present application.

As an example, as shown in fig. 3B, the DQ interface circuit includes a DQ physical layer circuit for transmission (TX DQ PHY), a DQ driver for transmission, a DQ physical layer circuit for reception (RX DQ PHY), and a DQ driver for reception; the DQ physical layer circuit for transmitting is coupled with the DQ driver for transmitting, and the DQ driver for transmitting is coupled with the DQ signal PAD; and the DQ physical layer circuit for receiving is coupled with the DQ driver for receiving, and the DQ driver for receiving is coupled with the DQ signal PAD. For example, in the processing of a programming command, the DQ physical layer circuit for transmission controls the DQ driver for transmission to output data to be written to the NVM chip to the DQ signal PAD based on the clock signal 1 supplied by the clock a; the DQ driver for transmitting also drives DQ signal PAD based on clock signal 1 to couple data to be written to the NVM chip onto DQ signal lines used by the control unit to couple the NVM chip. For another example, during processing of a read command, the DQ physical layer circuit for receiving controls the DQ driver for receiving to drive the DQ signal PAD to collect the DQ signal from the DQ signal line and to obtain the data read from the NVM chip from the DQ signal.

As another example, in the process that the DQ physical layer circuit for receiving controls the DQ driver for receiving to drive the DQ signal PAD to collect the DQ signal from the DQ signal line, since the DQ driver for transmitting is also electrically connected to the DQ signal PAD, when the DQ physical layer circuit for receiving controls the DQ driver for receiving to drive the DQ signal PAD to collect the DQ signal from the DQ signal line, the electrical connection between the DQ driver for transmitting and the DQ signal PAD may affect the receiving signal of the DQ signal PAD, which may cause the DQ driver for receiving to fail to receive the DQ signal or fail to receive the correct DQ signal. In order to enable the receiving DQ driver to receive the DQ signals sent by the NVM chip, the receiving DQ physical layer circuit is turned off to control the sending DQ driver before the receiving DQ physical layer circuit controls the receiving DQ driver to drive the DQ signal PAD to collect the DQ signals from the DQ signal line, so that the receiving DQ physical layer circuit is prevented from responding to the DQ signal PAD to collect the DQ signals.

As another example, as shown in fig. 3B, the interface circuit of the embodiment of the present application further includes a transmit buffer and a receive buffer; the transmission buffer is coupled with the DQ physical layer circuit for transmission, and provides data for generating DQ signals for the DQ physical layer circuit for transmission; the receiving buffer is coupled to the DQ physical layer circuit for receiving the acquired DQ signals from the DQ physical layer circuit for receiving.

Fig. 3C illustrates a schematic diagram of a DQS interface circuit according to an embodiment of the disclosure.

By way of example, as shown in FIG. 3C, DQS interface circuitry includes DQS physical layer circuitry for transmitting (TX DQS PHY), DQS driver for transmitting, DQS physical layer for receiving (RX DQS PHY) circuitry, and DQS driver for receiving; the DQS physical layer circuit for sending is coupled with the DQS driver for sending, and the DQS driver for sending is coupled with the DQS signal PAD; and the DQS physical layer circuitry for receiving is coupled to the DQS driver for receiving, the DQS driver for receiving is coupled to the DQS signal PAD. For example, during processing of a programming command, the DQS physical layer circuit for transmitting controls the DQS driver for transmitting to output the generated DQS signal to the DQS signal PAD based on the clock signal 1 provided by the clock A and the DQ driver for transmitting to output data to be written to the NVM chip to the DQ signal PAD while the DQS signal is flipped. For another example, during processing of a read command, DQS physical layer circuitry for receiving controls DQS drivers for receiving to drive DQS signal PAD to collect the DQS signal from the DQS signal line.

As another example, in the process that the DQS physical layer circuit for receiving controls the DQS driver for receiving to drive the DQS signal PAD to collect the DQS signal from the DQS signal line, since the DQS driver for transmitting is also electrically connected to the DQS signal PAD, when the DQS physical layer circuit for receiving controls the DQS driver for receiving to drive the DQS signal PAD to collect the DQS signal from the DQS signal line, the DQS signal PAD is affected by the presence of the DQS driver for transmitting, which may cause the DQS driver for receiving to fail to receive the DQS signal or fail to receive the correct DQS signal. In order for the receiving DQS driver to receive the DQS signal sent by the NVM chip, the receiving DQS physical layer circuit controls the sending DQS driver to close before the receiving DQS driver drives the DQS signal PAD to collect the DQS signal from the DQS signal line, so as to avoid the sending DQS driver responding to the DQS signal PAD to collect the DQS signal.

Fig. 3D illustrates a schematic structural diagram of an RE interface circuit according to an embodiment of the present application.

By way of example, as shown in fig. 3D, the RE interface circuit includes RE physical layer circuitry (RE PHY) and RE drivers; wherein the RE physical layer circuit is coupled to an RE driver, which is coupled to an RE signal PAD. For example, during read command processing, the physical layer circuitry of the RE signal controls the RE driver to output the generated RE signal to the RE signal PAD based on clock signal 2 provided by clock B, and the RE driver drives the RE signal PAD based on clock signal 2 to apply the generated RE signal to the RE signal line of the control component for coupling to the NVM chip.

For programming command processing, the control unit sends an electrical signal to the NVM chip, driven by an interface of the control unit coupled to the flash channel; for read command processing, an electrical signal is sent by the NVM chip (NVM chip or Target from which data is to be read) to the control unit, driven by the interface of the NVM chip coupled to the flash channel. In a possible implementation, since the driving capability of the NVM chip may be insufficient and the reception of the signal from the NVM chip by the control unit is affected, to solve this problem, the clock frequency of the clock signal applied to the RE interface circuit and the RE signal PAD during the processing of the read command is different from the clock frequency of the clock signal applied to the DQ interface circuit, the DQs interface circuit, the DQ signal PAD and the DQs signal PAD during the processing of the program command. For example, the clock frequency of the clock signals applied to the RE interface circuit and RE signal PAD is less than the clock frequency of the clock signals applied to the DQ interface circuit, DQS interface circuit, DQ signal PAD, and DQS signal PAD. That is, the clock frequency of the clock signal provided by the read command processing is less than the clock frequency of the clock signal provided by the program command processing. The NVM chip is caused to output the read data at a lower rate by reducing the clock frequency applied to the RE interface circuitry during read command processing. When the signal output rate decreases, the problem of insufficient drive capability of the NVM chip to the flash channel is overcome. Thus, although no improvement is made to the NVM chip, the interface circuitry of the control unit controls the NVM chip to use a lower frequency clock when applying RE signals during processing of read commands (as compared to the clock frequency used during processing of programming commands) to take a lower rate when outputting data during processing of read commands.

As another example, as shown in fig. 3A, the clock a and the clock B are different clocks, so as to adapt to different scenes, and improve applicability of the interface circuit in the embodiment of the present application, where the interface circuit in the embodiment of the present application further includes a selector; clock a and clock B couple the inputs of the selector; the DQ interface circuit, the DQS interface circuit, the DQ signal PAD and the DQS signal PAD are coupled with the output of the selector, so that the selector can apply the clock signal 1 provided by the clock A to the DQ interface circuit, the DQS interface circuit, the DQ signal PAD and the DQS signal PAD and can also apply the clock signal 2 provided by the clock B to the DQ interface circuit, the DQS interface circuit, the DQ signal PAD, the RE interface circuit and the RE signal PAD according to different requirements. Thus, clock B may be used to drive both the RE interface circuit and RE signal PAD, and DQ interface circuit, DQ signal PAD, DQS interface circuit and DQS signal PAD, while clock A is used to drive only DQ interface circuit, DQ signal PAD, DQS interface circuit and DQS signal PAD, but clock A is not used to drive RE interface circuit and RE signal PAD.

Also for example, the signal frequency of clock signal 1 provided by clock a is greater than the signal frequency of clock signal 2 provided by clock B. For example, selecting clock signal 1 provided by clock A for DQ interface circuit, DQS interface circuit, DQ signal PAD and DQS signal PAD by a selector; the RE interface circuit and RE signal PAD are driven by clock signal 2 provided by clock B. For example, in processing a programming command, the DQ interface circuit may generate a DQ signal based on clock signal 1 and drive DQ signal PAD to apply the generated DQ signal to DQ signal lines of the control component for coupling the NVM chip, the DQS interface circuit generates a DQS signal based on clock signal 1, and drive DQS signal PAD to apply the DQS signal to DQS signal lines of the control component for coupling the NVM chip based on clock signal 1. While processing the read command, the RE interface circuit generates an RE signal based on clock signal 2 and drives RE signal PAD based on clock signal 2 to apply the RE signal to the RE signal line of the control unit for coupling to the NVM chip. The read command processing and the program command processing are respectively provided with independent clocks, the difference of the clock signal frequency provided by the clock A and the clock signal frequency provided by the clock B is set to control the difference of the signal frequency of the interaction signals between the control component corresponding to the program command processing and the read command processing and the NVM chip, for example, the read command processing is performed by using the clock frequency lower than the clock frequency corresponding to the program command processing, so that the influence of insufficient driving capability on the signal quality when the NVM chip outputs data is overcome, the accuracy of the data received by the control component is improved, and the performance of the storage device is further improved. In an embodiment, the clock frequency of the clock signals provided by clock a and clock B may be set at the frequency of the designated clock signal configured by the NVM chip.

With continued reference to fig. 3A, in an alternative embodiment, although clock a is present in the interface circuit, clock a may not be used, but only clock B may be used, in some application scenarios, by the selector. For example, when it is recognized that the NVM chip to which the control unit is coupled has good driving capability, it is not necessary to actively reduce the frequency of the RE signal during processing of the read command, so that the same clock B is used to drive the interface circuit during processing of the read command and processing of the program command.

The physical layer circuitry in the interface circuitry may be designed according to the signal (DQ, DQS, RE signal) (as shown in fig. 3B, 3C, 3D above) or may be designed according to the functionality of processing a programming command (data input period) and processing a read command (data output period) (as shown in fig. 4 below).

Fig. 4 shows a schematic structural diagram of an interface circuit of another control component according to an embodiment of the present application.

As shown in fig. 4, the interface circuit includes a clock C, a clock D, a physical layer circuit (TX PHY) for transmitting data, a DQS driver (TX DQS Drive) for transmitting, a DQ driver (TX DQ Drive) for transmitting, a physical layer circuit (RX PHY) for receiving data, a DQS driver (RX DQS Drive) for receiving, a DQ driver (RX DQ Drive) for receiving, a RE driver (RE Drive), a DQ signal PAD, a DQS signal PAD, and a RE signal PAD, for example. Clock C couples the physical layer circuit for transmitting data, DQS driver for transmitting and DQ driver for transmitting; clock D couples the physical layer circuit for receiving data, DQS driver for receiving, DQ driver for receiving and RE driver; a DQ driver for transmitting and a DQ driver for receiving couple the DQ signal PAD; the DQS driver for transmitting and the DQS driver for receiving couple the DQS signal PAD; the RE driver is coupled to the RE signal PAD.

With continued reference to fig. 4, the physical layer circuit for transmitting data is coupled to the DQS driver for transmitting and the DQ driver for transmitting, and the physical layer circuit for transmitting data may control the DQS driver for transmitting to send the generated DQS signal to the DQS signal PAD, or may control the DQ driver for transmitting to output the generated DQ signal to the DQ signal PAD, i.e., control the DQS driver for transmitting and the DQ driver for transmitting to be the same physical layer circuit. For example, in response to processing the programming command, the physical layer circuit for transmitting data controls the DQS driver for transmitting to output the generated DQS signal to the DQS signal PAD based on the clock signal provided by clock C; in addition, the physical layer circuit for transmitting data while the DQS signal is inverted also controls the DQ driver for transmitting to output the generated DQ signal to the DQ signal PAD.

As another example, as shown in fig. 4, the interface circuit further includes a transmit buffer; the transmission buffer is coupled to the physical layer circuit for transmitting data, the transmission buffer is used for storing data used for generating DQ signals, and the physical layer circuit for transmitting data outputs the generated DQ signals to the DQ signal PAD for controlling the DQ driver for transmitting, and the transmission buffer provides the data used for generating the DQ signals to the physical layer circuit for transmitting data.

As another example, to accommodate different scenarios, the clock signals applied to the physical layer circuitry for transmitting data, DQS driver for transmitting, and DQ driver for transmitting may be switched or selected to improve the applicability of the interface circuits of embodiments of the present application. As shown in fig. 4, the interface circuit further includes a selector; the clock C and the clock D are coupled with the input of the selector; the output of the selector is coupled to the physical layer circuit for transmitting data, the DQS driver for transmitting and the DQ driver for transmitting, and the selector can select the coupling of the clock C and the physical layer circuit for transmitting data, the DQS driver for transmitting and the DQ driver for transmitting, or the coupling of the clock D and the physical layer circuit for transmitting data, and the DQS driver for transmitting and the DQ driver for transmitting.

With continued reference to fig. 4, the interface circuit of the embodiments of the present application may not only send data to be sent by the control component to the NVM chip, but may also receive data read from the NVM chip. The interface circuit controls the reception of data read from the NVM chip by a physical layer circuit for receiving data. By way of example, the physical layer circuit for receiving data is coupled to the DQS driver for receiving, the DQ driver for receiving, and the RE driver, and the physical layer circuit for receiving data controls the RE driver to output the generated RE signal to the RE signal PAD based on the clock signal provided by the clock D and applies the generated RE signal to the RE signal line of the control component for coupling the NVM chip via the RE signal PAD. The NVM chip, in response to receiving the RE signal from the RE signal line, takes over the DQ signal line and the DQs signal line by the NVM chip, generates DQ signals and DQs signals and applies the generated DQ signals to the DQ signal line and the generated DQs signals to the DQs signal line. The physical layer circuit for receiving the data controls the DQS driver for receiving to drive the DQS signal PAD to collect the DQS signal from the DQS signal line, responds to the inversion of the DQS signal, and controls the DQ driver for receiving to drive the DQ signal PAD to collect the DQ signal from the DQ signal line after delaying for a period of time.

As another example, as shown in fig. 4, the interface circuit further includes a receiving buffer; the receive buffer is coupled to the physical layer circuitry for receiving data and is configured to receive the collected DQ signals from the physical layer circuitry for receiving data.

As another example, as shown in fig. 4, the signal frequency of the clock signal provided by the clock C is greater than the signal frequency of the clock signal provided by the clock D. For example, the clock signal provided by clock C is selected for DQ interface circuit, DQS interface circuit, DQ signal PAD and DQS signal PAD by the selector; the RE interface circuit and RE signal PAD are clocked by clock D. For example, in processing a programming command, the DQ interface circuit may generate a DQ signal based on a clock signal provided by clock C and drive a DQ signal PAD to apply the generated DQ signal to DQ signal lines of the control component for coupling the NVM chip, the DQS interface circuit generates a DQS signal based on the clock signal provided by clock C, and drive the DQS signal PAD to apply the DQS signal to DQS signal lines of the control component for coupling the NVM chip based on the clock signal provided by clock C. While processing the read command, the RE interface circuit generates an RE signal based on the clock signal provided by clock D and drives the RE signal PAD to apply the RE signal to the RE signal line of the control unit for coupling to the NVM chip based on the clock signal provided by clock D. The read command processing and the program command processing are respectively provided with independent clocks, and the difference between the clock signal frequency provided by the clock C and the clock signal frequency provided by the clock D is set to control the difference between the signal frequencies of the interaction signals of the control component corresponding to the program command processing and the read command processing and the NVM chip, for example, the read command processing is performed by using the clock frequency lower than the clock frequency corresponding to the program command processing, so that the accuracy of the data received by the control component is improved, and the performance of the storage device is further improved.

Fig. 5 shows a schematic structural diagram of an interface circuit of another control component according to an embodiment of the present application.

By way of example, as shown in fig. 5, the interface circuit includes a clock C, a clock D, a physical layer circuit for transmitting data, a DQS driver for transmitting, a DQ driver for transmitting, a physical layer circuit for receiving data, a DQ driver for receiving, a RE driver, a DQ signal PAD, a DQS signal PAD, and a RE signal PAD. Clock C couples the physical layer circuit for transmitting data, DQS driver for transmitting and DQ driver for transmitting; the clock D is coupled with a physical layer circuit for receiving data, a DQ driver and an RE driver for receiving; the DQ driver for transmitting and the DQ driver for receiving couple the DQ signal PAD; the DQS driver for transmitting couples the DQS signal PAD; the DQ driver, the RE driver and the DQS signal PAD are coupled to receive the physical layer circuit for receiving data; the RE driver is coupled to the RE signal PAD.

With continued reference to fig. 5, the physical layer circuit for transmitting data is coupled to the DQS driver for transmitting and the DQ driver for transmitting, and the physical layer circuit for transmitting data may control the DQS driver for transmitting to send the generated DQS signal to the DQS signal PAD, or may control the DQ driver for transmitting to output the generated DQ signal to the DQ signal PAD, i.e., control the DQS driver for transmitting and the DQ driver for transmitting to be the same physical layer circuit. For example, in response to processing the programming command, the physical layer circuit for transmitting data controls the DQS driver for transmitting to output the generated DQS signal to the DQS signal PAD based on the clock signal provided by clock C; in addition, the physical layer circuit for transmitting data while the DQS signal is inverted also controls the DQ driver for transmitting to output the generated DQ signal to the DQ signal PAD.

As another example, as shown in fig. 5, the interface circuit further includes a transmit buffer; the transmission buffer is coupled to the physical layer circuit for transmitting data, the transmission buffer is for storing data for generating a DQ signal, and the transmission buffer supplies the data for generating a DQ signal to the physical layer circuit for transmitting data before the physical layer circuit for transmitting data controls the DQ driver for transmitting to output the generated DQ signal to the DQ signal PAD.

As another example, to accommodate different scenarios, the clock signals applied to the physical layer circuitry for transmitting data, DQS driver for transmitting, and DQ driver for transmitting may be switched or selected to improve the applicability of the interface circuit of embodiments of the present application. As shown in fig. 5, the interface circuit further includes a selector; the clock C and the clock D are coupled with the input of the selector; the output of the selector is coupled to the physical layer circuit for transmitting data, the DQS driver for transmitting and the DQ driver for transmitting, and the selector may select either the clock C to be coupled to the physical layer circuit for transmitting data, the DQS driver for transmitting to be coupled to the DQ driver for transmitting, or the clock D to be coupled to the physical layer circuit for transmitting data, the DQS driver for transmitting to be coupled to the DQ driver for transmitting.

With continued reference to fig. 5, the interface circuit of the embodiments of the present application may not only send data to be sent by the control component to the NVM chip, but may also receive data read by the NVM chip from the NVM chip. The interface circuit controls the reception of data read by the NVM chip from the NVM chip by a physical layer circuit for receiving the data. By way of example, the physical layer circuit for receiving data is coupled with the DQ driver for receiving and the RE driver, and the physical layer circuit for receiving data controls the RE driver to output the generated RE signal to the RE signal PAD based on the clock signal supplied by the clock D, and applies the generated RE signal to the RE signal line for coupling the NVM chip through the RE signal PAD. The NVM chip, in response to receiving the RE signal from the RE signal line, takes over the DQ signal line and the DQs signal line by the NVM chip, generates DQ signals and DQs signals and applies the generated DQ signals to the DQ signal line and the generated DQs signals to the DQs signal line. The DQS signal PAD is driven by a physical layer circuit for receiving data, the DQS signal PAD is collected from a DQS signal line, and after the DQS signal is overturned, the DQ driver for receiving is controlled to drive the DQ signal PAD to collect the DQ signal from the DQ signal line after a period of delay.

As another example, as shown in fig. 5, the interface circuit further includes a receiving buffer; the receive buffer is coupled to the physical layer circuitry for receiving data and is configured to receive the collected DQ signals from the physical layer circuitry for receiving data.

In the process of data interaction between the interface circuit of the control component and the NVM chip coupled with the control component, the control component can send a group of signals conforming to the interface protocol of the NVM chip to the flash memory channel through the interface circuit, and the NVM chip receives the signals through the flash memory channel; a set of signals conforming to the interface protocol of the NVM chip can also be sent by the NVM chip, and the control unit receives the signals sent by the NVM chip through the interface circuit. Since the control unit sends signals to the NVM chip, the driving capability of the control unit is required for driving, and the NVM chip sends signals to the control unit, the driving capability of the NVM chip is required for driving. Because the driving capabilities of the control component and the NVM chip may be different, the interface circuit of the embodiments of the present application may provide clock signals of different clock frequencies for the control component to send signals to the NVM chip than for the NVM chip to send signals to the control component. For example, the control unit may provide a stronger drive capability in view of mass storage during design, in which case the control unit uses a higher frequency clock signal when sending signals to the NVM chip than when sending signals to the control unit during read-out of data. The NVM chip may use a lower rate when sending signals to the control component relative to the rate at which the control component sends signals to the NVM chip; if the control unit sends signals to the NVM chip at a rate of 2000MT/s (Million Transfers Per Second, millions of transmissions per second), the NVM chip sends signals to the control unit at a clock frequency of 1600MT/s.

For ease of understanding, the following briefly describes the operation of the interface circuit of the embodiments of the present application for providing separate and different clock signals for the NVM chip to send signals to the control unit and for the control unit to send signals to the NVM chip.

As an example, the method as shown in fig. 6 can be applied to the interface circuits shown in fig. 3A to 3D, fig. 4, and fig. 5; the method comprises the following steps:

in the process that the control component sends signals to the NVM chip, an interface circuit of the control component needs to generate DQ signals and DQS signals, and sends the generated DQ signals and DQS signals to the NVM chip; wherein the DQ signal content includes data to be written to the NVM chip. In order to generate the DQ signal and the DQs signal and send the generated DQ signal and DQs signal to the NVM chip, the interface circuit of the embodiment of the present application performs the following step 601:

step 601, the interface circuit controls generation of DQ signals based on the clock signal A1, and applies the generated DQ signals to DQ signal lines of the control block for coupling the NVM chip; and controlling generation of the DQS signal based on the clock signal A1 and applying the generated DQS signal to DQS signal lines of the control component for coupling the NVM chip. In addition, the interface circuit controls DQS signal toggling based on clock signal A1 while controlling DQ signal lines coupling data to be written to the NVM chip to the data.

In the process of transmitting signals to the control part by the NVM chip, an interface circuit of the control part is required to generate RE signals and transmits the generated RE signals to the NVM chip; the NVM chip generates and transmits DQ and DQs signals to the control component, wherein the DQ signal content includes data read from the NVM chip. In order to generate the RE signal and collect the DQ signal and the DQs signal, the interface circuit of the embodiment of the present application performs the following step 602:

in step 602, the interface circuit controls generation of an RE signal based on a clock signal A2 and applies the generated RE signal to an RE signal line of the control unit for coupling to the NVM chip, wherein the frequency of the clock signal A2 is smaller than the frequency of the clock signal A1.

By way of example, the interface circuit is responsive to coupling the generated RE signal to the RE signal line of the NVM chip based on the clock signal A2 to collect the DQS signal from the DQS signal line of the NVM chip; and acquiring DQ signals from DQ signal lines of the NVM chip in response to the acquired DQS signal flip.

As another example, the interface circuit may select the clock signal for generating the DQ signal and the DQs signal, i.e., the clock signal A1 may be selected to control the DQ signal and the DQs signal; the same clock signal may also be selected as the RE signal generation, e.g., clock signal A2 providing the same clock frequency for the control unit to send signals to the NVM chip as the NVM chip to send signals to the control unit. When the control component sends signals to the NVM chip, the interface circuit controls and generates DQ signals based on the clock signal A2, and the generated DQ signals are applied to DQ signal lines of the control component for coupling the NVM chip; and controlling generation of the DQS signal based on the clock signal A2 and applying the generated DQS signal to DQS signal lines of the control component for coupling the NVM chip.

While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application. It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims

1. An interface circuit for operating a control component of an NVM chip, comprising: the DQ interface circuit is connected with the DQ signal PAD through the RE interface circuit; wherein,

the first clock provides a first clock signal, the second clock provides a second clock signal, and the frequency of the second clock signal is smaller than the frequency of the first clock signal;

the DQ interface circuit generates a DQ signal based on the first clock signal, and drives the DQ signal PAD based on the first clock signal to apply the DQ signal to DQ signal lines of the NVM chip;

The DQS interface circuit generating a DQS signal based on the first clock signal and driving the DQS signal PAD based on the first clock signal to apply the DQS signal to DQS signal lines of the control component for coupling to the NVM chip;

the RE interface circuit generates an RE signal based on the second clock signal and drives the RE signal PAD to apply the RE signal to RE signal lines of the NVM chip based on the second clock signal.

2. The interface circuit of claim 1, wherein the DQ interface circuit comprises a DQ physical layer circuit for transmitting and a DQ driver for transmitting; wherein,

the first clock provides the first clock signal for the DQ physical layer circuit for transmitting and the DQ driver for transmitting;

the DQ physical layer circuit for transmitting controls the DQ driver for transmitting to output data to be written to an NVM chip to the DQ signal PAD based on the first clock signal.

3. An interface circuit as claimed in claim 1 or 2, wherein the DQS interface circuit includes DQS physical layer circuit for transmitting and DQS driver for transmitting; the DQS physical layer for transmitting circuit controls the DQS driver for transmitting to output the generated DQS signal to the DQS signal PAD based on the first clock signal.

4. An interface circuit according to any of claims 1-3, wherein the RE interface circuit comprises: RE physical layer circuitry and RE driver; wherein,

the second clock provides the second clock signal to the RE physical layer circuit and the RE driver;

the RE physical layer circuit controls the RE driver to output the generated RE signal to the RE signal PAD based on the second clock signal.

5. An interface circuit for operating a control component of an NVM chip, comprising: a first clock, a second clock, a physical layer circuit for transmitting data, a DQS driver for transmitting, a DQ driver for transmitting, a physical layer circuit for receiving data, a DQS driver for receiving, a DQ driver for receiving, a RE driver, a DQ signal PAD, a DQS signal PAD, and a RE signal PAD; wherein,

the first clock couples the physical layer circuit for transmitting data, DQS driver for transmitting, and DQ driver for transmitting;

the second clock couples the physical layer circuit for receiving data, DQS driver for receiving, DQ driver for receiving and RE driver;

the DQ driver for transmitting and the DQ driver for receiving couple the DQ signal PAD;

The DQS driver for transmitting and the DQS driver for receiving couple the DQS signal PAD;

the RE driver is coupled to the RE signal PAD.

6. The interface circuit of claim 5, wherein

The physical layer circuit for transmitting data controls the DQS driver for transmitting to output the generated DQS signal to the DQS signal PAD based on the first clock signal, and controls the DQ driver for transmitting to output the generated DQ signal to the DQ signal PAD while the DQS signal is inverted.

7. The interface circuit of claim 5 or 6, wherein

The physical layer circuit for receiving data controls the RE driver to output the generated RE signal to the RE signal PAD based on the second clock signal, controls the DQS driver for receiving to receive the DQS signal from the DQS signal PAD, and controls the DQ driver for receiving transmission to acquire the DQ signal from the DQ signal PAD in response to the DQS signal toggling.

8. A method of operating an NVM chip, comprising:

generating a DQ signal based on the first clock signal control and applying the generated DQ signal to DQ signal lines of the control component for coupling the NVM chip; and controlling generation of a DQS signal based on the first clock signal and applying the generated DQS signal to DQS signal lines of the control component for coupling the NVM chip;

Generating an RE signal based on a second clock signal control, and applying the generated RE signal to an RE signal line of the control unit for coupling to the NVM chip, wherein the second clock signal has a frequency that is less than a frequency of the first clock signal.

9. The method of claim 8, wherein,

controlling the DQS signal to flip based on the first clock signal, simultaneously controlling DQ signal lines coupling data to be written to the NVM chip.

10. The method of claim 8 or 9, further comprising:

generating a DQ signal based on the second clock signal control and applying the generated DQ signal to DQ signal lines of the control component for coupling the NVM chip; and controlling generation of a DQS signal based on the second clock signal and applying the generated DQS signal to DQS signal lines of the control component for coupling the NVM chip.