CN117251315A - Memory performance test method, device, equipment and medium - Google Patents

Memory performance test method, device, equipment and medium Download PDF

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Publication number
CN117251315A
CN117251315A CN202211565860.0A CN202211565860A CN117251315A CN 117251315 A CN117251315 A CN 117251315A CN 202211565860 A CN202211565860 A CN 202211565860A CN 117251315 A CN117251315 A CN 117251315A
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memory
test
tested
thread
memory device
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王潇南
郝沁汾
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Wuxi Core Optical Interconnect Technology Research Institute Co ltd
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Wuxi Core Optical Interconnect Technology Research Institute Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2289—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by configuration test
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3442—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for planning or managing the needed capacity
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/3476—Data logging
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

The application discloses a memory performance test method, device, equipment and medium, wherein the method comprises the following steps: acquiring test parameters of the memory device to be tested; acquiring and judging the type of a current processor, and acquiring available physical cores of the current processor; creating a number of threads corresponding to the current available physical cores, and binding each thread to the ID of the corresponding available physical core; recording the time spent by each thread for reading the memory data with the same size from the memory device to be tested and the read times; and calculating the bandwidth and delay of the memory device to be tested according to the time spent by each thread and the reading times. The method solves the problems that the CPU performance is not utilized enough or the test result shakes due to the adoption of one CPU core when the memory is tested, and also solves the technical problems that the existing tool is not high in support degree of the memory delay test and poor in suitability.

Description

Memory performance test method, device, equipment and medium
Technical Field
The present application relates to the technical field of memory performance testing, and in particular, to a method, an apparatus, a device, and a medium for testing memory performance.
Background
In the hardware environment of a computer system, a memory device or a storage device is an extremely important component in the computer, and is used for storing data or other information required to be executed or calculated by a CPU, however, the bandwidth of acquiring data from a memory by the CPU and the delay of acquiring the data are important parameters for distinguishing the performance of the whole computer system, so it is very important to detect performance parameters such as the bandwidth and the delay of the memory device.
Currently, several common memory performance test tools are Intel MLC (Intel Memory Latency Checker) memory test tools issued by Intel corporation, and another LMbench is an open-source memory test tool, and another is also an open-source memory test tool Memtester. The Intel MLC test tool has complete functions and can test the bandwidth and delay performance of the memory, but the tool is mainly aimed at an Intel processor, and when the tool is used for testing the performance of the memory, the test result is floated each time under the same condition, and when the phase difference result is larger, a stable performance value is not calculated. Meanwhile, because the MLC tool is a closed source tool, a specific memory device cannot be tested (e.g. a new NVDIMM (Non-volatile Dual In-line Memory Module) memory is added In a local environment), and only a single test for the memory device cannot be performed. The other LMbench has a certain reference value, but since the latest update of the code is 28 days of 2005, the LMbench is too old in the age of the day-to-day variation of the performance of the memory device and the computer device, the test result of the memory delay has a certain access to the actual, and has the same defect as the MLC tool, and the memory device test cannot be specified. The Memtester tool also does not support memory latency testing as LMbench.
Disclosure of Invention
The purpose of the application is to provide a method, a device, equipment and a medium for testing the performance of a memory, which are used for solving the problems of insufficient CPU performance utilization or jitter of test results caused by adopting a CPU core when testing the memory, and also solving the problems of low support degree and poor suitability of the existing tool to the memory delay test.
The first aspect of the present application further provides a memory performance testing method, including:
acquiring test parameters of the memory device to be tested;
acquiring and judging the type of a current processor, and acquiring available physical cores of the current processor;
creating a number of threads corresponding to the current available physical cores, and binding each thread to the ID of the corresponding available physical core;
recording the time spent by each thread for reading the memory data with the same size from the memory device to be tested and the read times; and calculating the bandwidth and delay of the memory device to be tested according to the time spent and the reading times.
Optionally, before the obtaining the test parameters of the memory device to be tested, the method further includes:
judging whether the test parameters configured by the user meet preset specifications or not;
and if the preset specification is not met, prompting a user to input the test parameters of the specification.
Optionally, the obtaining the test parameters of the memory device to be tested includes:
and acquiring the memory device to be tested, the memory size of the memory to be tested and the physical memory starting address.
Optionally, the method further comprises:
detecting whether the memory device to be tested specified in the test parameters has a device file node or not;
if the equipment file node exists, directly opening the equipment file node; if the equipment file node does not exist, the equipment file node corresponding to the memory equipment designated in the test parameters is created, and the equipment file node is opened.
Optionally, the acquiring and judging the type of the current processor, and acquiring the available physical core of the current processor, includes:
acquiring the type of the current processor and judging whether the current processor is of an X86 architecture or not;
if yes, modifying the processor core configuration file and closing the hardware prefetcher;
if not, the available core number of the current processor is obtained.
Optionally, before creating the number of threads corresponding to the current available physical core and binding each thread to the ID of the corresponding available physical core, the method further includes:
and mapping the memory address of the memory device to be tested specified in the test parameters into the current process according to the size of the test memory.
Optionally, the recording of the time spent and the number of times that each thread finishes reading memory data of the same size from the memory device to be tested; and calculates the bandwidth and delay of the memory device to be tested according to the time spent and the reading times, including:
controlling each thread to read memory data with preset size from the memory device to be tested by taking the preset size as a unit;
recording the time spent by each thread for reading the memory data and the times for reading each unit of data;
calculating the test bandwidth of each thread according to the memory data read by each thread and the spent time; calculating the test delay of each thread according to the time spent by each thread for reading the memory data and the times for reading each unit data;
and calculating the average value of the test bandwidths and the test delays of all threads to obtain the bandwidths and the delays of the memory devices to be tested.
The second aspect of the application also provides a memory performance testing device, which comprises an acquisition module, a judgment module, a creation module and a calculation module which are connected in sequence;
the acquisition module is used for acquiring the test parameters of the memory device to be tested;
the judging module is used for acquiring and judging the type of the current processor and acquiring the available physical cores of the current processor;
the creation module is used for creating threads with the number corresponding to the current available physical cores and binding each thread to the ID of the corresponding available physical core;
the computing module is used for recording the time spent by each thread for reading the memory data with the same size from the memory device to be tested and the read times; and calculating the bandwidth and delay of the memory device to be tested according to the time spent and the reading times.
A third aspect of the present application provides a memory performance test apparatus, the apparatus comprising a processor and a memory:
the memory is used for storing program codes and transmitting the program codes to the processor;
the processor is configured to execute the steps of the memory performance testing method according to the first aspect according to the instructions in the program code.
A fourth aspect of the present application provides a computer readable storage medium for storing program code for executing the memory performance test method according to the first aspect.
From the above technical solutions, the embodiments of the present application have the following advantages:
the method for testing the memory performance comprises the following steps: acquiring test parameters of the memory device to be tested; acquiring and judging the type of a current processor, and acquiring available physical cores of the current processor; creating a number of threads corresponding to the current available physical cores, and binding each thread to the ID of the corresponding available physical core; recording the time spent by each thread for reading the memory data with the same size from the memory device to be tested and the read times; and calculating the bandwidth and delay of the memory device to be tested according to the time spent and the reading times. The performance test result of the memory device can be output by inputting the appointed memory device to be tested and indicating the corresponding test parameters by a user, and the using method of the tool and the meaning of the test result information are not needed to be known and learned in a large amount of time before the test tool is used; in addition, the type of the processor can be identified, and the processor can be adapted to the corresponding memory device according to the type of the processor; the stable test result is achieved by running independent test threads on each physical core, and the problem that the CPU performance is not utilized enough or the test result is dithered because one physical core is not used for running each time is avoided.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the embodiments of the application. The objectives and other advantages of the application will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flowchart of a first embodiment of a memory performance testing method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a thread and a core corresponding to each other in a memory performance testing method according to an embodiment of the present disclosure;
FIG. 3 is a flowchart of a second embodiment of a memory performance testing method according to an embodiment of the present application;
FIG. 4 is a system frame diagram as used in embodiments of the present application;
FIG. 5 is a schematic diagram illustrating an embodiment of a memory performance testing apparatus according to an embodiment of the present application;
fig. 6 is a schematic diagram of an embodiment of a memory performance testing apparatus according to an embodiment of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application, which are generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, as provided in the accompanying drawings, is not intended to limit the scope of the application, as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present application without making any inventive effort, are intended to be within the scope of the present application.
It should be noted that like reference numerals and letters refer to like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only to distinguish the description, and are not to be construed as indicating or implying relative importance.
Referring to fig. 1, a flowchart of a first embodiment of a memory performance testing method is shown. The memory performance test method is used in terminal equipment, mainly computers and the like. The memory performance test method comprises the following steps:
101. acquiring test parameters of the memory device to be tested;
the method and the device can acquire the designated memory device type of the memory device to be tested, the memory size of the test memory device, the physical memory starting address and the like, and further comprise other optional parameters. The method comprises the steps of analyzing the type of the memory device to be tested, and opening or creating a memory device file description node for the memory device according to the type (conventional disk, DDR device, NVDIMM device and the like) of the specified memory device to be used as a test object. The test memory size of the memory device may be 1024B or 2048B, which may also be tested according to the user requirements. The memory start address may be 0, and setting 0 indicates taking the memory start address of the device to be tested as a test start point.
102. Acquiring and judging the type of a current processor, and acquiring available physical cores of the current processor;
the method and the device can judge whether the current device is an X86 architecture processor or not, can judge whether the current processor is an Intel processor according to the type of the processor, and can close the corresponding hardware prefetcher if the current device is the X86 architecture processor, so that the influence of the hardware prefetcher on the reading speed of the appointed memory device is reduced, and the problem that the test cannot be carried out on the specific memory device is solved. In addition, the present application can also identify the physical cores that are currently available to the processor.
103. Creating a number of threads corresponding to the current available physical cores, and binding each thread to the ID of the corresponding available physical core;
the method and the device can create threads with the number corresponding to the current available physical cores, and bind each thread to the ID of the corresponding available physical core; so that each thread participates in reading memory data in the memory device to be tested, the corresponding relationship between a specific thread and a physical core is shown in fig. 2, and each thread in fig. 2 corresponds to one physical core. The number of physical cores may be 8 or 16, or may be determined according to the number of available physical cores in a specific CPU, and then the corresponding thread number may be determined according to the number of available physical cores.
104. Recording the time spent by each thread for reading the memory data with the same size from the memory device to be tested and the read times; and calculating the bandwidth and delay of the memory device to be tested according to the time spent and the reading times.
The method and the device can respectively test the time spent by each thread for reading the data from the memory device to be tested and the number of times of reading the data unit, and calculate the test bandwidth and the test delay of each thread through the time spent by reading the data and the number of times of reading the data unit. The test bandwidth and the test delay of each thread are respectively as follows:
test bandwidth = data size/time (units: byte/ns);
test delay = time/number of reads (unit: ns);
and then, the average value of the test bandwidths and the average value of the test delays can be obtained for the test bandwidths and the test delays of all threads:
test bandwidth average = test bandwidth accumulation per thread;
test delay average = test delay accumulation per thread;
the obtained average value is the bandwidth and the delay of the memory device to be tested.
According to the embodiment of the application, the performance test result of the memory device can be output by inputting the appointed memory device to be tested and indicating the corresponding test parameters by a user, so that a great deal of time is not needed before the test tool is used to know and learn the using method of the tool and the meaning of the test result information; in addition, the type of the processor can be identified, and the processor can be adapted to the corresponding memory device according to the type of the processor; the stable test result is achieved by running independent test threads on each physical core, and the problem that the CPU performance is underutilized or the test result shakes due to the fact that all physical cores are underutilized by running programs each time is avoided.
Referring to fig. 3, a flowchart of a second embodiment of a memory performance testing method is shown. The memory performance test method is used in terminal equipment, mainly computers and the like. The memory performance test method comprises the following steps:
201. judging whether the test parameters configured by the user meet preset specifications or not;
it should be noted that, the present application may input the test parameters (including the specified memory device type, the test memory size, the physical memory starting address, and other optional parameters) by the user; the system can compare the input test parameters of the user with the preset test parameter input specifications, and if the comparison results of the formats are inconsistent, a prompt signal is fed back to the user. The data specification format of the test parameters can be: memory device: DDR4 equipment, set up test memory: 1024B, memory start address: 0 (setting 0 means taking the memory starting address of the object device to be tested as the test starting point), if other parameters are also included, the data format of other parameters is also required to be compared.
202. And if the preset specification is not met, prompting a user to input the test parameters of the specification.
It should be noted that if the system determines that the input test parameters are not compliant, the specification is printed and the user is prompted to input according to the specification.
203. Acquiring memory equipment to be tested, the memory size of the memory to be tested and a physical memory starting address;
it should be noted that, according to the test parameters input by the user, the system may parse out the test information such as the type of the memory device, the test memory size and the start address. The designated memory device may be a DDR4 device to be tested, with a test memory size of 1024B and a memory start address of 0.
204. Detecting whether the memory device to be tested specified in the test parameters has a device file node or not;
it should be noted that, the parameter checking and analyzing module (Args Check & Analysis) of the present application provides adjustable testing options and selectable testing objects (memory devices), and the memory Device checking module (Mem Device Check) opens or creates a memory Device file description node for the specified memory Device according to the type of the specified memory Device (conventional disk, DDR Device, NVDIMM Device, etc.), so as to be used as a testing object, thereby solving the testing problem of the specified Device, and providing convenient adjustable testing parameters to achieve the purposes of more flexible, convenient and various testing.
The overall architecture of the system is shown in fig. 4, which depicts the major constituent modules in the software of the present invention. Including a parameter checking and parsing module (ars Check & Analysis), a memory Device Check module (Mem Device Check), a Device file creation module (FD Create), a CPU Check module (CPU Check), a prefetcher stop module (Disable Prefetcher), a CPU Core detection module (CPU Core Check), a memory mapping module (Mmap), and a thread creation module (Create Thread Pool).
205. If the equipment file node exists, directly opening the equipment file node; if the equipment file node does not exist, the equipment file node corresponding to the memory equipment designated in the test parameters is created, and the equipment file node is opened.
It should be noted that, in the present application, if the device file node exists, the device file node is directly opened; if the device file node does not exist, a device file creation module (FD Create) may Create the device file node corresponding to the memory device specified in the test parameter, and open the device file node.
Specifically, the problem that the existing tool cannot support the NVDIMM device or test inaccuracy can be solved by creating DAX (Direct Access) device nodes for the NVDIMM device and directly mapping the physical memory address of the NVDIMM to a memory space directly accessible by the current application process by utilizing a pmem module in the libnvdimm subsystem to cooperate with a DAX mode of mmap in the form of a DAX file without passing through a Page Cache.
When DDR4 equipment is used as the memory equipment to be tested, the file node/dev/mem can exist under the/dev directory, so that the memory equipment can be directly opened.
206. Acquiring the type of the current processor and judging whether the current processor is of an X86 architecture or not;
it should be noted that, in the system of the present application, the architecture of the current processor may be checked by a CPU Check module (CPU Check). For example, the shell command "branch" may be directly called to execute to determine whether it is an X86 architecture processor, if yes, the "modprobe msr" command is executed through a system call, and then 0X60628e2089 is written to the 0X1a0 position of the "msr" file in the CPU device directory, so as to close the Intel prefect function, and further avoid the influence of the prefect function on the memory reading speed.
207. If yes, modifying the processor core configuration file and closing the hardware prefetcher; if not, the available core number of the current processor is obtained.
When the current physical core is not an X86 architecture processor, the hardware prefetcher can be directly closed through the prefetcher stopping module (Disable Prefetcher), so that the influence of the hardware prefetcher on the reading speed of the appointed memory device is reduced, and the problem that the specific memory device cannot be tested is solved. If the architecture of the processor is not an X86 architecture processor, then the number of cores available to the current processor may be obtained through the get_nprocs () function.
208. Acquiring and judging the type of a current processor, and acquiring available physical cores of the current processor;
it should be noted that, the CPU Core detection module (CPU Core Check) in the present application may detect the number of physical cores of the current processor and obtain the number of physical cores that are currently available.
209. And mapping the memory address of the memory device to be tested specified in the test parameters into the current process according to the size of the test memory.
It should be noted that, the memory mapping module (Mmap) in the present application may map the memory address of the memory device to be tested to the current process according to the size of the test memory. Specifically, when the test memory is smaller than 4096Byte, the memory addresses of the memory device to be tested can be mapped to the current process according to the size of 4096 Byte; and obtaining the virtual memory starting address returned by the function.
210. Creating a number of threads corresponding to the current available physical cores, and binding each thread to the ID of the corresponding available physical core;
the thread creation module (Create Thread Pool) in the present application may create a corresponding number of threads after acquiring the current number of available physical cores. Specifically, each thread may use a CPU_ZERO (), CPU_SET (), pthread_security_np () combination to bind each thread to a corresponding physical core that has not yet been bound.
211. Controlling each thread to read memory data with preset size from the memory device to be tested by taking the preset size as a unit;
it should be noted that, in the present application, each thread may continuously read memory data with a preset size from the memory to be tested, and since the data read each time is limited to one unit, the memory data with the preset size needs to be read several times. Specifically, when the size of the read memory data is 1024B, and each unit data is 64B, 16 times are required for reading 1024B memory data.
Specifically, each unit (Cache Line) in the present application may be 64B, and each thread may create a structure body with a size of 64B, and create a linked list of data structures stored in the Cache Line unit; the specific size of the read data may be 1024B, and the number of nodes of the data structure linked list is 16 (1024/64=16).
212. Recording the time spent by each thread for reading the memory data and the times for reading each unit of data;
each thread in the present application may begin timing using a clock_gettime () function; each thread starts reading memory data by taking a Cache Line as a unit (64B) as a size; each thread may end the timer using a clock_gettime () function; the time it takes for each thread to read the data can be calculated and saved into the time consuming array of the host process before the thread is exited.
213. Calculating the test bandwidth of each thread according to the memory data read by each thread and the spent time; calculating the test delay of each thread according to the time spent by each thread for reading the memory data and the times for reading each unit data;
it should be noted that, the present application may test the time spent by each thread reading data from the memory device to be tested and the number of times of reading data units, and calculate the test bandwidth and the test delay of each thread through the time spent reading data and the number of times of reading data units. The test bandwidth and the test delay of each thread are respectively as follows:
test bandwidth = data size/time (units: byte/ns);
test delay = time/number of reads (unit: ns);
specifically, when the total read memory data size of each thread is 1024B and the read times are 16, and the total thread number is 16, then the test bandwidth and test delay of each thread test are:
test bandwidth=1024B/time used (unit: byte/ns);
test delay = time used/16 (units: ns).
214. And calculating the average value of the test bandwidths and the test delays of all threads to obtain the bandwidths and the delays of the memory devices to be tested.
In the application, the average value of the test bandwidth and the average value of the test delay can be obtained for the test bandwidths and the test delays of all threads:
test bandwidth average = test bandwidth accumulation per thread;
test delay average = test delay accumulation per thread;
the obtained average value is the bandwidth and the delay of the memory device to be tested.
Specifically, when the total read memory data size of each thread is 1024B and the read times are 16, and when the total thread number is 16, calculating the average value of the test results of each thread as follows:
test bandwidth average = test bandwidth accumulation sum/16;
test delay average = test delay accumulation and/or 16;
according to the embodiment of the application, the performance test result of the memory device can be output by inputting the appointed memory device to be tested and indicating the corresponding test parameters by a user, so that a great deal of time is not needed before the test tool is used to know and learn the using method of the tool and the meaning of the test result information; in addition, the method can simultaneously identify the type of the memory device through software and create a device node file for the memory device, so that the test problem of the memory device of the NVDIMM type is supported; the stable test result is achieved by running independent test threads on each physical core, and the problem that the CPU performance is not utilized enough or the test result is dithered because one physical core is not used for running each time is avoided. Through the memory bandwidth and delay test software, the memory performance of the appointed memory device can be tested very conveniently and efficiently, and meanwhile, the performance of the memory device can be visually seen through the output of the evaluation result of the program, so that a convenient and accurate memory performance test tool is provided.
Referring to fig. 5, a block diagram of a memory performance testing apparatus according to an embodiment of the present application is shown. According to the embodiment of the invention, the method comprises an acquisition module 301, a judgment module 302, a creation module 303 and a calculation module 304 which are connected in sequence, and specifically comprises the following steps:
an obtaining module 301, configured to obtain a test parameter of a memory device to be tested;
a judging module 302, configured to acquire and judge a current processor type, and acquire an available physical core of the current processor;
a creation module 303, configured to create a number of threads corresponding to the current available physical core, and bind each thread to an ID of the corresponding available physical core;
a calculation module 304, configured to record time spent by each thread for reading memory data of the same size from the memory device to be tested and the number of times of reading; and calculating the bandwidth and delay of the memory device to be tested according to the time spent and the reading times.
According to the method, the device and the system, the performance test result of the memory device can be output by inputting the appointed memory device to be tested and indicating the corresponding test parameters by a user, so that a great deal of time is not needed before the test tool is used to know and learn the using method of the tool and the meaning of the test result information; in addition, the type of the processor can be identified, and the processor can be adapted to the corresponding memory device according to the type of the processor; the stable test result is achieved by running independent test threads on each physical core, and the problem that the CPU performance is not utilized enough or the test result is dithered because one physical core is not used for running each time is avoided.
As shown in fig. 6, the present invention also discloses a memory performance test device, which includes a memory 41 and a processor 42, where the memory includes a program of a memory performance test method, and the program of the memory performance test method when executed by the processor implements the following steps:
acquiring test parameters of the memory device to be tested;
judging the type of the current processor and acquiring an available physical core of the current processor;
creating a number of threads corresponding to the current available physical cores, and binding each thread to the ID of the corresponding available physical core;
recording the time spent by each thread for reading the memory data with the same size from the memory device to be tested and the read times; and calculating the bandwidth and delay of the memory device to be tested according to the time spent and the reading times.
A fourth aspect of the present invention provides a readable storage medium having a memory performance test method program embodied therein, which when executed by a processor, implements the steps of the memory performance test method as described in any one of the preceding claims.
In the several embodiments provided in this application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above described device embodiments are only illustrative, e.g. the division of the units is only one logical function division, and there may be other divisions in practice, such as: multiple units or components may be combined or may be integrated into another system, or some features may be omitted, or not performed. In addition, the various components shown or discussed may be coupled or directly coupled or communicatively coupled to each other via some interface, whether indirectly coupled or communicatively coupled to devices or units, whether electrically, mechanically, or otherwise.
The units described above as separate components may or may not be physically separate, and components shown as units may or may not be physical units; can be located in one place or distributed to a plurality of network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in each embodiment of the present invention may be integrated in one processing unit, or each unit may be separately used as one unit, or two or more units may be integrated in one unit; the integrated units may be implemented in hardware or in hardware plus software functional units.
Those of ordinary skill in the art will appreciate that: all or part of the steps for implementing the above method embodiments may be implemented by hardware related to program instructions, and the foregoing program may be stored in a readable storage medium, where the program, when executed, performs steps including the above method embodiments; and the aforementioned storage medium includes: a mobile storage device, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk or an optical disk, or the like, which can store program codes.
Alternatively, the above-described integrated units of the present invention may be stored in a readable storage medium if implemented in the form of software functional modules and sold or used as separate products. Based on such understanding, the technical solution of the embodiments of the present invention may be embodied in essence or a part contributing to the prior art in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the embodiments of the present invention. And the aforementioned storage medium includes: a removable storage device, ROM, RAM, magnetic or optical disk, or other medium capable of storing program code.

Claims (10)

1. The method for testing the memory performance is characterized by comprising the following steps:
acquiring test parameters of the memory device to be tested;
acquiring and judging the type of a current processor, and acquiring available physical cores of the current processor;
creating a number of threads corresponding to the current available physical cores, and binding each thread to the ID of the corresponding available physical core;
recording the time spent by each thread for reading the memory data with the same size from the memory device to be tested and the read times; and calculating the bandwidth and delay of the memory device to be tested according to the time spent and the reading times.
2. The method for testing the performance of the memory according to claim 1, further comprising, before the step of obtaining the test parameters of the memory device to be tested:
judging whether the test parameters configured by the user meet preset specifications or not;
and if the preset specification is not met, prompting a user to input the test parameters of the specification.
3. The method for testing the performance of the memory according to claim 1, wherein the obtaining the test parameters of the memory device to be tested comprises:
and acquiring the memory device to be tested, the memory size of the memory to be tested and the physical memory starting address.
4. The memory performance testing method according to claim 1, further comprising:
detecting whether the memory device to be tested specified in the test parameters has a device file node or not;
if the equipment file node exists, directly opening the equipment file node; if the equipment file node does not exist, the equipment file node corresponding to the memory equipment designated in the test parameters is created, and the equipment file node is opened.
5. The method for testing the performance of the memory according to claim 1, wherein the acquiring and determining the type of the current processor and acquiring the available physical cores of the current processor comprise:
acquiring the type of the current processor and judging whether the current processor is of an X86 architecture or not;
if yes, modifying the processor core configuration file and closing the hardware prefetcher;
if not, the available core number of the current processor is obtained.
6. The method of claim 1, further comprising, prior to creating the number of threads corresponding to the current available physical core and binding each thread to the ID of the corresponding available physical core:
and mapping the memory address of the memory device to be tested specified in the test parameters into the current process according to the size of the test memory.
7. The method for testing memory performance according to claim 1, wherein the time spent and the number of times each thread reads memory data of the same size from the memory device to be tested are recorded; and calculates the bandwidth and delay of the memory device to be tested according to the time spent and the reading times, including:
controlling each thread to read memory data with preset size from the memory device to be tested by taking the preset size as a unit;
recording the time spent by each thread for reading the memory data and the times for reading each unit of data;
calculating the test bandwidth of each thread according to the memory data read by each thread and the spent time; calculating the test delay of each thread according to the time spent by each thread for reading the memory data and the times for reading each unit data;
and calculating the average value of the test bandwidths and the test delays of all threads to obtain the bandwidths and the delays of the memory devices to be tested.
8. The memory performance testing device is characterized by comprising an acquisition module, a judgment module, a creation module and a calculation module which are connected in sequence;
the acquisition module is used for acquiring the test parameters of the memory device to be tested;
the judging module is used for acquiring and judging the type of the current processor and acquiring the available physical core number of the current processor;
the creation module is used for creating threads with the number corresponding to the current available physical cores and binding each thread to the ID of the corresponding available physical core;
the computing module is used for recording the time spent by each thread for reading the memory data with the same size from the memory device to be tested and the read times; and calculating the bandwidth and delay of the memory device to be tested according to the time spent and the reading times.
9. A memory performance testing apparatus, the apparatus comprising a processor and a memory:
the memory is used for storing program codes and transmitting the program codes to the processor;
the processor is configured to execute the memory performance test method of any one of claims 1-7 according to instructions in the program code.
10. A computer readable storage medium, characterized in that the computer readable storage medium is for storing a program code for performing the memory performance test method according to any one of claims 1-7.
CN202211565860.0A 2022-12-07 2022-12-07 Memory performance test method, device, equipment and medium Pending CN117251315A (en)

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CN202211565860.0A CN117251315A (en) 2022-12-07 2022-12-07 Memory performance test method, device, equipment and medium

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202211565860.0A CN117251315A (en) 2022-12-07 2022-12-07 Memory performance test method, device, equipment and medium

Publications (1)

Publication Number Publication Date
CN117251315A true CN117251315A (en) 2023-12-19

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